225 lines
8.0 KiB
VHDL
225 lines
8.0 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:35:02 05/06/2020
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-- Design Name:
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-- Module Name: Sweep - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Sweep is
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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NPOINTS : in STD_LOGIC_VECTOR (12 downto 0);
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CONFIG_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
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CONFIG_DATA : in STD_LOGIC_VECTOR (95 downto 0);
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USER_NSAMPLES : in STD_LOGIC_VECTOR (9 downto 0);
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NSAMPLES : out STD_LOGIC_VECTOR (9 downto 0);
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SAMPLING_BUSY : in STD_LOGIC;
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SAMPLING_DONE : in STD_LOGIC;
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START_SAMPLING : out STD_LOGIC;
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PORT_SELECT : out STD_LOGIC;
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BAND_SELECT : out STD_LOGIC;
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-- fixed part of source/LO registers
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MAX2871_DEF_4 : in STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_3 : in STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_1 : in STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_0 : in STD_LOGIC_VECTOR (31 downto 0);
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-- assembled source/LO registers
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SOURCE_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
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SOURCE_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
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SOURCE_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
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SOURCE_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
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RELOAD_PLL_REGS : out STD_LOGIC;
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PLL_RELOAD_DONE : in STD_LOGIC;
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PLL_LOCKED : in STD_LOGIC;
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SWEEP_HALTED : out STD_LOGIC;
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SWEEP_RESUME : in STD_LOGIC;
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ATTENUATOR : out STD_LOGIC_VECTOR(6 downto 0);
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SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
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--SETTLING_TIME : in STD_LOGIC_VECTOR (15 downto 0);
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EXCITE_PORT1 : in STD_LOGIC;
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EXCITE_PORT2 : in STD_LOGIC;
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-- Debug signals
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DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
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);
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end Sweep;
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architecture Behavioral of Sweep is
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signal point_cnt : unsigned(12 downto 0);
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type Point_states is (TriggerSetup, SettingUp, SettlingPort1, ExcitingPort1, SettlingPort2, ExcitingPort2, Done);
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signal state : Point_states;
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signal settling_cnt : unsigned(15 downto 0);
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signal settling_time : unsigned(15 downto 0);
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begin
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CONFIG_ADDRESS <= std_logic_vector(point_cnt);
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-- assemble registers
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-- source register 0: N divider and fractional division value
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SOURCE_REG_0 <= MAX2871_DEF_0(31) & "000000000" & CONFIG_DATA(6 downto 0) & CONFIG_DATA(27 downto 16) & "000";
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-- source register 1: Modulus value
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SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & CONFIG_DATA(39 downto 28) & "001";
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-- source register 3: VCO selection
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SOURCE_REG_3 <= CONFIG_DATA(12 downto 7) & MAX2871_DEF_3(25 downto 3) & "011";
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-- output power A passed on from default registers, output B disabled
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SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & CONFIG_DATA(15 downto 13) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5 downto 3) & "100";
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-- LO register 0: N divider and fractional division value
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LO_REG_0 <= MAX2871_DEF_0(31) & "000000000" & CONFIG_DATA(54 downto 48) & CONFIG_DATA(75 downto 64) & "000";
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-- LO register 1: Modulus value
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LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & CONFIG_DATA(87 downto 76) & "001";
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-- LO register 3: VCO selection
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LO_REG_3 <= CONFIG_DATA(60 downto 55) & MAX2871_DEF_3(25 downto 3) & "011";
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-- both outputs enabled at -1dbm
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LO_REG_4 <= MAX2871_DEF_4(31 downto 23) & CONFIG_DATA(63 downto 61) & MAX2871_DEF_4(19 downto 9) & "101101100";
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ATTENUATOR <= CONFIG_DATA(46 downto 40);
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SOURCE_FILTER <= CONFIG_DATA(89 downto 88);
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BAND_SELECT <= CONFIG_DATA(47);
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settling_time <= to_unsigned(2048, 16) when CONFIG_DATA(94 downto 93) = "00" else -- 20us
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to_unsigned(6144, 16) when CONFIG_DATA(94 downto 93) = "01" else -- 60us
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to_unsigned(18432, 16) when CONFIG_DATA(94 downto 93) = "10" else -- 180us
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to_unsigned(55296, 16); -- 540us
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NSAMPLES <= USER_NSAMPLES when CONFIG_DATA(92 downto 90) = "000" else
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std_logic_vector(to_unsigned(1, 10)) when CONFIG_DATA(92 downto 90) = "001" else
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std_logic_vector(to_unsigned(3, 10)) when CONFIG_DATA(92 downto 90) = "010" else
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std_logic_vector(to_unsigned(7, 10)) when CONFIG_DATA(92 downto 90) = "011" else
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std_logic_vector(to_unsigned(24, 10)) when CONFIG_DATA(92 downto 90) = "100" else
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std_logic_vector(to_unsigned(71, 10)) when CONFIG_DATA(92 downto 90) = "101" else
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std_logic_vector(to_unsigned(238, 10)) when CONFIG_DATA(92 downto 90) = "110" else
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std_logic_vector(to_unsigned(714, 10));
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DEBUG_STATUS(10 downto 8) <= "000" when state = TriggerSetup else
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"001" when state = SettingUp else
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"010" when state = SettlingPort1 else
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"011" when state = ExcitingPort1 else
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"100" when state = SettlingPort2 else
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"101" when state = ExcitingPort2 else
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"110" when state = Done else
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"111";
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DEBUG_STATUS(7) <= PLL_RELOAD_DONE;
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DEBUG_STATUS(6) <= PLL_RELOAD_DONE and PLL_LOCKED;
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DEBUG_STATUS(5) <= SAMPLING_BUSY;
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DEBUG_STATUS(4 downto 0) <= (others => '0');
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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point_cnt <= (others => '0');
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state <= TriggerSetup;
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START_SAMPLING <= '0';
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RELOAD_PLL_REGS <= '0';
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SWEEP_HALTED <= '0';
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else
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case state is
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when TriggerSetup =>
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RELOAD_PLL_REGS <= '1';
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if PLL_RELOAD_DONE = '0' then
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state <= SettingUp;
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end if;
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when SettingUp =>
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-- highest bit in CONFIG_DATA determines whether the sweep should be halted prior to sampling
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SWEEP_HALTED <= CONFIG_DATA(95);
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RELOAD_PLL_REGS <= '0';
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if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
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-- check if halted sweep is resumed
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if CONFIG_DATA(95) = '0' or SWEEP_RESUME = '1' then
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SWEEP_HALTED <= '0';
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if EXCITE_PORT1 = '1' then
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state <= SettlingPort1;
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elsif EXCITE_PORT2 = '1' then
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state <= SettlingPort2;
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else
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state <= Done;
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end if;
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settling_cnt <= settling_time;
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end if;
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end if;
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when SettlingPort1 =>
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PORT_SELECT <= '1';
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-- wait for settling time to elapse
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if settling_cnt > 0 then
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settling_cnt <= settling_cnt - 1;
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else
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START_SAMPLING <= '1';
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if SAMPLING_BUSY = '1' then
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state <= ExcitingPort1;
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end if;
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end if;
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when ExcitingPort1 =>
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-- wait for sampling to finish
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START_SAMPLING <= '0';
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if SAMPLING_BUSY = '0' then
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if EXCITE_PORT2 = '1' then
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state <= SettlingPort2;
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else
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state <= Done;
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end if;
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settling_cnt <= unsigned(SETTLING_TIME);
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end if;
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when SettlingPort2 =>
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PORT_SELECT <= '0';
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-- wait for settling time to elapse
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if settling_cnt > 0 then
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settling_cnt <= settling_cnt - 1;
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else
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START_SAMPLING <= '1';
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if SAMPLING_BUSY = '1' then
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state <= ExcitingPort2;
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end if;
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end if;
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when ExcitingPort2 =>
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-- wait for sampling to finish
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START_SAMPLING <= '0';
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if SAMPLING_BUSY = '0' then
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if point_cnt < unsigned(NPOINTS) then
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point_cnt <= point_cnt + 1;
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state <= TriggerSetup;
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PORT_SELECT <= '1';
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else
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point_cnt <= (others => '0');
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state <= Done;
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end if;
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end if;
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when others =>
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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