114 lines
2.9 KiB
VHDL
114 lines
2.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:14:17 03/05/2019
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-- Design Name:
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-- Module Name: spi_slave - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity spi_slave is
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generic ( W : integer);
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Port ( SPI_CLK : in STD_LOGIC;
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MISO : out STD_LOGIC;
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MOSI : in STD_LOGIC;
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CS : in STD_LOGIC;
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BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
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BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
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CLK : in STD_LOGIC;
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COMPLETE : out STD_LOGIC
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-- RISING_TOGGLE : inout STD_LOGIC;
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-- FALLING_TOGGLE : inout STD_LOGIC
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);
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end spi_slave;
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architecture Behavioral of spi_slave is
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signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0);
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signal mosi_buffer : STD_LOGIC_VECTOR (W-2 downto 0);
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signal data_valid : STD_LOGIC_VECTOR(2 downto 0);
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signal data_synced : STD_LOGIC_VECTOR(2 downto 0);
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signal data : STD_LOGIC_VECTOR(W-1 downto 0);
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signal bit_cnt : STD_LOGIC_VECTOR(W-2 downto 0);
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begin
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process(CLK)
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begin
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if rising_edge(CLK) then
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data_valid(2 downto 1) <= data_valid(1 downto 0);
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if data_valid(2) = '1' then
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if data_synced(0) = '0' then
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BUF_OUT <= data;
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COMPLETE <= '1';
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data_synced(0) <= '1';
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else
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COMPLETE <= '0';
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end if;
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else
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COMPLETE <= '0';
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data_synced(0) <= '0';
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end if;
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end if;
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end process;
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MISO <= miso_buffer(W-1) when CS = '0' else 'Z';
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slave_in: process(SPI_CLK)
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begin
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if rising_edge(SPI_CLK) then
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-- FALLING_TOGGLE <= not FALLING_TOGGLE;
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data_synced(2 downto 1) <= data_synced(1 downto 0);
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if bit_cnt(W-2) = '1' then
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-- this was the last bit
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data_valid(0) <= '1';
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data <= mosi_buffer(W-2 downto 0) & MOSI;
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else
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if data_valid(0) = '1' and data_synced(2) = '1' then
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data_valid(0) <= '0';
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end if;
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mosi_buffer <= mosi_buffer(W-3 downto 0) & MOSI;
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end if;
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end if;
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end process;
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slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt)
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begin
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if CS = '1' then
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bit_cnt <= (others => '0');
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miso_buffer <= BUF_IN;
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elsif falling_edge(SPI_CLK) then
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if bit_cnt(W-2) = '0' then
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bit_cnt <= bit_cnt(W-3 downto 0) & '1';
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miso_buffer <= miso_buffer(W-2 downto 0) & '0';
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else
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bit_cnt <= (others => '0');
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miso_buffer <= BUF_IN;
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end if;
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end if;
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end process;
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end Behavioral; |