7e6de49721
When USE_DEBUG_PINS is enabled and debug session is open, their pin initialization makes debug probe to lost session. As these pins are not used, let's disable it by default.
387 lines
11 KiB
C++
387 lines
11 KiB
C++
#include <HW_HAL.hpp>
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#include "Hardware.hpp"
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#include "Si5351C.hpp"
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#include "max2871.hpp"
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#include "FPGA/FPGA.hpp"
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#include "Exti.hpp"
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#include "VNA.hpp"
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#include "Manual.hpp"
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#include "SpectrumAnalyzer.hpp"
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#include <cstring>
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "HW"
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#include "Log.h"
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static uint32_t extOutFreq = 0;
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static bool extRefInUse = false;
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HW::Mode activeMode;
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static bool unlevel = false;
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static Protocol::ReferenceSettings ref;
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static uint32_t lastISR;
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using namespace HWHAL;
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static void HaltedCallback() {
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switch(activeMode) {
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case HW::Mode::VNA:
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VNA::SweepHalted();
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break;
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default:
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break;
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}
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}
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static void ReadComplete(const FPGA::SamplingResult &result) {
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bool needs_work = false;
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switch(activeMode) {
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case HW::Mode::VNA:
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needs_work = VNA::MeasurementDone(result);
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break;
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case HW::Mode::Manual:
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needs_work = Manual::MeasurementDone(result);
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break;
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case HW::Mode::SA:
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needs_work = SA::MeasurementDone(result);
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break;
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default:
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break;
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}
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if(needs_work) {
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STM::DispatchToInterrupt(HW::Work);
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}
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}
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static void FPGA_Interrupt(void*) {
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FPGA::InitiateSampleRead(ReadComplete);
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lastISR = HAL_GetTick();
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}
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void HW::Work() {
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switch(activeMode) {
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case HW::Mode::VNA:
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VNA::Work();
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break;
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case HW::Mode::Manual:
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Manual::Work();
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break;
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case HW::Mode::SA:
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SA::Work();
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break;
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default:
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break;
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}
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}
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bool HW::Init() {
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#if USE_DEBUG_PINS
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// initialize debug pins
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GPIO_InitTypeDef gpio;
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gpio.Pin = DEBUG1_PIN;
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gpio.Mode = GPIO_MODE_OUTPUT_PP;
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gpio.Speed = GPIO_SPEED_HIGH;
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HAL_GPIO_Init(DEBUG1_GPIO, &gpio);
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gpio.Pin = DEBUG2_PIN;
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HAL_GPIO_Init(DEBUG2_GPIO, &gpio);
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#endif
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LOG_DEBUG("Initializing...");
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activeMode = Mode::Idle;
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Si5351.Init();
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// Use Si5351 to generate reference frequencies for other PLLs and ADC
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Si5351.SetPLL(Si5351C::PLL::A, HW::SI5351CPLLConstantFrequency, Si5351C::PLLSource::XTAL);
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while(!Si5351.Locked(Si5351C::PLL::A));
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Si5351.SetPLL(Si5351C::PLL::B, HW::SI5351CPLLAlignedFrequency, Si5351C::PLLSource::XTAL);
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while(!Si5351.Locked(Si5351C::PLL::B));
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extRefInUse = 0;
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extOutFreq = 0;
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Si5351.Disable(SiChannel::ReferenceOut);
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// Both MAX2871 get a 100MHz reference
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// Si5351.SetBypass(SiChannel::Source, Si5351C::PLLSource::XTAL);
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Si5351.SetCLK(SiChannel::Source, HW::PLLRef, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Source);
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// Si5351.SetBypass(SiChannel::LO1, Si5351C::PLLSource::XTAL);
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Si5351.SetCLK(SiChannel::LO1, HW::PLLRef, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::LO1);
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// 16MHz FPGA clock
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Si5351.SetCLK(SiChannel::FPGA, HW::FPGAClkInFrequency, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::FPGA);
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// Generate second LO with Si5351
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Si5351.SetCLK(SiChannel::Port1LO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port1LO2);
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Si5351.SetCLK(SiChannel::Port2LO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port2LO2);
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Si5351.SetCLK(SiChannel::RefLO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::RefLO2);
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// PLL reset appears to realign phases of clock signals
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Si5351.ResetPLL(Si5351C::PLL::B);
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LOG_DEBUG("Si5351 locked");
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// FPGA clock is now present, can initialize
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if (!FPGA::Init(HaltedCallback)) {
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LOG_ERR("Aborting due to uninitialized FPGA");
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return false;
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}
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// Set default ADC samplerate
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, HW::ADCprescaler);
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// Set phase increment according to
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, HW::DFTphaseInc);
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Exti::SetCallback(FPGA_INTR_GPIO_Port, FPGA_INTR_Pin, Exti::EdgeType::Rising, Exti::Pull::Down, FPGA_Interrupt);
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// Initialize PLLs and build VCO maps
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// enable source synthesizer
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FPGA::Enable(FPGA::Periphery::SourceChip);
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FPGA::SetMode(FPGA::Mode::SourcePLL);
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Source.Init(HW::PLLRef, false, 1, false);
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Source.SetPowerOutA(MAX2871::Power::n4dbm);
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// output B is not used
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Source.SetPowerOutB(MAX2871::Power::n4dbm, false);
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if(!Source.BuildVCOMap()) {
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LOG_WARN("Source VCO map failed");
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} else {
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LOG_INFO("Source VCO map complete");
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}
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Source.SetFrequency(1000000000);
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Source.UpdateFrequency();
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LOG_DEBUG("Source temp: %u", Source.GetTemp());
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// disable source synthesizer/enable LO synthesizer
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FPGA::SetMode(FPGA::Mode::FPGA);
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FPGA::Disable(FPGA::Periphery::SourceChip);
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FPGA::Enable(FPGA::Periphery::LO1Chip);
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FPGA::SetMode(FPGA::Mode::LOPLL);
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LO1.Init(HW::PLLRef, false, 1, false);
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LO1.SetPowerOutA(MAX2871::Power::n4dbm);
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LO1.SetPowerOutB(MAX2871::Power::n4dbm);
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if(!LO1.BuildVCOMap()) {
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LOG_WARN("LO1 VCO map failed");
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} else {
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LOG_INFO("LO1 VCO map complete");
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}
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LO1.SetFrequency(1000000000 + IF1);
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LO1.UpdateFrequency();
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LOG_DEBUG("LO temp: %u", LO1.GetTemp());
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FPGA::SetMode(FPGA::Mode::FPGA);
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// disable both synthesizers
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FPGA::Disable(FPGA::Periphery::LO1Chip);
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FPGA::WriteMAX2871Default(Source.GetRegisters());
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LOG_INFO("Initialized");
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FPGA::Enable(FPGA::Periphery::ReadyLED);
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Ref::update();
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return true;
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}
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void HW::SetMode(Mode mode) {
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if(activeMode == mode) {
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// already the correct mode
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return;
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}
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unlevel = false;
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switch(activeMode) {
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case Mode::Manual:
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Manual::Stop();
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break;
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case Mode::VNA:
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VNA::Stop();
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break;
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default:
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break;
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}
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if(mode != Mode::Idle) {
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// do a full initialization when switching directly between modes
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HW::Init();
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lastISR = HAL_GetTick();
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}
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SetIdle();
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activeMode = mode;
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}
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bool HW::GetTemps(uint8_t *source, uint8_t *lo) {
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FPGA::SetMode(FPGA::Mode::SourcePLL);
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*source = Source.GetTemp();
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FPGA::SetMode(FPGA::Mode::LOPLL);
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*lo = LO1.GetTemp();
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FPGA::SetMode(FPGA::Mode::FPGA);
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return true;
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}
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void HW::SetIdle() {
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unlevel = false;
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FPGA::AbortSweep();
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FPGA::SetMode(FPGA::Mode::FPGA);
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FPGA::Enable(FPGA::Periphery::SourceChip, false);
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FPGA::Enable(FPGA::Periphery::SourceRF, false);
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FPGA::Enable(FPGA::Periphery::LO1Chip, false);
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FPGA::Enable(FPGA::Periphery::LO1RF, false);
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FPGA::Enable(FPGA::Periphery::Amplifier, false);
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FPGA::Enable(FPGA::Periphery::Port1Mixer, false);
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FPGA::Enable(FPGA::Periphery::Port2Mixer, false);
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FPGA::Enable(FPGA::Periphery::RefMixer, false);
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FPGA::Enable(FPGA::Periphery::PortSwitch, false);
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}
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HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool applyCorrections, bool port2) {
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if (applyCorrections) {
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auto correction = Cal::SourceCorrection(freq);
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if (port2) {
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cdbm += correction.port2;
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} else {
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cdbm += correction.port1;
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}
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}
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AmplitudeSettings ret;
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if(freq < BandSwitchFrequency) {
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if(cdbm <= HW::LowBandMinPower) {
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// can use the low power setting
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ret.lowBandPower = Si5351C::DriveStrength::mA2;
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cdbm -= HW::LowBandMinPower;
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} else {
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// needs the high power setting
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ret.lowBandPower = Si5351C::DriveStrength::mA8;
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cdbm -= HW::LowBandMaxPower;
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}
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} else {
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if(cdbm <= HW::HighBandMinPower) {
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// can use the low power setting
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ret.highBandPower = MAX2871::Power::n4dbm;
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cdbm -= HW::HighBandMinPower;
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} else {
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// needs the high power setting
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ret.highBandPower = MAX2871::Power::p5dbm;
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cdbm -= HW::HighBandMaxPower;
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}
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}
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// calculate required attenuation
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int16_t attval = -cdbm / 25;
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if(attval > 127) {
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attval = 127;
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ret.unlevel = true;
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} else if(attval < 0) {
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attval = 0;
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ret.unlevel = true;
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} else {
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ret.unlevel = false;
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}
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ret.attenuator = attval;
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return ret;
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}
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bool HW::TimedOut() {
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constexpr uint32_t timeout = 1000;
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if(activeMode != Mode::Idle && HAL_GetTick() - lastISR > timeout) {
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return true;
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} else {
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return false;
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}
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}
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void HW::SetOutputUnlevel(bool unlev) {
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unlevel = unlev;
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}
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void HW::fillDeviceInfo(Protocol::DeviceInfo *info, bool updateEvenWhenBusy) {
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// copy constant default values
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memcpy(info, &HW::Info, sizeof(HW::Info));
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if(activeMode == Mode::Idle || updateEvenWhenBusy) {
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// updating values from FPGA allowed
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// read PLL temperatures
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uint8_t tempSource, tempLO;
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GetTemps(&tempSource, &tempLO);
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LOG_INFO("PLL temperatures: %u/%u", tempSource, tempLO);
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// Read ADC min/max
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auto limits = FPGA::GetADCLimits();
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LOG_INFO("ADC limits: P1: %d/%d P2: %d/%d R: %d/%d",
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limits.P1min, limits.P1max, limits.P2min, limits.P2max,
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limits.Rmin, limits.Rmax);
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#define ADC_LIMIT 30000
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if(limits.P1min < -ADC_LIMIT || limits.P1max > ADC_LIMIT
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|| limits.P2min < -ADC_LIMIT || limits.P2max > ADC_LIMIT
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|| limits.Rmin < -ADC_LIMIT || limits.Rmax > ADC_LIMIT) {
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info->ADC_overload = true;
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} else {
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info->ADC_overload = false;
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}
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auto status = FPGA::GetStatus();
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info->LO1_locked = (status & (int) FPGA::Interrupt::LO1Unlock) ? 0 : 1;
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info->source_locked = (status & (int) FPGA::Interrupt::SourceUnlock) ? 0 : 1;
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info->extRefAvailable = Ref::available();
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info->extRefInUse = extRefInUse;
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info->unlevel = unlevel;
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info->temp_LO1 = tempLO;
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info->temp_source = tempSource;
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FPGA::ResetADCLimits();
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}
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info->temp_MCU = STM::getTemperature();
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}
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bool HW::Ref::available() {
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return Si5351.ExtCLKAvailable();
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}
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void HW::Ref::set(Protocol::ReferenceSettings s) {
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ref = s;
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}
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bool HW::Ref::usingExternal() {
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return extRefInUse;
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}
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void HW::Ref::update() {
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if(extOutFreq != ref.ExtRefOuputFreq) {
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extOutFreq = ref.ExtRefOuputFreq;
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if(extOutFreq == 0) {
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Si5351.Disable(SiChannel::ReferenceOut);
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LOG_INFO("External reference output disabled");
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} else {
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Si5351.SetCLK(SiChannel::ReferenceOut, extOutFreq, Si5351C::PLL::A);
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Si5351.Enable(SiChannel::ReferenceOut);
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LOG_INFO("External reference output set to %luHz", extOutFreq);
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}
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}
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bool useExternal = ref.UseExternalRef;
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if (ref.AutomaticSwitch) {
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useExternal = Ref::available();
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}
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if(useExternal != extRefInUse) {
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// switch between internal and external reference
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extRefInUse = useExternal;
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if(extRefInUse) {
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if(!Ref::available()) {
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LOG_WARN("Forced switch to external reference but no signal detected");
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}
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Si5351.ConfigureCLKIn(10000000);
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Si5351.SetPLL(Si5351C::PLL::A, HW::SI5351CPLLConstantFrequency, Si5351C::PLLSource::CLKIN);
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Si5351.SetPLL(Si5351C::PLL::B, HW::SI5351CPLLAlignedFrequency, Si5351C::PLLSource::CLKIN);
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LOG_INFO("Switched to external reference");
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FPGA::Enable(FPGA::Periphery::ExtRefLED);
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} else {
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Si5351.SetPLL(Si5351C::PLL::A, HW::SI5351CPLLConstantFrequency, Si5351C::PLLSource::XTAL);
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Si5351.SetPLL(Si5351C::PLL::B, HW::SI5351CPLLAlignedFrequency, Si5351C::PLLSource::XTAL);
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LOG_INFO("Switched to internal reference");
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FPGA::Disable(FPGA::Periphery::ExtRefLED);
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}
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}
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constexpr uint32_t lock_timeout = 100;
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uint32_t start = HAL_GetTick();
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while(!Si5351.Locked(Si5351C::PLL::A) || !Si5351.Locked(Si5351C::PLL::A)) {
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if(HAL_GetTick() - start > lock_timeout) {
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LOG_ERR("Clock distributor PLLs failed to lock");
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return;
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}
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}
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}
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