143 lines
3.3 KiB
Plaintext
143 lines
3.3 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.6
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# Date: Tue May 5 15:36:58 2020
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:dds_compiler:4.0
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = tqg144
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT DDS_Compiler xilinx.com:ip:dds_compiler:4.0
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# END Select
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# BEGIN Parameters
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CSET amplitude_mode=Full_Range
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CSET channel_pin=false
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CSET channels=1
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CSET clock_enable=false
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CSET component_name=SinCos
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CSET dds_clock_rate=100
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CSET dsp48_use=Minimal
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CSET explicit_period=false
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CSET frequency_resolution=0.4
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CSET gui_behaviour=Coregen
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CSET has_phase_out=false
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CSET latency=6
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CSET latency_configuration=Auto
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CSET memory_type=Auto
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CSET negative_cosine=false
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CSET negative_sine=false
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CSET noise_shaping=None
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CSET optimization_goal=Auto
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CSET output_frequency1=0
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CSET output_frequency10=0
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CSET output_frequency11=0
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CSET output_frequency12=0
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CSET output_frequency13=0
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CSET output_frequency14=0
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CSET output_frequency15=0
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CSET output_frequency16=0
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CSET output_frequency2=0
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CSET output_frequency3=0
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CSET output_frequency4=0
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CSET output_frequency5=0
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CSET output_frequency6=0
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CSET output_frequency7=0
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CSET output_frequency8=0
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CSET output_frequency9=0
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CSET output_selection=Sine_and_Cosine
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CSET output_width=16
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CSET parameter_entry=Hardware_Parameters
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CSET partspresent=SIN_COS_LUT_only
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CSET period=1
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CSET phase_increment=Fixed
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CSET phase_offset=None
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CSET phase_offset_angles1=0
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CSET phase_offset_angles10=0
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CSET phase_offset_angles11=0
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CSET phase_offset_angles12=0
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CSET phase_offset_angles13=0
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CSET phase_offset_angles14=0
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CSET phase_offset_angles15=0
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CSET phase_offset_angles16=0
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CSET phase_offset_angles2=0
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CSET phase_offset_angles3=0
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CSET phase_offset_angles4=0
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CSET phase_offset_angles5=0
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CSET phase_offset_angles6=0
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CSET phase_offset_angles7=0
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CSET phase_offset_angles8=0
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CSET phase_offset_angles9=0
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CSET phase_width=12
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CSET pinc1=0
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CSET pinc10=0
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CSET pinc11=0
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CSET pinc12=0
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CSET pinc13=0
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CSET pinc14=0
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CSET pinc15=0
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CSET pinc16=0
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CSET pinc2=0
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CSET pinc3=0
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CSET pinc4=0
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CSET pinc5=0
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CSET pinc6=0
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CSET pinc7=0
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CSET pinc8=0
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CSET pinc9=0
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CSET poff1=0
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CSET poff10=0
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CSET poff11=0
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CSET poff12=0
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CSET poff13=0
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CSET poff14=0
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CSET poff15=0
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CSET poff16=0
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CSET poff2=0
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CSET poff3=0
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CSET poff4=0
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CSET poff5=0
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CSET poff6=0
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CSET poff7=0
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CSET poff8=0
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CSET poff9=0
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CSET por_mode=false
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CSET rdy=false
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CSET rfd=false
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CSET sclr_pin=false
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CSET spurious_free_dynamic_range=36
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-08-28T14:48:35Z
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# END Extra information
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GENERATE
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# CRC: dc69a097
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