| .. |
|
ipcore_dir
|
Allow different source PLL power per sweep point, add power range to sweep
|
2021-07-09 22:25:54 +02:00 |
|
DFT.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
Flattop.dat
|
Window coefficient files added
|
2020-10-29 20:07:41 +01:00 |
|
Hann.dat
|
Window coefficient files added
|
2020-10-29 20:07:41 +01:00 |
|
Kaiser.dat
|
Window coefficient files added
|
2020-10-29 20:07:41 +01:00 |
|
MAX2871.vhd
|
FPGA project adapted to new pinout
|
2020-08-30 16:19:18 +02:00 |
|
MCP33131.vhd
|
Improved spectrum analyzer mode
|
2020-09-17 19:54:03 +02:00 |
|
ResetDelay.vhd
|
Basic DFT spectrum analysis working
|
2020-11-08 14:38:31 +01:00 |
|
Sampling.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
spi_slave.vhd
|
Test of DFT implementation in FPGA
|
2020-11-08 14:38:31 +01:00 |
|
SPIConfig.vhd
|
Basic DFT spectrum analysis working
|
2020-11-08 14:38:31 +01:00 |
|
Sweep.vhd
|
Allow different source PLL power per sweep point, add power range to sweep
|
2021-07-09 22:25:54 +02:00 |
|
Synchronizer.vhd
|
FPGA project adapted to new pinout
|
2020-08-30 16:19:18 +02:00 |
|
Test_DFT.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
Test_MAX2871.vhd
|
FPGA project adapted to new pinout
|
2020-08-30 16:19:18 +02:00 |
|
Test_MCP33131.vhd
|
Improved spectrum analyzer mode
|
2020-09-17 19:54:03 +02:00 |
|
Test_PLL.vhd
|
FPGA project adapted to new pinout
|
2020-08-30 16:19:18 +02:00 |
|
Test_Sampling.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
Test_SinCos.vhd
|
FPGA project adapted to new pinout
|
2020-08-30 16:19:18 +02:00 |
|
Test_SPI.vhd
|
Test of DFT implementation in FPGA
|
2020-11-08 14:38:31 +01:00 |
|
Test_SPICommands.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
Test_Window.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
Test_Windowing.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
top.bin
|
Allow different source PLL power per sweep point, add power range to sweep
|
2021-07-09 22:25:54 +02:00 |
|
top.ucf
|
Test of DFT implementation in FPGA
|
2020-11-08 14:38:31 +01:00 |
|
top.vhd
|
rename clk160 -> clk_pll
|
2021-11-19 21:18:54 +01:00 |
|
VNA.gise
|
Allow different source PLL power per sweep point, add power range to sweep
|
2021-07-09 22:25:54 +02:00 |
|
VNA.xise
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
|
window.vhd
|
Windowing option added to sampling
|
2020-09-16 16:13:06 +02:00 |
|
Windowing.vhd
|
Use full multiplier bitwidth for windowing + increased number of DFT bins
|
2020-11-08 14:38:31 +01:00 |
