257 lines
8.2 KiB
C++
257 lines
8.2 KiB
C++
#include "SpectrumAnalyzer.hpp"
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#include "Hardware.hpp"
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#include "HW_HAL.hpp"
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#include <complex.h>
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#include <limits>
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#include "Communication.h"
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#include "FreeRTOS.h"
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#include "task.h"
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#define LOG_LEVEL LOG_LEVEL_DEBUG
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#define LOG_MODULE "SA"
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#include "Log.h"
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static Protocol::SpectrumAnalyzerSettings s;
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static uint32_t pointCnt;
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static uint32_t points;
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static uint32_t binSize;
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static uint8_t signalIDstep;
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static uint32_t sampleNum;
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static Protocol::PacketInfo p;
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static bool active = false;
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static uint32_t lastLO2;
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static uint32_t actualRBW;
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static float port1Measurement, port2Measurement;
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using namespace HWHAL;
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static void StartNextSample() {
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uint64_t freq = s.f_start + (s.f_stop - s.f_start) * pointCnt / (points - 1);
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uint64_t LO1freq;
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uint32_t LO2freq;
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switch(signalIDstep) {
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case 0:
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default:
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// reset minimum amplitudes in first signal ID step
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port1Measurement = std::numeric_limits<float>::max();
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port2Measurement = std::numeric_limits<float>::max();
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// Use default LO frequencies
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LO1freq = freq + HW::IF1;
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LO2freq = HW::IF1 - HW::IF2;
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 112);
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, 1120);
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break;
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case 1:
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LO2freq = HW::IF1 - HW::IF2;
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// Shift first LO to other side
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// depending on the measurement frequency this is not possible or additive mixing has to be used
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if(freq >= HW::IF1 + HW::LO1_minFreq) {
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// frequency is high enough to shift 1.LO below measurement frequency
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LO1freq = freq - HW::IF1;
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break;
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} else if(freq <= HW::IF1 - HW::LO1_minFreq) {
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// frequency is low enough to add 1.LO to measurement frequency
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LO1freq = HW::IF1 - freq;
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break;
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}
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// unable to reach required frequency with 1.LO, skip this signal ID step
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signalIDstep++;
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/* no break */
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case 2:
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// Shift both LOs to other side
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LO1freq = freq + HW::IF1;
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LO2freq = HW::IF1 + HW::IF2;
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break;
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case 3:
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LO2freq = HW::IF1 + HW::IF2;
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// Shift second LO to other side
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// depending on the measurement frequency this is not possible or additive mixing has to be used
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if(freq >= HW::IF1 + HW::LO1_minFreq) {
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// frequency is high enough to shift 1.LO below measurement frequency
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LO1freq = freq - HW::IF1;
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break;
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} else if(freq <= HW::IF1 - HW::LO1_minFreq) {
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// frequency is low enough to add 1.LO to measurement frequency
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LO1freq = HW::IF1 - freq;
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break;
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}
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// unable to reach required frequency with 1.LO, skip this signal ID step
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signalIDstep++;
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/* no break */
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case 4:
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// Use default frequencies with different ADC samplerate to remove images in final IF
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LO1freq = freq + HW::IF1;
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LO2freq = HW::IF1 - HW::IF2;
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FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 120);
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, 1200);
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}
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LO1.SetFrequency(LO1freq);
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// LO1 is not able to reach all frequencies with the required precision, adjust LO2 to account for deviation
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int32_t LO1deviation = (int64_t) LO1.GetActualFrequency() - LO1freq;
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LO2freq += LO1deviation;
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// only adjust LO2 PLL if necessary (if the deviation is significantly less than the RBW it does not matter)
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if((uint32_t) abs(LO2freq - lastLO2) > actualRBW / 2) {
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Si5351.SetCLK(SiChannel::Port1LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::Port2LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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lastLO2 = LO2freq;
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}
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// Configure the sampling in the FPGA
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FPGA::WriteSweepConfig(0, 0, Source.GetRegisters(), LO1.GetRegisters(), 0,
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0, FPGA::SettlingTime::us20, FPGA::Samples::SPPRegister, 0,
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FPGA::LowpassFilter::M947);
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FPGA::StartSweep();
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}
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void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
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LOG_DEBUG("Setting up...");
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SA::Stop();
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vTaskDelay(5);
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s = settings;
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HW::SetMode(HW::Mode::SA);
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FPGA::SetMode(FPGA::Mode::FPGA);
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// in almost all cases a full sweep requires more points than the FPGA can handle at a time
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// individually start each point and do the sweep in the uC
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FPGA::SetNumberOfPoints(1);
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// calculate required samples per measurement for requested RBW
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// see https://www.tek.com/blog/window-functions-spectrum-analyzers for window factors
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constexpr float window_factors[4] = {0.89f, 2.23f, 1.44f, 3.77f};
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sampleNum = HW::ADCSamplerate * window_factors[s.WindowType] / s.RBW;
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// round up to next multiple of 16
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if(sampleNum%16) {
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sampleNum += 16 - sampleNum%16;
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}
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if(sampleNum >= HW::MaxSamples) {
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sampleNum = HW::MaxSamples;
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}
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actualRBW = HW::ADCSamplerate * window_factors[s.WindowType] / sampleNum;
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FPGA::SetSamplesPerPoint(sampleNum);
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// calculate amount of required points
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points = 2 * (s.f_stop - s.f_start) / actualRBW;
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// adjust to integer multiple of requested result points (in order to have the same amount of measurements in each bin)
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points += s.pointNum - points % s.pointNum;
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binSize = points / s.pointNum;
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LOG_DEBUG("%u displayed points, resulting in %lu points and bins of size %u", s.pointNum, points, binSize);
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// set initial state
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pointCnt = 0;
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// enable the required hardware resources
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Si5351.Enable(SiChannel::Port1LO2);
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Si5351.Enable(SiChannel::Port2LO2);
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FPGA::SetWindow((FPGA::Window) s.WindowType);
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FPGA::Enable(FPGA::Periphery::LO1Chip);
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FPGA::Enable(FPGA::Periphery::LO1RF);
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FPGA::Enable(FPGA::Periphery::ExcitePort1);
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FPGA::Enable(FPGA::Periphery::Port1Mixer);
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FPGA::Enable(FPGA::Periphery::Port2Mixer);
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lastLO2 = 0;
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active = true;
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StartNextSample();
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}
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bool SA::MeasurementDone(FPGA::SamplingResult result) {
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if(!active) {
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return false;
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}
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FPGA::AbortSweep();
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float port1 = abs(std::complex<float>(result.P1I, result.P1Q))/sampleNum;
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float port2 = abs(std::complex<float>(result.P2I, result.P2Q))/sampleNum;
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if(port1 < port1Measurement) {
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port1Measurement = port1;
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}
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if(port2 < port2Measurement) {
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port2Measurement = port2;
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}
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// trigger work function
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return true;
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}
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void SA::Work() {
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if(!active) {
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return;
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}
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if(!s.SignalID || signalIDstep >= 4) {
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// this measurement point is done, handle result according to detector
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uint16_t binIndex = pointCnt / binSize;
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uint32_t pointInBin = pointCnt % binSize;
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bool lastPointInBin = pointInBin >= binSize - 1;
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auto det = (Detector) s.Detector;
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if(det == Detector::Normal) {
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det = binIndex & 0x01 ? Detector::PosPeak : Detector::NegPeak;
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}
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switch(det) {
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case Detector::PosPeak:
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if(pointInBin == 0) {
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p.spectrumResult.port1 = std::numeric_limits<float>::min();
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p.spectrumResult.port2 = std::numeric_limits<float>::min();
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}
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if(port1Measurement > p.spectrumResult.port1) {
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p.spectrumResult.port1 = port1Measurement;
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}
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if(port2Measurement > p.spectrumResult.port2) {
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p.spectrumResult.port2 = port2Measurement;
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}
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break;
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case Detector::NegPeak:
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if(pointInBin == 0) {
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p.spectrumResult.port1 = std::numeric_limits<float>::max();
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p.spectrumResult.port2 = std::numeric_limits<float>::max();
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}
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if(port1Measurement < p.spectrumResult.port1) {
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p.spectrumResult.port1 = port1Measurement;
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}
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if(port2Measurement < p.spectrumResult.port2) {
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p.spectrumResult.port2 = port2Measurement;
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}
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break;
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case Detector::Sample:
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if(pointInBin <= binSize / 2) {
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// still in first half of bin, simply overwrite
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p.spectrumResult.port1 = port1Measurement;
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p.spectrumResult.port2 = port2Measurement;
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}
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break;
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case Detector::Average:
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if(pointInBin == 0) {
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p.spectrumResult.port1 = 0;
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p.spectrumResult.port2 = 0;
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}
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p.spectrumResult.port1 += port1Measurement;
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p.spectrumResult.port2 += port2Measurement;
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if(lastPointInBin) {
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// calculate average
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p.spectrumResult.port1 /= binSize;
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p.spectrumResult.port2 /= binSize;
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}
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break;
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case Detector::Normal:
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// nothing to do, normal detector handled by PosPeak or NegPeak in each sample
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break;
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}
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if(lastPointInBin) {
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// Send result to application
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p.type = Protocol::PacketType::SpectrumAnalyzerResult;
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// measurements are already up to date, fill remaining fields
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p.spectrumResult.pointNum = binIndex;
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p.spectrumResult.frequency = s.f_start + (s.f_stop - s.f_start) * binIndex / (s.pointNum - 1);
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Communication::Send(p);
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}
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// setup for next step
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signalIDstep = 0;
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if(pointCnt < points - 1) {
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pointCnt++;
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} else {
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pointCnt = 0;
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}
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} else {
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// more measurements required for signal ID
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signalIDstep++;
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}
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StartNextSample();
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}
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void SA::Stop() {
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active = false;
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FPGA::AbortSweep();
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}
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