378 lines
11 KiB
VHDL
378 lines
11 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:38:37 09/18/2020
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-- Design Name:
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-- Module Name: DFT - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DFT is
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Generic (BINS : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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PORT1 : in STD_LOGIC_VECTOR (15 downto 0);
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PORT2 : in STD_LOGIC_VECTOR (15 downto 0);
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NEW_SAMPLE : in STD_LOGIC;
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NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
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BIN1_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
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DIFFBIN_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
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RESULT_READY : out STD_LOGIC;
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OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
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NEXT_OUTPUT : in STD_LOGIC);
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end DFT;
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architecture Behavioral of DFT is
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COMPONENT dft_result
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GENERIC(depth : integer);
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PORT(
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CLK : IN std_logic;
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READ_ADDRESS : in integer range 0 to depth-1;
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WRITE_ADDRESS : in integer range 0 to depth-1;
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DATA_IN : IN std_logic_vector(191 downto 0);
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WE : IN std_logic;
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DATA_OUT : OUT std_logic_vector(191 downto 0)
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);
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END COMPONENT;
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COMPONENT result_bram
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PORT (
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clka : IN STD_LOGIC;
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wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
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clkb : IN STD_LOGIC;
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addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT SinCos
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PORT (
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clk : IN STD_LOGIC;
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phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT SinCosMult
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PORT (
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clk : IN STD_LOGIC;
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a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT DSP_SLICE
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT window
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PORT(
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CLK : IN std_logic;
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INDEX : IN std_logic_vector(6 downto 0);
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WINDOW_TYPE : IN std_logic_vector(1 downto 0);
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VALUE : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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--type result is array(BINS-1 downto 0) of std_logic_vector(47 downto 0);
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--signal port1_real : result;
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--signal port1_imag : result;
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--signal port2_real : result;
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--signal port2_imag : result;
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--signal port1_real_read : std_logic_vector(47 downto 0);
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--signal port1_imag_read : std_logic_vector(47 downto 0);
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--signal port2_real_read : std_logic_vector(47 downto 0);
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--signal port2_imag_read : std_logic_vector(47 downto 0);
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signal sample_cnt : integer range 0 to 131072;
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signal samples_to_take : integer range 0 to 131072;
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signal bin_cnt : integer range 0 to BINS+2;
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signal read_address : integer range 0 to BINS-1;
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signal write_address : integer range 0 to BINS-1;
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signal read_address_vector : std_logic_vector(5 downto 0);
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signal write_address_vector : std_logic_vector(5 downto 0);
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signal we : std_logic_vector(0 downto 0);
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signal ram_in : std_logic_vector(191 downto 0);
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signal ram_out : std_logic_vector(191 downto 0);
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type States is (WaitingForSample, WaitMult, WaitSinCos, Busy, Ready);
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signal state : States;
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signal port1_latch : std_logic_vector(15 downto 0);
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signal port2_latch : std_logic_vector(15 downto 0);
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signal phase : std_logic_vector(31 downto 0);
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signal phase_inc : std_logic_vector(31 downto 0);
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signal sine : std_logic_vector(15 downto 0);
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signal cosine : std_logic_vector(15 downto 0);
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signal mult1_a : std_logic_vector(17 downto 0);
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signal mult1_b : std_logic_vector(17 downto 0);
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signal mult1_c : std_logic_vector(47 downto 0);
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signal mult1_p : std_logic_vector(47 downto 0);
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signal mult2_a : std_logic_vector(17 downto 0);
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signal mult2_b : std_logic_vector(17 downto 0);
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signal mult2_c : std_logic_vector(47 downto 0);
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signal mult2_p : std_logic_vector(47 downto 0);
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signal mult3_a : std_logic_vector(17 downto 0);
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signal mult3_b : std_logic_vector(17 downto 0);
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signal mult3_c : std_logic_vector(47 downto 0);
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signal mult3_p : std_logic_vector(47 downto 0);
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signal mult4_a : std_logic_vector(17 downto 0);
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signal mult4_b : std_logic_vector(17 downto 0);
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signal mult4_c : std_logic_vector(47 downto 0);
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signal mult4_p : std_logic_vector(47 downto 0);
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signal mult_enable : std_logic;
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signal mult_accumulate : std_logic_vector(0 downto 0);
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begin
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LookupTable : SinCos
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PORT MAP (
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clk => CLK,
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phase_in => phase(31 downto 20),
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cosine => cosine,
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sine => sine
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);
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Mult1 : DSP_SLICE
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PORT MAP (
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clk => CLK,
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ce => mult_enable,
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sel => mult_accumulate,
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a => mult1_a,
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b => mult1_b,
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c => mult1_c,
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p => mult1_p
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);
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Mult2 : DSP_SLICE
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PORT MAP (
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clk => CLK,
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ce => mult_enable,
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sel => mult_accumulate,
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a => mult2_a,
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b => mult2_b,
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c => mult2_c,
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p => mult2_p
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);
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Mult3 : DSP_SLICE
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PORT MAP (
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clk => CLK,
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ce => mult_enable,
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sel => mult_accumulate,
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a => mult3_a,
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b => mult3_b,
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c => mult3_c,
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p => mult3_p
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);
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Mult4 : DSP_SLICE
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PORT MAP (
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clk => CLK,
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ce => mult_enable,
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sel => mult_accumulate,
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a => mult4_a,
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b => mult4_b,
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c => mult4_c,
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p => mult4_p
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);
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result_ram: result_bram
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PORT MAP (
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clka => CLK,
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wea => we,
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addra => write_address_vector,
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dina => ram_in,
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clkb => CLK,
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addrb => read_address_vector,
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doutb => ram_out
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);
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read_address_vector <= std_logic_vector(to_unsigned(read_address, 6));
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write_address_vector <= std_logic_vector(to_unsigned(write_address, 6));
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OUTPUT <= ram_out;
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mult1_c <= ram_out(191 downto 144);
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mult2_c <= ram_out(143 downto 96);
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mult3_c <= ram_out(95 downto 48);
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mult4_c <= ram_out(47 downto 0);
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ram_in <= mult1_p & mult2_p & mult3_p & mult4_p;
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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mult_enable <= '0';
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mult_accumulate <= "0";
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sample_cnt <= 0;
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RESULT_READY <= '0';
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read_address <= 0;
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write_address <= 0;
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we <= "0";
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state <= WaitingForSample;
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else
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samples_to_take <= to_integer(unsigned(NSAMPLES & "0000")) - 1;
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case state is
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when WaitingForSample =>
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we <= "0";
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mult_enable <= '0';
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mult_accumulate <= "0";
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read_address <= 0;
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write_address <= 0;
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if NEW_SAMPLE = '1' then
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-- calculate phase for initial bin
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mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
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mult1_b <= "00" & BIN1_PHASEINC;
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mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
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mult2_b <= "00" & DIFFBIN_PHASEINC;
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state <= WaitMult;
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bin_cnt <= 0;
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mult_enable <= '1';
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end if;
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when WaitMult =>
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RESULT_READY <= '0';
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we <= "0";
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mult_enable <= '1';
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mult_accumulate <= "0";
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read_address <= 0;
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write_address <= 0;
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if bin_cnt < 4 then
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bin_cnt <= bin_cnt + 1;
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else
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bin_cnt <= 0;
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mult_enable <= '0';
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state <= WaitSinCos;
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phase <= mult1_p(15 downto 0) & "0000000000000000";
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phase_inc <= mult2_p(23 downto 0) & "00000000";
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port1_latch <= PORT1;
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port2_latch <= PORT2;
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end if;
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when WaitSinCos =>
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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RESULT_READY <= '0';
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we <= "0";
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mult_enable <= '0';
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mult_accumulate <= "0";
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read_address <= 0;
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write_address <= 0;
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if bin_cnt < 6 then
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bin_cnt <= bin_cnt + 1;
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else
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bin_cnt <= 0;
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mult_enable <= '1';
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read_address <= 1;
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-- sign extended multiplication
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mult1_a <= port1_latch(15) & port1_latch(15) & port1_latch;
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mult1_b <= sine(15) & sine(15) & sine;
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mult2_a <= port1_latch(15) & port1_latch(15) & port1_latch;
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mult2_b <= cosine(15) & cosine(15) & cosine;
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mult3_a <= port2_latch(15) & port2_latch(15) & port2_latch;
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mult3_b <= sine(15) & sine(15) & sine;
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mult4_a <= port2_latch(15) & port2_latch(15) & port2_latch;
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mult4_b <= cosine(15) & cosine(15) & cosine;
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state <= BUSY;
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if sample_cnt = 0 then
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mult_accumulate <= "0";
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else
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mult_accumulate <= "1";
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end if;
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end if;
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when BUSY =>
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mult_enable <= '1';
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if sample_cnt = 0 then
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mult_accumulate <= "0";
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else
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mult_accumulate <= "1";
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end if;
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RESULT_READY <= '0';
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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-- sign extended multiplication
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mult1_a <= port1_latch(15) & port1_latch(15) & port1_latch;
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mult1_b <= sine(15) & sine(15) & sine;
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mult2_a <= port1_latch(15) & port1_latch(15) & port1_latch;
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mult2_b <= cosine(15) & cosine(15) & cosine;
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mult3_a <= port2_latch(15) & port2_latch(15) & port2_latch;
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mult3_b <= sine(15) & sine(15) & sine;
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mult4_a <= port2_latch(15) & port2_latch(15) & port2_latch;
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mult4_b <= cosine(15) & cosine(15) & cosine;
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if bin_cnt >= 3 then
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-- multiplier result is available, advance write address
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we <= "1";
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write_address <= bin_cnt - 3;
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else
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we <= "0";
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write_address <= 0;
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end if;
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if bin_cnt >= BINS+2 then
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read_address <= 0;
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if sample_cnt < samples_to_take then
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sample_cnt <= sample_cnt + 1;
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state <= WaitingForSample;
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else
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state <= Ready;
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end if;
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else
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bin_cnt <= bin_cnt + 1;
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if bin_cnt < BINS - 2 then
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read_address <= bin_cnt + 2;
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end if;
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end if;
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when Ready =>
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we <= "0";
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RESULT_READY <= '1';
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write_address <= 0;
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if NEXT_OUTPUT = '1' then
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-- fetch next entry from RAM
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if read_address < BINS - 1 then
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read_address <= read_address + 1;
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else
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RESULT_READY <= '0';
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sample_cnt <= 0;
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mult_enable <= '0';
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state <= WaitingForSample;
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read_address <= 0;
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end if;
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end if;
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when others =>
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state <= WaitingForSample;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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