137 lines
3.1 KiB
Plaintext
137 lines
3.1 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.6
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# Date: Fri Nov 6 13:56:17 2020
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = tqg144
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
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# END Select
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# BEGIN Parameters
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CSET a_binarywidth=0
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CSET a_width=18
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CSET areg_1=false
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CSET areg_2=false
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CSET areg_3=true
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CSET areg_4=true
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CSET b_binarywidth=0
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CSET b_width=18
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CSET breg_1=false
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CSET breg_2=false
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CSET breg_3=true
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CSET breg_4=true
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CSET c_binarywidth=0
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CSET c_width=48
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CSET cinreg_1=false
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CSET cinreg_2=false
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CSET cinreg_3=false
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CSET cinreg_4=false
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CSET cinreg_5=false
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CSET component_name=DSP48
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CSET concat_binarywidth=0
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CSET concat_width=48
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CSET concatreg_3=false
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CSET concatreg_4=false
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CSET concatreg_5=false
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CSET creg_1=false
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CSET creg_2=false
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CSET creg_3=true
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CSET creg_4=true
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CSET creg_5=true
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CSET d_binarywidth=0
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CSET d_width=18
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CSET dreg_1=false
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CSET dreg_2=false
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CSET dreg_3=false
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CSET gui_behaviour=Coregen
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CSET has_a_ce=false
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CSET has_a_sclr=false
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CSET has_acout=false
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CSET has_b_ce=false
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CSET has_b_sclr=false
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CSET has_bcout=false
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CSET has_c_ce=false
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CSET has_c_sclr=false
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CSET has_carrycascout=false
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CSET has_carryout=false
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CSET has_ce=true
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CSET has_concat_ce=false
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CSET has_concat_sclr=false
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CSET has_d_ce=false
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CSET has_d_sclr=false
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CSET has_m_ce=false
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CSET has_m_sclr=false
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CSET has_p_ce=false
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CSET has_p_sclr=false
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CSET has_pcout=false
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CSET has_sclr=false
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CSET has_sel_ce=false
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CSET has_sel_sclr=false
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CSET instruction1=A*B
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CSET instruction2=A*B+C
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CSET instruction3=#
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CSET instruction4=#
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CSET instruction5=#
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CSET instruction6=#
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CSET instruction7=#
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CSET instruction8=#
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CSET instruction_list=#
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CSET mreg_5=true
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CSET opreg_1=false
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CSET opreg_2=false
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CSET opreg_3=true
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CSET opreg_4=true
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CSET opreg_5=true
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CSET output_properties=Full_Precision
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CSET p_binarywidth=0
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CSET p_full_width=48
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CSET p_width=48
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CSET pcin_binarywidth=0
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CSET pipeline_options=Automatic
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CSET preg_6=true
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CSET show_filtered=false
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CSET tier_1=false
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CSET tier_2=false
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CSET tier_3=false
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CSET tier_4=false
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CSET tier_5=false
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CSET tier_6=false
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CSET use_dsp48=true
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-11-05T14:23:53Z
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# END Extra information
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GENERATE
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# CRC: 2ca4f824
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