Jan Käberich c1f131b6d7 Rename combined file		2020-09-20 12:00:58 +02:00
Documentation	Create BuildAndFlash.md	2020-09-20 11:14:48 +02:00
FPGA	mitigation for peaks caused by limited fractional divider in PLLs	2020-09-20 10:13:06 +02:00
Hardware	Trace for port switch moved to fix short with aluminium shield	2020-09-06 15:54:51 +02:00
Software	mitigation for peaks caused by limited fractional divider in PLLs	2020-09-20 10:13:06 +02:00
.gitignore	Schematic + some placement	2020-07-25 17:34:56 +02:00
AssembleFirmware.py	Rename combined file	2020-09-20 12:00:58 +02:00