caiyu/LibreVNA
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C++ 50.3%
C 47%
VHDL 2.2%
QMake 0.2%
Python 0.2%
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Jan Käberich ca3bc9c794 DC jack with power priority over USB
2020-09-21 12:23:30 +02:00
Documentation Create BuildAndFlash.md 2020-09-20 11:14:48 +02:00
FPGA mitigation for peaks caused by limited fractional divider in PLLs 2020-09-20 10:13:06 +02:00
Hardware DC jack with power priority over USB 2020-09-21 12:23:30 +02:00
Software Bugfix: only enable highband source once per sweep 2020-09-20 22:51:51 +02:00
.gitignore Schematic + some placement 2020-07-25 17:34:56 +02:00
AssembleFirmware.py Rename combined file 2020-09-20 12:00:58 +02:00