134 lines
3.6 KiB
VHDL
134 lines
3.6 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:25:23 09/18/2020
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-- Design Name:
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-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_DFT.vhd
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-- Project Name: VNA
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: DFT
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Test_DFT IS
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END Test_DFT;
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ARCHITECTURE behavior OF Test_DFT IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT DFT
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GENERIC(BINS : integer);
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PORT(
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CLK : IN std_logic;
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RESET : IN std_logic;
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PORT1 : IN std_logic_vector(15 downto 0);
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PORT2 : IN std_logic_vector(15 downto 0);
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NEW_SAMPLE : IN std_logic;
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NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
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BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
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DIFFBIN_PHASEINC : IN std_logic_vector(15 downto 0);
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RESULT_READY : OUT std_logic;
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OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
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NEXT_OUTPUT : IN std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '0';
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signal PORT1 : std_logic_vector(15 downto 0) := (others => '0');
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signal PORT2 : std_logic_vector(15 downto 0) := (others => '0');
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signal NEW_SAMPLE : std_logic := '0';
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signal BIN1_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
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signal DIFFBIN_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
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signal NEXT_OUTPUT : std_logic := '0';
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signal NSAMPLES : STD_LOGIC_VECTOR (12 downto 0);
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--Outputs
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signal RESULT_READY : std_logic;
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signal OUTPUT : STD_LOGIC_VECTOR (191 downto 0);
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: DFT
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GENERIC MAP(BINS => 64)
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PORT MAP (
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CLK => CLK,
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RESET => RESET,
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PORT1 => PORT1,
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PORT2 => PORT2,
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NEW_SAMPLE => NEW_SAMPLE,
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NSAMPLES => NSAMPLES,
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BIN1_PHASEINC => BIN1_PHASEINC,
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DIFFBIN_PHASEINC => DIFFBIN_PHASEINC,
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RESULT_READY => RESULT_READY,
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OUTPUT => OUTPUT,
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NEXT_OUTPUT => NEXT_OUTPUT
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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RESET <= '1';
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PORT1 <= "1000000000000000";
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PORT2 <= "0100000000000000";
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BIN1_PHASEINC <= "0100000000000000";
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DIFFBIN_PHASEINC <= "0010000000000000";
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NSAMPLES <= "0000000000000011";
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wait for 100 ns;
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RESET <= '0';
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wait for CLK_period*10;
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NEW_SAMPLE <= '1';
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wait for CLK_period;
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NEW_SAMPLE <= '0';
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while True loop
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wait for CLK_period * 79;
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NEW_SAMPLE <= '1';
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wait for CLK_period;
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NEW_SAMPLE <= '0';
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end loop;
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wait;
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end process;
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END;
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