caiyu/LibreVNA
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Jan Käberich de8761545d Experimental feature: only excite one port when other traces are paused
2020-09-15 23:22:08 +02:00
FPGA Experimental feature: only excite one port when other traces are paused 2020-09-15 23:22:08 +02:00
Hardware Trace for port switch moved to fix short with aluminium shield 2020-09-06 15:54:51 +02:00
Software Experimental feature: only excite one port when other traces are paused 2020-09-15 23:22:08 +02:00
.gitignore Schematic + some placement 2020-07-25 17:34:56 +02:00
AssembleFirmware.py PC Application: partial firmware update dialog 2020-08-30 22:03:41 +02:00