262 lines
7.5 KiB
VHDL
262 lines
7.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:38:37 09/18/2020
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-- Design Name:
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-- Module Name: DFT - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DFT is
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Generic (BINS : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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PORT1 : in STD_LOGIC_VECTOR (15 downto 0);
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PORT2 : in STD_LOGIC_VECTOR (15 downto 0);
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NEW_SAMPLE : in STD_LOGIC;
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NSAMPLES : in STD_LOGIC_VECTOR (15 downto 0);
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BIN1_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
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DIFFBIN_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
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WINDOW_INC : in STD_LOGIC_VECTOR (15 downto 0);
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WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
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RESULT_READY : out STD_LOGIC;
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OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
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NEXT_OUTPUT : in STD_LOGIC);
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end DFT;
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architecture Behavioral of DFT is
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COMPONENT SinCos
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PORT (
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clk : IN STD_LOGIC;
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phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT SinCosMult
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PORT (
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clk : IN STD_LOGIC;
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a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT window
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PORT(
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CLK : IN std_logic;
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INDEX : IN std_logic_vector(6 downto 0);
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WINDOW_TYPE : IN std_logic_vector(1 downto 0);
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VALUE : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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type result is array(BINS-1 downto 0) of std_logic_vector(47 downto 0);
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signal port1_real : result;
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signal port1_imag : result;
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signal port2_real : result;
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signal port2_imag : result;
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signal sample_cnt : integer range 0 to 65535;
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signal bin_cnt : integer range 0 to BINS+2;
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signal output_cnt : integer range 0 to BINS-1;
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type States is (WaitingForSample, WindowingStart, WaitMult, WaitMult2, PhaseReady, WindowingReady, WaitSinCos, Busy, Ready);
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signal state : States;
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signal port1_latch : std_logic_vector(15 downto 0);
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signal port2_latch : std_logic_vector(15 downto 0);
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signal window_index : std_logic_vector(6 downto 0);
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signal window_cnt : unsigned(
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signal window_value : std_logic_vector(15 downto 0);
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signal phase : std_logic_vector(31 downto 0);
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signal phase_inc : std_logic_vector(31 downto 0);
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signal sine : std_logic_vector(15 downto 0);
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signal cosine : std_logic_vector(15 downto 0);
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signal mult1_a : std_logic_vector(15 downto 0);
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signal mult1_b : std_logic_vector(15 downto 0);
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signal mult1_p : std_logic_vector(31 downto 0);
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signal mult2_a : std_logic_vector(15 downto 0);
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signal mult2_b : std_logic_vector(15 downto 0);
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signal mult2_p : std_logic_vector(31 downto 0);
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signal mult3_a : std_logic_vector(15 downto 0);
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signal mult3_b : std_logic_vector(15 downto 0);
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signal mult3_p : std_logic_vector(31 downto 0);
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signal mult4_a : std_logic_vector(15 downto 0);
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signal mult4_b : std_logic_vector(15 downto 0);
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signal mult4_p : std_logic_vector(31 downto 0);
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begin
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LookupTable : SinCos
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PORT MAP (
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clk => CLK,
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phase_in => phase(31 downto 20),
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cosine => cosine,
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sine => sine
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);
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Mult1 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult1_a,
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b => mult1_b,
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p => mult1_p
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);
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Mult2 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult2_a,
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b => mult2_b,
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p => mult2_p
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);
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Mult3 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult3_a,
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b => mult3_b,
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p => mult3_p
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);
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Mult4 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult4_a,
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b => mult4_b,
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p => mult4_p
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);
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WindowROM: window PORT MAP(
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CLK => CLK,
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INDEX => window_index(15 downto 9),
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WINDOW_TYPE => WINDOW_TYPE,
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VALUE => window_value
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);
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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window_index <= (others => '0');
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sample_cnt <= 0;
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RESULT_READY <= '1';
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state <= WaitingForSample;
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else
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case state is
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when WaitingForSample =>
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RESULT_READY <= '1';
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OUTPUT <= port1_real(output_cnt) & port1_imag(output_cnt) & port2_real(output_cnt) & port2_imag(output_cnt);
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if NEXT_OUTPUT = '1' then
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if output_cnt < BINS - 1 then
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output_cnt <= output_cnt + 1;
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else
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output_cnt <= 0;
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end if;
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end if;
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if NEW_SAMPLE = '1' then
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-- calculate phase for initial bin
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mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
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mult1_b <= BIN1_PHASEINC;
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mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
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mult2_b <= DIFFBIN_PHASEINC;
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-- window ADC data
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mult3_a <= PORT1;
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mult3_b <= window_value;
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mult4_a <= PORT2;
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mult4_b <= window_value;
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state <= WaitMult;
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end if;
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when WaitMult =>
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RESULT_READY <= '0';
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state <= WaitMult2;
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when WaitMult2 =>
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RESULT_READY <= '0';
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state <= PhaseReady;
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when PhaseReady =>
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RESULT_READY <= '0';
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-- initial phase is ready
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phase <= mult1_p;
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phase_inc <= mult2_p;
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state <= WindowingReady;
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when WindowingReady =>
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RESULT_READY <= '0';
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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port1_latch <= mult3_p(31 downto 16);
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port2_latch <= mult4_p(31 downto 16);
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bin_cnt <= 0;
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state <= WaitSinCos;
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when WaitSinCos =>
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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RESULT_READY <= '0';
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if bin_cnt < 4 then
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bin_cnt <= bin_cnt + 1;
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else
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bin_cnt <= 0;
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state <= BUSY;
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end if;
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when BUSY =>
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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mult1_a <= port1_latch;
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mult1_b <= sine;
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mult2_a <= port1_latch;
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mult2_b <= cosine;
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mult3_a <= port2_latch;
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mult3_b <= sine;
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mult4_a <= port2_latch;
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mult4_b <= cosine;
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if bin_cnt >= 3 then
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-- multiplier result is available, accumulate
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if sample_cnt = 0 then
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port1_real(bin_cnt-3) <= mult1_p;
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port1_imag(bin_cnt-3) <= mult2_p;
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port2_real(bin_cnt-3) <= mult3_p;
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port2_imag(bin_cnt-3) <= mult4_p;
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else
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port1_real(bin_cnt-3) <= std_logic_vector(unsigned(port1_real(bin_cnt-3))+unsigned(mult1_p));
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port1_imag(bin_cnt-3) <= std_logic_vector(unsigned(port1_imag(bin_cnt-3))+unsigned(mult2_p));
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port2_real(bin_cnt-3) <= std_logic_vector(unsigned(port2_real(bin_cnt-3))+unsigned(mult3_p));
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--port2_imag(bin_cnt-3) <= std_logic_vector(unsigned(port2_imag(bin_cnt-3))+unsigned(mult4_p));
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end if;
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end if;
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if bin_cnt >= BINS+2 then
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state <= WaitingForSample;
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RESULT_READY <= '1';
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sample_cnt <= sample_cnt + 1;
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window_index <= std_logic_vector(unsigned(window_index)+unsigned(WINDOW_INC));
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output_cnt <= 0;
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else
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RESULT_READY <= '0';
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bin_cnt <= bin_cnt + 1;
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end if;
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when others =>
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RESULT_READY <= '0';
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state <= WaitingForSample;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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