caiyu/LibreVNA
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48 Commits 1 Branch 0 Tags 266 MiB
C++ 50.3%
C 47%
VHDL 2.2%
QMake 0.2%
Python 0.2%
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Jan Käberich efcd5e8347 Blockdiagrams
2020-09-21 18:49:17 +02:00
Documentation Blockdiagrams 2020-09-21 18:49:17 +02:00
FPGA mitigation for peaks caused by limited fractional divider in PLLs 2020-09-20 10:13:06 +02:00
Hardware DC jack with power priority over USB 2020-09-21 12:23:30 +02:00
Software CPU temperature readout 2020-09-21 14:29:31 +02:00
.gitignore Schematic + some placement 2020-07-25 17:34:56 +02:00
AssembleFirmware.py Rename combined file 2020-09-20 12:00:58 +02:00