146 lines
4.5 KiB
C++
146 lines
4.5 KiB
C++
#include "Manual.hpp"
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#include "HW_HAL.hpp"
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#include "Hardware.hpp"
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#include "Communication.h"
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#include <cstring>
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static bool active = false;
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static uint32_t samples;
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static Protocol::ManualStatusV1 status;
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using namespace HWHAL;
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void Manual::Setup(Protocol::ManualControlV1 m) {
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HW::SetMode(HW::Mode::Manual);
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samples = m.Samples;
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FPGA::AbortSweep();
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// Configure lowband source
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if (m.SourceLowEN) {
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Si5351.SetCLK(SiChannel::LowbandSource, m.SourceLowFrequency, Si5351C::PLL::B,
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(Si5351C::DriveStrength) m.SourceLowPower);
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Si5351.Enable(SiChannel::LowbandSource);
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} else {
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Si5351.Disable(SiChannel::LowbandSource);
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}
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// Configure highband source
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Source.SetFrequency(m.SourceHighFrequency);
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Source.SetPowerOutA((MAX2871::Power) m.SourceHighPower);
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// Configure LO1
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LO1.SetFrequency(m.LO1Frequency);
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// Configure LO2
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if(m.LO2EN) {
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// Generate second LO with Si5351
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Si5351.SetCLK(SiChannel::Port1LO2, m.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port1LO2);
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Si5351.SetCLK(SiChannel::Port2LO2, m.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port2LO2);
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Si5351.SetCLK(SiChannel::RefLO2, m.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::RefLO2);
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// PLL reset appears to realign phases of clock signals
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Si5351.ResetPLL(Si5351C::PLL::B);
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} else {
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Si5351.Disable(SiChannel::Port1LO2);
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Si5351.Disable(SiChannel::Port2LO2);
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Si5351.Disable(SiChannel::RefLO2);
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}
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FPGA::WriteMAX2871Default(Source.GetRegisters());
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FPGA::SetNumberOfPoints(1);
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FPGA::SetSamplesPerPoint(m.Samples);
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// Configure single sweep point
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FPGA::WriteSweepConfig(0, !m.SourceHighband, Source.GetRegisters(),
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LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us20,
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FPGA::Samples::SPPRegister, 0,
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(FPGA::LowpassFilter) m.SourceHighLowpass);
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FPGA::SetWindow((FPGA::Window) m.WindowType);
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// Enable/Disable periphery
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FPGA::Enable(FPGA::Periphery::SourceChip, m.SourceHighCE);
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FPGA::Enable(FPGA::Periphery::SourceRF, m.SourceHighRFEN);
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FPGA::Enable(FPGA::Periphery::LO1Chip, m.LO1CE);
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FPGA::Enable(FPGA::Periphery::LO1RF, m.LO1RFEN);
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FPGA::Enable(FPGA::Periphery::Amplifier, m.AmplifierEN);
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FPGA::Enable(FPGA::Periphery::Port1Mixer, m.Port1EN);
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FPGA::Enable(FPGA::Periphery::Port2Mixer, m.Port2EN);
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FPGA::Enable(FPGA::Periphery::RefMixer, m.RefEN);
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FPGA::SetupSweep(0, m.PortSwitch == 1, m.PortSwitch == 0);
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FPGA::Enable(FPGA::Periphery::PortSwitch);
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// Enable new data and sweep halt interrupt
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FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
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active = true;
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FPGA::StartSweep();
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}
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bool Manual::MeasurementDone(const FPGA::SamplingResult &result) {
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if(!active) {
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return false;
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}
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// save measurement
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status.port1real = (float) result.P1I / samples;
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status.port1imag = (float) result.P1Q / samples;
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status.port2real = (float) result.P2I / samples;
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status.port2imag = (float) result.P2Q / samples;
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status.refreal = (float) result.RefI / samples;
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status.refimag = (float) result.RefQ / samples;
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return true;
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}
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void Manual::Work() {
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if(!active) {
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return;
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}
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Protocol::PacketInfo p;
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p.type = Protocol::PacketType::ManualStatusV1;
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p.manualStatusV1 = status;
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uint16_t isr_flags = FPGA::GetStatus();
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if (!(isr_flags & 0x0002)) {
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p.manualStatusV1.source_locked = 1;
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} else {
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p.manualStatusV1.source_locked = 0;
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}
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if (!(isr_flags & 0x0001)) {
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p.manualStatusV1.LO_locked = 1;
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} else {
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p.manualStatusV1.LO_locked = 0;
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}
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auto limits = FPGA::GetADCLimits();
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FPGA::ResetADCLimits();
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p.manualStatusV1.port1min = limits.P1min;
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p.manualStatusV1.port1max = limits.P1max;
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p.manualStatusV1.port2min = limits.P2min;
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p.manualStatusV1.port2max = limits.P2max;
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p.manualStatusV1.refmin = limits.Rmin;
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p.manualStatusV1.refmax = limits.Rmax;
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HW::GetTemps(&p.manualStatusV1.temp_source, &p.manualStatusV1.temp_LO);
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Communication::Send(p);
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HW::Ref::update();
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Protocol::PacketInfo packet;
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packet.type = Protocol::PacketType::DeviceStatusV1;
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// Enable PLL chips for temperature reading
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bool srcEn = FPGA::IsEnabled(FPGA::Periphery::SourceChip);
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bool LOEn = FPGA::IsEnabled(FPGA::Periphery::LO1Chip);
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FPGA::Enable(FPGA::Periphery::SourceChip);
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FPGA::Enable(FPGA::Periphery::LO1Chip);
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HW::getDeviceStatus(&packet.statusV1, true);
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// restore PLL state
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FPGA::Enable(FPGA::Periphery::SourceChip, srcEn);
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FPGA::Enable(FPGA::Periphery::LO1Chip, LOEn);
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Communication::Send(packet);
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// Trigger next status update
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FPGA::StartSweep();
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}
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void Manual::Stop() {
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active = false;
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}
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