57 lines
1.5 KiB
VHDL
57 lines
1.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:01:17 11/03/2020
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-- Design Name:
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-- Module Name: dft_result - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity dft_result is
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Generic (depth : integer);
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Port ( CLK : in STD_LOGIC;
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READ_ADDRESS : in integer range 0 to depth-1;
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WRITE_ADDRESS : in integer range 0 to depth-1;
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DATA_IN : in STD_LOGIC_VECTOR (191 downto 0);
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DATA_OUT : out STD_LOGIC_VECTOR (191 downto 0);
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WE : in STD_LOGIC);
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end dft_result;
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architecture rtl of dft_result is
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type memory is array(depth-1 downto 0) of std_logic_vector(191 downto 0);
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signal ram : memory;
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begin
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process(CLK)
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begin
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if rising_edge(CLK) then
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DATA_OUT <= ram(READ_ADDRESS);
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if(WE = '1') then
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ram(WRITE_ADDRESS) <= DATA_IN;
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end if;
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end if;
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end process;
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end rtl;
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