48 lines
1.0 KiB
VHDL
48 lines
1.0 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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--Simple Generic Galois LFSR
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--Copyright (C) 2017 David Shah
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--Licensed under the MIT License
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entity galois_lfsr is
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generic(
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size : natural := 32;
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polynomial : std_logic_vector := x"80000057";
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init : std_logic_vector := x"2b8e9b90"
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);
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port(
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clock : in std_logic;
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enable : in std_logic;
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reset : in std_logic; --active high sync reset
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data : out std_logic_vector(size-1 downto 0)
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);
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end galois_lfsr;
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architecture Behavioral of galois_lfsr is
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signal reg_d : std_logic_vector(size-1 downto 0);
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signal reg_q : std_logic_vector(size-1 downto 0) := init;
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begin
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reg_d <= (("0" & reg_q(size-1 downto 1)) xor polynomial) when reg_q(0) = '1' else
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("0" & reg_q(size-1 downto 1));
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process(clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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reg_q <= init;
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else
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if enable = '1' then
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reg_q <= reg_d;
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end if;
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end if;
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end if;
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end process;
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data <= reg_q;
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end Behavioral;
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