74 lines
2.0 KiB
VHDL
74 lines
2.0 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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--Parameterisable Gaussian White Noise Generator
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--Copyright (C) 2017 David Shah
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--Licensed under the MIT License
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--This uses a number of LFSR pseudorandom number generators in combination with
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--central limit theorem to generate gaussian noise for test purposes
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entity whitenoise_gen is
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generic(
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int_width : natural := 32; --width of LFSRs and interal calcs
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ext_width : natural := 12; --width of external value output
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num_lfsrs : natural := 20; --number of parallel LFSRs
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lfsr_poly : std_logic_vector := x"80000057" --LFSR polynomial
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);
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port(
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clock : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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data : out std_logic_vector(ext_width - 1 downto 0)
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);
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end whitenoise_gen;
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architecture Behavioral of whitenoise_gen is
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type lfsr_value_t is array(0 to num_lfsrs - 1) of std_logic_vector(int_width - 1 downto 0);
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signal lfsr_q : lfsr_value_t;
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signal sum_d : std_logic_vector(int_width - 1 downto 0) := (others => '0');
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signal sum_q : std_logic_vector(int_width - 1 downto 0);
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begin
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lfsr_gen: for i in 0 to num_lfsrs - 1 generate
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lfsr_i : entity work.galois_lfsr
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generic map(
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size => int_width,
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polynomial => lfsr_poly,
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init => std_logic_vector(to_unsigned( i + 1, int_width)))
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port map(
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clock => clock,
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enable => enable,
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reset => reset,
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data => lfsr_q(i));
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end generate;
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process(lfsr_q)
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variable sum : signed(int_width - 1 downto 0);
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begin
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sum := (others => '0');
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for i in 0 to num_lfsrs - 1 loop
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sum := sum + signed(lfsr_q(i));
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end loop;
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sum_d <= std_logic_vector(sum);
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end process;
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process(clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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sum_q <= (others => '0');
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elsif enable = '1' then
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sum_q <= sum_d;
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end if;
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end if;
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end process;
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data <= sum_q(int_width - 1 downto (int_width - ext_width));
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end Behavioral;
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