diff --git a/fpga/.gitignore b/fpga/.gitignore old mode 100644 new mode 100755 diff --git a/fpga/dds/.gitignore b/fpga/dds/.gitignore new file mode 100644 index 0000000..a3af5ba --- /dev/null +++ b/fpga/dds/.gitignore @@ -0,0 +1,4 @@ +*.pyc +*.gen.vhd +bin/ +*.csv diff --git a/fpga/dds/dds-core.vhd b/fpga/dds/dds-core.vhd new file mode 100644 index 0000000..24b7c8d --- /dev/null +++ b/fpga/dds/dds-core.vhd @@ -0,0 +1,50 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +--Direct Digital Synthesis Core +--Copyright (C) 2017 David Shah +--Licensed under the MIT License + +entity dds_core is + generic ( + N : natural := 24; --frequency word size + M : natural := 12 --phase out size (M <= N) + ); + port ( + clock : in std_logic; --control and synthesis clock + reset : in std_logic; --sync reset + enable : in std_logic; + freq_val : in std_logic_vector(N-1 downto 0); --frequency setting word + phase_val : in std_logic_vector(N-1 downto 0); --phase setting word + phase_load : in std_logic; --update phase + phase_out : out std_logic_vector(M-1 downto 0) --phase output + ); +end dds_core; + +architecture Behavioral of dds_core is + + signal freq_reg : unsigned(N-1 downto 0) := (others => '0'); + signal phase_acc : unsigned(N-1 downto 0) := (others => '0'); + signal phase_out_reg : std_logic_vector(M-1 downto 0) := (others => '0'); +begin + process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + freq_reg <= (others => '0'); + phase_acc <= (others => '0'); + phase_out_reg <= (others => '0'); + elsif enable = '1' then + freq_reg <= unsigned(freq_val); + if phase_load = '1' then + phase_acc <= unsigned(phase_val); + else + phase_acc <= phase_acc + freq_reg; + end if; + phase_out_reg <= std_logic_vector(phase_acc(N-1 downto (N-M))); + end if; + end if; + end process; + phase_out <= phase_out_reg; +end Behavioral; diff --git a/fpga/dds/dds-iq-sine-gen.vhd b/fpga/dds/dds-iq-sine-gen.vhd new file mode 100644 index 0000000..7c82bfb --- /dev/null +++ b/fpga/dds/dds-iq-sine-gen.vhd @@ -0,0 +1,84 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +--IQ DDS generator +--Copyright (C) 2017 David Shah +--Licensed under the MIT License + +entity dds_iq_sine_gen is + port( + clock : in std_logic; + reset : in std_logic; + enable : in std_logic; + frequency : in std_logic_vector(23 downto 0); --frequency setting word + global_phase : in std_logic_vector(23 downto 0); --global phase setting + global_phase_load : in std_logic; --assert to update phase + q_phase_offset : in std_logic_vector(11 downto 0); --phase shift between I and Q + i_amplitude : in std_logic_vector(7 downto 0); --I and Q amplitude scaling + q_amplitude : in std_logic_vector(7 downto 0); + + i_out : out std_logic_vector(11 downto 0); + q_out : out std_logic_vector(11 downto 0) + ); +end dds_iq_sine_gen; + +architecture Behavioral of dds_iq_sine_gen is + + signal dds_phase : std_logic_vector(11 downto 0); + signal i_phase_d, q_phase_d, i_phase_q, q_phase_q : std_logic_vector(11 downto 0); + signal i_sine, q_sine : std_logic_vector(11 downto 0); + signal i_scaled_d, q_scaled_d, i_scaled_q, q_scaled_q : std_logic_vector(19 downto 0); + +begin + dds : entity work.dds_core + generic map( + N => 24, + M => 12) + port map( + clock => clock, + reset => reset, + enable => enable, + freq_val => frequency, + phase_val => global_phase, + phase_load => global_phase_load, + phase_out => dds_phase); + + i_sine_tbl : entity work.dds_sine_table + port map( + clock => clock, + address => i_phase_q, + data => i_sine); + + q_sine_tbl : entity work.dds_sine_table + port map( + clock => clock, + address => q_phase_q, + data => q_sine); + + i_phase_d <= dds_phase; + q_phase_d <= std_logic_vector(unsigned(dds_phase) + unsigned(q_phase_offset)); + + i_scaled_d <= std_logic_vector(resize(signed(i_sine) * signed("0" & i_amplitude), 20)); + q_scaled_d <= std_logic_vector(resize(signed(q_sine) * signed("0" & q_amplitude), 20)); + + i_out <= i_scaled_q(19 downto 8); + q_out <= q_scaled_q(19 downto 8); + + process(clock) + begin + if rising_edge(clock) then + if reset = '1' then + i_phase_q <= (others => '0'); + q_phase_q <= (others => '0'); + i_scaled_q <= (others => '0'); + q_scaled_q <= (others => '0'); + elsif enable = '1' then + i_phase_q <= i_phase_d; + q_phase_q <= q_phase_d; + i_scaled_q <= i_scaled_d; + q_scaled_q <= q_scaled_d; + end if; + end if; + end process; +end Behavioral; diff --git a/fpga/dds/dds-testbench.vhd b/fpga/dds/dds-testbench.vhd new file mode 100644 index 0000000..a1c8ba5 --- /dev/null +++ b/fpga/dds/dds-testbench.vhd @@ -0,0 +1,69 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use STD.textio.ALL; + +entity dds_testbench is +end dds_testbench; + +architecture Behavioral of dds_testbench is + + signal clock : std_logic := '0'; + signal i_val, q_val : std_logic_vector(11 downto 0); + signal frequency : std_logic_vector(23 downto 0); + signal q_phase : std_logic_vector(11 downto 0); + signal i_amp, q_amp : std_logic_vector(7 downto 0); + + file outfile : text; +begin + + frequency <= x"051EB8"; --1MHz with a 50MHz clock + q_phase <= x"400"; --90 degree offset + i_amp <= x"FF"; + q_amp <= x"7F"; + + gen : entity work.dds_iq_sine_gen + port map( + clock => clock, + reset => '0', + enable => '1', + frequency => frequency, + global_phase => x"000000", + global_phase_load => '0', + q_phase_offset => q_phase, + i_amplitude => i_amp, + q_amplitude => q_amp, + i_out => i_val, + q_out => q_val); + + process + variable i_tmp, q_tmp : integer; + variable oline : line; + begin + + file_open(outfile, "output.csv", write_mode); + write(oline, string'("t, i, q,")); + writeline(outfile, oline); + for i in 1 to 1000 loop + wait for 10 ns; + clock <= '1'; + wait for 10 ns; + clock <= '0'; + + i_tmp := to_integer(signed(i_val)); + q_tmp := to_integer(signed(q_val)); + + write(oline, (now / 1 ns), left, 4); + write(oline, string'(", ")); + write(oline, i_tmp, left, 5); + write(oline, string'(", ")); + write(oline, q_tmp, left, 5); + write(oline, string'(", ")); + + writeline(outfile, oline); + end loop; + + file_close(outfile); + wait; + end process; +end Behavioral; diff --git a/fpga/dds/graphview.py b/fpga/dds/graphview.py new file mode 100644 index 0000000..b99f5e0 --- /dev/null +++ b/fpga/dds/graphview.py @@ -0,0 +1,33 @@ +# -*- coding: utf-8 -*- +""" +Created on Sun Nov 15 15:54:00 2015 + +@author: David +""" +import matplotlib.pyplot as plt +import sys +filename = sys.argv[1] + +times = [] +titles = [] +values = [] +spacing = 0 + +with open(filename) as f: + lines = f.readlines() + header = lines[0] + splitHeader = header.split(",") + titles = splitHeader[1:-1] + for i in range(0, len(titles)): + values.append([]) + for line in lines[1:]: + splitLine = line.split(",") + for i in range(1, len(titles)+1): + values[i-1].append(float(splitLine[i]) + ((i - 1) * spacing)) + times.append(float(splitLine[0])) + for i in range(0, len(titles)): + plt.plot(times, values[i], label=titles[i]) + + plt.gca().axes.get_yaxis().set_ticks([]) + plt.legend(bbox_to_anchor=(1.02, 1), loc=2, borderaxespad=0.) + plt.show() diff --git a/fpga/dds/sin-table-gen.py b/fpga/dds/sin-table-gen.py new file mode 100644 index 0000000..5d1e37b --- /dev/null +++ b/fpga/dds/sin-table-gen.py @@ -0,0 +1,40 @@ +import math +addr_bits = 12 +data_bits = 12 + +def to_bin(x, n): + return ('{0:0' + str(n) + 'b}').format(x)[-n:] + +with open("dds-sine-table.gen.vhd", 'w') as f: + f.write("--Autogenerated sine table - do not modify\n") + f.write("library IEEE;\n") + f.write("use IEEE.STD_LOGIC_1164.ALL;\n") + f.write("use IEEE.NUMERIC_STD.ALL;\n\n") + f.write("entity dds_sine_table is\n") + f.write("\tport(\n") + f.write("\t\tclock : in std_logic;\n") + f.write("\t\taddress : in std_logic_vector(" + str(addr_bits - 1) + " downto 0);\n") + f.write("\t\tdata : out std_logic_vector(" + str(data_bits - 1) + " downto 0));\n") + f.write("end dds_sine_table;\n\n") + f.write("architecture Behavioral of dds_sine_table is\n") + f.write("begin\n") + f.write("\tprocess(clock)\n") + f.write("\tbegin\n") + f.write("\t\tif rising_edge(clock) then\n") + f.write("\t\t\tcase address is\n") + for x in range(0, 2**addr_bits): + val = math.sin(2.0 * math.pi * (x / float(2**addr_bits))) + val *= (2**(data_bits - 1) - 1) + val = int(val) + if val < 0: + val = abs(val) + val = val ^ ((2**data_bits) - 1) + val += 1 + f.write("\t\t\t\twhen \"" + to_bin(x,addr_bits) + "\" => \n") + f.write("\t\t\t\t\tdata <= \"" + to_bin(val, data_bits) + "\";\n") + f.write("\t\t\t\twhen others => \n") + f.write("\t\t\t\t\tdata <= \"" + to_bin(0, data_bits) + "\";\n") + f.write("\t\t\tend case;\n") + f.write("\t\tend if;\n") + f.write("\tend process;\n") + f.write("end Behavioral;\n") diff --git a/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/4d72b0fa095d8e42.xci b/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/4d72b0fa095d8e42.xci new file mode 100644 index 0000000..c7dc70c --- /dev/null +++ b/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/4d72b0fa095d8e42.xci @@ -0,0 +1,204 @@ + + + xilinx.com + ipcache + 4d72b0fa095d8e42 + 0 + + + iq_sample_fifo + + + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + iq_sample_fifo + 64 + false + 13 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 0 + 8189 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 8188 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 24 + 8192 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 24 + 8192 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 13 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + false + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + false + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 13 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + artix7 + + xc7a50t + ftg256 + VHDL + + MIXED + -2 + + TRUE + TRUE + f9fab666 + 4d72b0fa095d8e42 + IP_Unknown + 2 + TRUE + . + + . + 2016.3 + GLOBAL + + + + diff --git a/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/iq_sample_fifo_sim_netlist.v b/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/iq_sample_fifo_sim_netlist.v new file mode 100755 index 0000000..3db3634 --- /dev/null +++ b/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/iq_sample_fifo_sim_netlist.v @@ -0,0 +1,7497 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 +// Date : Sat Apr 15 09:49:57 2017 +// Host : david-desktop-arch running 64-bit unknown +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ iq_sample_fifo_sim_netlist.v +// Design : iq_sample_fifo +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a50tftg256-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "iq_sample_fifo,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty); + (* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk; + (* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk; + (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [23:0]din; + (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; + (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; + (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [23:0]dout; + (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; + (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; + + wire [23:0]din; + wire [23:0]dout; + wire empty; + wire full; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + wire NLW_U0_almost_empty_UNCONNECTED; + wire NLW_U0_almost_full_UNCONNECTED; + wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; + wire NLW_U0_axi_ar_overflow_UNCONNECTED; + wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; + wire NLW_U0_axi_ar_prog_full_UNCONNECTED; + wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; + wire NLW_U0_axi_ar_underflow_UNCONNECTED; + wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; + wire NLW_U0_axi_aw_overflow_UNCONNECTED; + wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; + wire NLW_U0_axi_aw_prog_full_UNCONNECTED; + wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; + wire NLW_U0_axi_aw_underflow_UNCONNECTED; + wire NLW_U0_axi_b_dbiterr_UNCONNECTED; + wire NLW_U0_axi_b_overflow_UNCONNECTED; + wire NLW_U0_axi_b_prog_empty_UNCONNECTED; + wire NLW_U0_axi_b_prog_full_UNCONNECTED; + wire NLW_U0_axi_b_sbiterr_UNCONNECTED; + wire NLW_U0_axi_b_underflow_UNCONNECTED; + wire NLW_U0_axi_r_dbiterr_UNCONNECTED; + wire NLW_U0_axi_r_overflow_UNCONNECTED; + wire NLW_U0_axi_r_prog_empty_UNCONNECTED; + wire NLW_U0_axi_r_prog_full_UNCONNECTED; + wire NLW_U0_axi_r_sbiterr_UNCONNECTED; + wire NLW_U0_axi_r_underflow_UNCONNECTED; + wire NLW_U0_axi_w_dbiterr_UNCONNECTED; + wire NLW_U0_axi_w_overflow_UNCONNECTED; + wire NLW_U0_axi_w_prog_empty_UNCONNECTED; + wire NLW_U0_axi_w_prog_full_UNCONNECTED; + wire NLW_U0_axi_w_sbiterr_UNCONNECTED; + wire NLW_U0_axi_w_underflow_UNCONNECTED; + wire NLW_U0_axis_dbiterr_UNCONNECTED; + wire NLW_U0_axis_overflow_UNCONNECTED; + wire NLW_U0_axis_prog_empty_UNCONNECTED; + wire NLW_U0_axis_prog_full_UNCONNECTED; + wire NLW_U0_axis_sbiterr_UNCONNECTED; + wire NLW_U0_axis_underflow_UNCONNECTED; + wire NLW_U0_dbiterr_UNCONNECTED; + wire NLW_U0_m_axi_arvalid_UNCONNECTED; + wire NLW_U0_m_axi_awvalid_UNCONNECTED; + wire NLW_U0_m_axi_bready_UNCONNECTED; + wire NLW_U0_m_axi_rready_UNCONNECTED; + wire NLW_U0_m_axi_wlast_UNCONNECTED; + wire NLW_U0_m_axi_wvalid_UNCONNECTED; + wire NLW_U0_m_axis_tlast_UNCONNECTED; + wire NLW_U0_m_axis_tvalid_UNCONNECTED; + wire NLW_U0_overflow_UNCONNECTED; + wire NLW_U0_prog_empty_UNCONNECTED; + wire NLW_U0_prog_full_UNCONNECTED; + wire NLW_U0_rd_rst_busy_UNCONNECTED; + wire NLW_U0_s_axi_arready_UNCONNECTED; + wire NLW_U0_s_axi_awready_UNCONNECTED; + wire NLW_U0_s_axi_bvalid_UNCONNECTED; + wire NLW_U0_s_axi_rlast_UNCONNECTED; + wire NLW_U0_s_axi_rvalid_UNCONNECTED; + wire NLW_U0_s_axi_wready_UNCONNECTED; + wire NLW_U0_s_axis_tready_UNCONNECTED; + wire NLW_U0_sbiterr_UNCONNECTED; + wire NLW_U0_underflow_UNCONNECTED; + wire NLW_U0_valid_UNCONNECTED; + wire NLW_U0_wr_ack_UNCONNECTED; + wire NLW_U0_wr_rst_busy_UNCONNECTED; + wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; + wire [12:0]NLW_U0_data_count_UNCONNECTED; + wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; + wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; + wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; + wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; + wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; + wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; + wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; + wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; + wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; + wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; + wire [12:0]NLW_U0_rd_data_count_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; + wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; + wire [12:0]NLW_U0_wr_data_count_UNCONNECTED; + + (* C_ADD_NGC_CONSTRAINT = "0" *) + (* C_APPLICATION_TYPE_AXIS = "0" *) + (* C_APPLICATION_TYPE_RACH = "0" *) + (* C_APPLICATION_TYPE_RDCH = "0" *) + (* C_APPLICATION_TYPE_WACH = "0" *) + (* C_APPLICATION_TYPE_WDCH = "0" *) + (* C_APPLICATION_TYPE_WRCH = "0" *) + (* C_AXIS_TDATA_WIDTH = "8" *) + (* C_AXIS_TDEST_WIDTH = "1" *) + (* C_AXIS_TID_WIDTH = "1" *) + (* C_AXIS_TKEEP_WIDTH = "1" *) + (* C_AXIS_TSTRB_WIDTH = "1" *) + (* C_AXIS_TUSER_WIDTH = "4" *) + (* C_AXIS_TYPE = "0" *) + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "64" *) + (* C_AXI_ID_WIDTH = "1" *) + (* C_AXI_LEN_WIDTH = "8" *) + (* C_AXI_LOCK_WIDTH = "1" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_TYPE = "1" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_COMMON_CLOCK = "0" *) + (* C_COUNT_TYPE = "0" *) + (* C_DATA_COUNT_WIDTH = "13" *) + (* C_DEFAULT_VALUE = "BlankString" *) + (* C_DIN_WIDTH = "24" *) + (* C_DIN_WIDTH_AXIS = "1" *) + (* C_DIN_WIDTH_RACH = "32" *) + (* C_DIN_WIDTH_RDCH = "64" *) + (* C_DIN_WIDTH_WACH = "1" *) + (* C_DIN_WIDTH_WDCH = "64" *) + (* C_DIN_WIDTH_WRCH = "2" *) + (* C_DOUT_RST_VAL = "0" *) + (* C_DOUT_WIDTH = "24" *) + (* C_ENABLE_RLOCS = "0" *) + (* C_ENABLE_RST_SYNC = "1" *) + (* C_EN_SAFETY_CKT = "0" *) + (* C_ERROR_INJECTION_TYPE = "0" *) + (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) + (* C_ERROR_INJECTION_TYPE_RACH = "0" *) + (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WACH = "0" *) + (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) + (* C_FAMILY = "artix7" *) + (* C_FULL_FLAGS_RST_VAL = "0" *) + (* C_HAS_ALMOST_EMPTY = "0" *) + (* C_HAS_ALMOST_FULL = "0" *) + (* C_HAS_AXIS_TDATA = "1" *) + (* C_HAS_AXIS_TDEST = "0" *) + (* C_HAS_AXIS_TID = "0" *) + (* C_HAS_AXIS_TKEEP = "0" *) + (* C_HAS_AXIS_TLAST = "0" *) + (* C_HAS_AXIS_TREADY = "1" *) + (* C_HAS_AXIS_TSTRB = "0" *) + (* C_HAS_AXIS_TUSER = "1" *) + (* C_HAS_AXI_ARUSER = "0" *) + (* C_HAS_AXI_AWUSER = "0" *) + (* C_HAS_AXI_BUSER = "0" *) + (* C_HAS_AXI_ID = "0" *) + (* C_HAS_AXI_RD_CHANNEL = "1" *) + (* C_HAS_AXI_RUSER = "0" *) + (* C_HAS_AXI_WR_CHANNEL = "1" *) + (* C_HAS_AXI_WUSER = "0" *) + (* C_HAS_BACKUP = "0" *) + (* C_HAS_DATA_COUNT = "0" *) + (* C_HAS_DATA_COUNTS_AXIS = "0" *) + (* C_HAS_DATA_COUNTS_RACH = "0" *) + (* C_HAS_DATA_COUNTS_RDCH = "0" *) + (* C_HAS_DATA_COUNTS_WACH = "0" *) + (* C_HAS_DATA_COUNTS_WDCH = "0" *) + (* C_HAS_DATA_COUNTS_WRCH = "0" *) + (* C_HAS_INT_CLK = "0" *) + (* C_HAS_MASTER_CE = "0" *) + (* C_HAS_MEMINIT_FILE = "0" *) + (* C_HAS_OVERFLOW = "0" *) + (* C_HAS_PROG_FLAGS_AXIS = "0" *) + (* C_HAS_PROG_FLAGS_RACH = "0" *) + (* C_HAS_PROG_FLAGS_RDCH = "0" *) + (* C_HAS_PROG_FLAGS_WACH = "0" *) + (* C_HAS_PROG_FLAGS_WDCH = "0" *) + (* C_HAS_PROG_FLAGS_WRCH = "0" *) + (* C_HAS_RD_DATA_COUNT = "0" *) + (* C_HAS_RD_RST = "0" *) + (* C_HAS_RST = "0" *) + (* C_HAS_SLAVE_CE = "0" *) + (* C_HAS_SRST = "0" *) + (* C_HAS_UNDERFLOW = "0" *) + (* C_HAS_VALID = "0" *) + (* C_HAS_WR_ACK = "0" *) + (* C_HAS_WR_DATA_COUNT = "0" *) + (* C_HAS_WR_RST = "0" *) + (* C_IMPLEMENTATION_TYPE = "2" *) + (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) + (* C_IMPLEMENTATION_TYPE_RACH = "1" *) + (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WACH = "1" *) + (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) + (* C_INIT_WR_PNTR_VAL = "0" *) + (* C_INTERFACE_TYPE = "0" *) + (* C_MEMORY_TYPE = "1" *) + (* C_MIF_FILE_NAME = "BlankString" *) + (* C_MSGON_VAL = "1" *) + (* C_OPTIMIZATION_MODE = "0" *) + (* C_OVERFLOW_LOW = "0" *) + (* C_POWER_SAVING_MODE = "0" *) + (* C_PRELOAD_LATENCY = "1" *) + (* C_PRELOAD_REGS = "0" *) + (* C_PRIM_FIFO_TYPE = "8kx4" *) + (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) + (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) + (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) + (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) + (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) + (* C_PROG_EMPTY_TYPE = "0" *) + (* C_PROG_EMPTY_TYPE_AXIS = "0" *) + (* C_PROG_EMPTY_TYPE_RACH = "0" *) + (* C_PROG_EMPTY_TYPE_RDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WACH = "0" *) + (* C_PROG_EMPTY_TYPE_WDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WRCH = "0" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL = "8189" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) + (* C_PROG_FULL_THRESH_NEGATE_VAL = "8188" *) + (* C_PROG_FULL_TYPE = "0" *) + (* C_PROG_FULL_TYPE_AXIS = "0" *) + (* C_PROG_FULL_TYPE_RACH = "0" *) + (* C_PROG_FULL_TYPE_RDCH = "0" *) + (* C_PROG_FULL_TYPE_WACH = "0" *) + (* C_PROG_FULL_TYPE_WDCH = "0" *) + (* C_PROG_FULL_TYPE_WRCH = "0" *) + (* C_RACH_TYPE = "0" *) + (* C_RDCH_TYPE = "0" *) + (* C_RD_DATA_COUNT_WIDTH = "13" *) + (* C_RD_DEPTH = "8192" *) + (* C_RD_FREQ = "1" *) + (* C_RD_PNTR_WIDTH = "13" *) + (* C_REG_SLICE_MODE_AXIS = "0" *) + (* C_REG_SLICE_MODE_RACH = "0" *) + (* C_REG_SLICE_MODE_RDCH = "0" *) + (* C_REG_SLICE_MODE_WACH = "0" *) + (* C_REG_SLICE_MODE_WDCH = "0" *) + (* C_REG_SLICE_MODE_WRCH = "0" *) + (* C_SELECT_XPM = "0" *) + (* C_SYNCHRONIZER_STAGE = "2" *) + (* C_UNDERFLOW_LOW = "0" *) + (* C_USE_COMMON_OVERFLOW = "0" *) + (* C_USE_COMMON_UNDERFLOW = "0" *) + (* C_USE_DEFAULT_SETTINGS = "0" *) + (* C_USE_DOUT_RST = "0" *) + (* C_USE_ECC = "0" *) + (* C_USE_ECC_AXIS = "0" *) + (* C_USE_ECC_RACH = "0" *) + (* C_USE_ECC_RDCH = "0" *) + (* C_USE_ECC_WACH = "0" *) + (* C_USE_ECC_WDCH = "0" *) + (* C_USE_ECC_WRCH = "0" *) + (* C_USE_EMBEDDED_REG = "0" *) + (* C_USE_FIFO16_FLAGS = "0" *) + (* C_USE_FWFT_DATA_COUNT = "0" *) + (* C_USE_PIPELINE_REG = "0" *) + (* C_VALID_LOW = "0" *) + (* C_WACH_TYPE = "0" *) + (* C_WDCH_TYPE = "0" *) + (* C_WRCH_TYPE = "0" *) + (* C_WR_ACK_LOW = "0" *) + (* C_WR_DATA_COUNT_WIDTH = "13" *) + (* C_WR_DEPTH = "8192" *) + (* C_WR_DEPTH_AXIS = "1024" *) + (* C_WR_DEPTH_RACH = "16" *) + (* C_WR_DEPTH_RDCH = "1024" *) + (* C_WR_DEPTH_WACH = "16" *) + (* C_WR_DEPTH_WDCH = "1024" *) + (* C_WR_DEPTH_WRCH = "16" *) + (* C_WR_FREQ = "1" *) + (* C_WR_PNTR_WIDTH = "13" *) + (* C_WR_PNTR_WIDTH_AXIS = "10" *) + (* C_WR_PNTR_WIDTH_RACH = "4" *) + (* C_WR_PNTR_WIDTH_RDCH = "10" *) + (* C_WR_PNTR_WIDTH_WACH = "4" *) + (* C_WR_PNTR_WIDTH_WDCH = "10" *) + (* C_WR_PNTR_WIDTH_WRCH = "4" *) + (* C_WR_RESPONSE_LATENCY = "1" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0 + (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), + .almost_full(NLW_U0_almost_full_UNCONNECTED), + .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), + .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), + .axi_ar_injectdbiterr(1'b0), + .axi_ar_injectsbiterr(1'b0), + .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), + .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), + .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), + .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), + .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), + .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), + .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), + .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), + .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), + .axi_aw_injectdbiterr(1'b0), + .axi_aw_injectsbiterr(1'b0), + .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), + .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), + .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), + .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), + .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), + .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), + .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), + .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), + .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), + .axi_b_injectdbiterr(1'b0), + .axi_b_injectsbiterr(1'b0), + .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), + .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), + .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), + .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), + .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), + .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), + .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), + .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), + .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), + .axi_r_injectdbiterr(1'b0), + .axi_r_injectsbiterr(1'b0), + .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), + .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), + .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), + .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), + .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), + .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), + .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), + .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), + .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), + .axi_w_injectdbiterr(1'b0), + .axi_w_injectsbiterr(1'b0), + .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), + .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), + .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), + .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), + .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), + .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), + .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), + .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), + .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), + .axis_injectdbiterr(1'b0), + .axis_injectsbiterr(1'b0), + .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), + .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), + .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), + .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), + .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), + .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), + .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), + .backup(1'b0), + .backup_marker(1'b0), + .clk(1'b0), + .data_count(NLW_U0_data_count_UNCONNECTED[12:0]), + .dbiterr(NLW_U0_dbiterr_UNCONNECTED), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .int_clk(1'b0), + .m_aclk(1'b0), + .m_aclk_en(1'b0), + .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), + .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), + .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), + .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), + .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), + .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), + .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), + .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), + .m_axi_arready(1'b0), + .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), + .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), + .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), + .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), + .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), + .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), + .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), + .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), + .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), + .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), + .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), + .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), + .m_axi_awready(1'b0), + .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), + .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), + .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), + .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), + .m_axi_bid(1'b0), + .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), + .m_axi_bresp({1'b0,1'b0}), + .m_axi_buser(1'b0), + .m_axi_bvalid(1'b0), + .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_rid(1'b0), + .m_axi_rlast(1'b0), + .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), + .m_axi_rresp({1'b0,1'b0}), + .m_axi_ruser(1'b0), + .m_axi_rvalid(1'b0), + .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), + .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), + .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), + .m_axi_wready(1'b0), + .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), + .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), + .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), + .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]), + .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), + .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), + .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]), + .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), + .m_axis_tready(1'b0), + .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]), + .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), + .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), + .overflow(NLW_U0_overflow_UNCONNECTED), + .prog_empty(NLW_U0_prog_empty_UNCONNECTED), + .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full(NLW_U0_prog_full_UNCONNECTED), + .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .rd_clk(rd_clk), + .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[12:0]), + .rd_en(rd_en), + .rd_rst(1'b0), + .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), + .rst(1'b0), + .s_aclk(1'b0), + .s_aclk_en(1'b0), + .s_aresetn(1'b0), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid(1'b0), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlock(1'b0), + .s_axi_arprot({1'b0,1'b0,1'b0}), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(1'b0), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid(1'b0), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock(1'b0), + .s_axi_awprot({1'b0,1'b0,1'b0}), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(1'b0), + .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), + .s_axi_bready(1'b0), + .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), + .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), + .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), + .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), + .s_axi_rready(1'b0), + .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), + .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), + .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wid(1'b0), + .s_axi_wlast(1'b0), + .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), + .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wuser(1'b0), + .s_axi_wvalid(1'b0), + .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tdest(1'b0), + .s_axis_tid(1'b0), + .s_axis_tkeep(1'b0), + .s_axis_tlast(1'b0), + .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), + .s_axis_tstrb(1'b0), + .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tvalid(1'b0), + .sbiterr(NLW_U0_sbiterr_UNCONNECTED), + .sleep(1'b0), + .srst(1'b0), + .underflow(NLW_U0_underflow_UNCONNECTED), + .valid(NLW_U0_valid_UNCONNECTED), + .wr_ack(NLW_U0_wr_ack_UNCONNECTED), + .wr_clk(wr_clk), + .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[12:0]), + .wr_en(wr_en), + .wr_rst(1'b0), + .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr + (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); + output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; + + wire [12:0]Q; + wire [0:0]WEA; + wire [23:0]din; + wire [23:0]dout; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; + wire \ramloop[2].ram.r_n_0 ; + wire \ramloop[2].ram.r_n_1 ; + wire \ramloop[2].ram.r_n_2 ; + wire \ramloop[2].ram.r_n_3 ; + wire \ramloop[2].ram.r_n_4 ; + wire \ramloop[2].ram.r_n_5 ; + wire \ramloop[2].ram.r_n_6 ; + wire \ramloop[2].ram.r_n_7 ; + wire \ramloop[2].ram.r_n_8 ; + wire \ramloop[3].ram.r_n_0 ; + wire \ramloop[3].ram.r_n_1 ; + wire \ramloop[3].ram.r_n_2 ; + wire \ramloop[3].ram.r_n_3 ; + wire \ramloop[3].ram.r_n_4 ; + wire \ramloop[3].ram.r_n_5 ; + wire \ramloop[3].ram.r_n_6 ; + wire \ramloop[3].ram.r_n_7 ; + wire \ramloop[3].ram.r_n_8 ; + wire \ramloop[4].ram.r_n_0 ; + wire \ramloop[4].ram.r_n_1 ; + wire \ramloop[4].ram.r_n_2 ; + wire \ramloop[4].ram.r_n_3 ; + wire \ramloop[4].ram.r_n_4 ; + wire \ramloop[4].ram.r_n_5 ; + wire \ramloop[4].ram.r_n_6 ; + wire \ramloop[4].ram.r_n_7 ; + wire \ramloop[4].ram.r_n_8 ; + wire \ramloop[5].ram.r_n_0 ; + wire \ramloop[5].ram.r_n_1 ; + wire \ramloop[5].ram.r_n_2 ; + wire \ramloop[5].ram.r_n_3 ; + wire \ramloop[5].ram.r_n_4 ; + wire \ramloop[5].ram.r_n_5 ; + wire \ramloop[5].ram.r_n_6 ; + wire \ramloop[5].ram.r_n_7 ; + wire \ramloop[5].ram.r_n_8 ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux__parameterized0 \has_mux_b.B + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\ramloop[2].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\ramloop[5].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_8 ), + .DOBDO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .DOPBDOP(\ramloop[3].ram.r_n_8 ), + .dout(dout[23:6]), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .rd_clk(rd_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r + (.Q(Q), + .WEA(WEA), + .din(din[1:0]), + .dout(dout[1:0]), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r + (.Q(Q), + .WEA(WEA), + .din(din[5:2]), + .dout(dout[5:2]), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[14:6]), + .\dout[13] ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }), + .\dout[14] (\ramloop[2].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r + (.DOBDO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .DOPBDOP(\ramloop[3].ram.r_n_8 ), + .Q(Q[11:0]), + .WEA(WEA), + .din(din[14:6]), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[23:15]), + .\dout[22] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\dout[23] (\ramloop[4].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[23:15]), + .\dout[22] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\dout[23] (\ramloop[5].ram.r_n_8 ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_mux" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux__parameterized0 + (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 , + dout, + \gc0.count_d1_reg[12] , + rd_clk, + DOBDO, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + DOPBDOP, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ); + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ; + output [17:0]dout; + input \gc0.count_d1_reg[12] ; + input rd_clk; + input [7:0]DOBDO; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + input [0:0]DOPBDOP; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; + + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [17:0]dout; + wire \gc0.count_d1_reg[12] ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ; + wire rd_clk; + + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hAC)) + \dout[10]_INST_0 + (.I0(DOBDO[4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[4])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hAC)) + \dout[11]_INST_0 + (.I0(DOBDO[5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[5])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hAC)) + \dout[12]_INST_0 + (.I0(DOBDO[6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[6])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hAC)) + \dout[13]_INST_0 + (.I0(DOBDO[7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[7])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hAC)) + \dout[14]_INST_0 + (.I0(DOPBDOP), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[8])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hAC)) + \dout[15]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [0]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[9])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \dout[16]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [1]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[10])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \dout[17]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [2]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[11])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \dout[18]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [3]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[12])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \dout[19]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [4]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[13])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \dout[20]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [5]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[14])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \dout[21]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [6]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[15])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \dout[22]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [7]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[16])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \dout[23]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[17])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hAC)) + \dout[6]_INST_0 + (.I0(DOBDO[0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[0])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hAC)) + \dout[7]_INST_0 + (.I0(DOBDO[1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[1])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hAC)) + \dout[8]_INST_0 + (.I0(DOBDO[2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[2])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hAC)) + \dout[9]_INST_0 + (.I0(DOBDO[3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[3])); + FDRE #( + .INIT(1'b0)) + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(\gc0.count_d1_reg[12] ), + .Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .R(1'b0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA); + output [1:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [1:0]din; + input [0:0]WEA; + + wire [12:0]Q; + wire [0:0]WEA; + wire [1:0]din; + wire [1:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA); + output [3:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [3:0]din; + input [0:0]WEA; + + wire [12:0]Q; + wire [0:0]WEA; + wire [3:0]din; + wire [3:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 + (\dout[13] , + \dout[14] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[13] ; + output [0:0]\dout[14] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[13] ; + wire [0:0]\dout[14] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[13] (\dout[13] ), + .\dout[14] (\dout[14] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 + (DOBDO, + DOPBDOP, + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]DOBDO; + output [0:0]DOPBDOP; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram + (.DOBDO(DOBDO), + .DOPBDOP(DOPBDOP), + .Q(Q), + .WEA(WEA), + .din(din), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[22] (\dout[22] ), + .\dout[23] (\dout[23] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[22] (\dout[22] ), + .\dout[23] (\dout[23] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA); + output [1:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [1:0]din; + input [0:0]WEA; + + wire [12:0]Q; + wire [0:0]WEA; + wire [1:0]din; + wire [1:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; + wire [15:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; + wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; + wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB18E1 #( + .DOA_REG(0), + .DOB_REG(0), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(18'h00000), + .INIT_B(18'h00000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(2), + .READ_WIDTH_B(2), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(18'h00000), + .SRVAL_B(18'h00000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(2), + .WRITE_WIDTH_B(2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram + (.ADDRARDADDR({Q,1'b0}), + .ADDRBWRADDR({\gc0.count_d1_reg[12] ,1'b0}), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:2],dout}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .WEA({WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA); + output [3:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [3:0]din; + input [0:0]WEA; + + wire [12:0]Q; + wire [0:0]WEA; + wire [3:0]din; + wire [3:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(4), + .READ_WIDTH_B(4), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(4), + .WRITE_WIDTH_B(4)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[12] ,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:4],dout}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 + (\dout[13] , + \dout[14] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[13] ; + output [0:0]\dout[14] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[13] ; + wire [0:0]\dout[14] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[13] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[14] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 + (DOBDO, + DOPBDOP, + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]DOBDO; + output [0:0]DOPBDOP; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],DOBDO}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[22] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[23] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[22] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[23] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top + (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); + output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; + + wire [12:0]Q; + wire [0:0]WEA; + wire [23:0]din; + wire [23:0]dout; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 + (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); + output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; + + wire [12:0]Q; + wire [0:0]WEA; + wire [23:0]din; + wire [23:0]dout; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth + (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); + output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; + + wire [12:0]Q; + wire [0:0]WEA; + wire [23:0]din; + wire [23:0]dout; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs + (ram_full_i_reg, + RD_PNTR_WR, + ram_full_i_reg_0, + WR_PNTR_RD, + Q, + D, + rd_clk, + wr_clk, + \gic0.gc0.count_d2_reg[12] , + bin2gray, + I6); + output ram_full_i_reg; + output [11:0]RD_PNTR_WR; + output ram_full_i_reg_0; + output [12:0]WR_PNTR_RD; + input [0:0]Q; + input [0:0]D; + input rd_clk; + input wr_clk; + input [0:0]\gic0.gc0.count_d2_reg[12] ; + input [11:0]bin2gray; + input [12:0]I6; + + wire [0:0]D; + wire [12:0]I6; + wire [0:0]Q; + wire [11:0]RD_PNTR_WR; + wire [12:0]WR_PNTR_RD; + wire [11:0]bin2gray; + wire [0:0]\gic0.gc0.count_d2_reg[12] ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ; + wire [10:0]gray2bin; + wire p_0_out; + wire [12:12]p_23_out; + wire [12:0]p_3_out; + wire [12:0]p_4_out; + wire [12:12]p_5_out; + wire [12:12]p_6_out; + wire ram_full_i_reg; + wire ram_full_i_reg_0; + wire rd_clk; + wire [12:0]rd_pntr_gc; + wire wr_clk; + wire [12:0]wr_pntr_gc; + + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1 + (.I0(p_23_out), + .I1(Q), + .O(ram_full_i_reg)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1__0 + (.I0(p_23_out), + .I1(D), + .O(ram_full_i_reg_0)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \gnxpm_cdc.gsync_stage[1].rd_stg_inst + (.in0(wr_pntr_gc), + .out(p_3_out), + .rd_clk(rd_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_3 \gnxpm_cdc.gsync_stage[1].wr_stg_inst + (.Q(rd_pntr_gc), + .out(p_4_out), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_4 \gnxpm_cdc.gsync_stage[2].rd_stg_inst + (.D({p_0_out,gray2bin}), + .\gnxpm_cdc.wr_pntr_bin_reg[12] (p_5_out), + .out(p_3_out), + .rd_clk(rd_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_5 \gnxpm_cdc.gsync_stage[2].wr_stg_inst + (.D({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 }), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (p_6_out), + .out(p_4_out), + .wr_clk(wr_clk)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ), + .Q(RD_PNTR_WR[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), + .Q(RD_PNTR_WR[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), + .Q(RD_PNTR_WR[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(p_6_out), + .Q(p_23_out), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ), + .Q(RD_PNTR_WR[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ), + .Q(RD_PNTR_WR[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ), + .Q(RD_PNTR_WR[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), + .Q(RD_PNTR_WR[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), + .Q(RD_PNTR_WR[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), + .Q(RD_PNTR_WR[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), + .Q(RD_PNTR_WR[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), + .Q(RD_PNTR_WR[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), + .Q(RD_PNTR_WR[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(I6[0]), + .Q(rd_pntr_gc[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(I6[10]), + .Q(rd_pntr_gc[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(I6[11]), + .Q(rd_pntr_gc[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(I6[12]), + .Q(rd_pntr_gc[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(I6[1]), + .Q(rd_pntr_gc[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(I6[2]), + .Q(rd_pntr_gc[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(I6[3]), + .Q(rd_pntr_gc[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(I6[4]), + .Q(rd_pntr_gc[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(I6[5]), + .Q(rd_pntr_gc[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(I6[6]), + .Q(rd_pntr_gc[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(I6[7]), + .Q(rd_pntr_gc[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(I6[8]), + .Q(rd_pntr_gc[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(I6[9]), + .Q(rd_pntr_gc[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[0]), + .Q(WR_PNTR_RD[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[10]), + .Q(WR_PNTR_RD[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(p_0_out), + .Q(WR_PNTR_RD[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(p_5_out), + .Q(WR_PNTR_RD[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[1]), + .Q(WR_PNTR_RD[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[2]), + .Q(WR_PNTR_RD[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[3]), + .Q(WR_PNTR_RD[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[4]), + .Q(WR_PNTR_RD[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[5]), + .Q(WR_PNTR_RD[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[6]), + .Q(WR_PNTR_RD[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[7]), + .Q(WR_PNTR_RD[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[8]), + .Q(WR_PNTR_RD[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[9]), + .Q(WR_PNTR_RD[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[0]), + .Q(wr_pntr_gc[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[10]), + .Q(wr_pntr_gc[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[11]), + .Q(wr_pntr_gc[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(\gic0.gc0.count_d2_reg[12] ), + .Q(wr_pntr_gc[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[1]), + .Q(wr_pntr_gc[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[2]), + .Q(wr_pntr_gc[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[3]), + .Q(wr_pntr_gc[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[4]), + .Q(wr_pntr_gc[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[5]), + .Q(wr_pntr_gc[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[6]), + .Q(wr_pntr_gc[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[7]), + .Q(wr_pntr_gc[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[8]), + .Q(wr_pntr_gc[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[9]), + .Q(wr_pntr_gc[9]), + .R(1'b0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare + (ram_full_i_reg, + \gnxpm_cdc.rd_pntr_bin_reg[12] , + wr_en, + out, + comp2, + \gic0.gc0.count_d1_reg[11] , + RD_PNTR_WR); + output ram_full_i_reg; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; + input wr_en; + input out; + input comp2; + input [11:0]\gic0.gc0.count_d1_reg[11] ; + input [11:0]RD_PNTR_WR; + + wire [11:0]RD_PNTR_WR; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp1; + wire comp2; + wire [11:0]\gic0.gc0.count_d1_reg[11] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; + wire out; + wire ram_full_i_reg; + wire [5:0]v1_reg; + wire wr_en; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [0]), + .I1(RD_PNTR_WR[0]), + .I2(\gic0.gc0.count_d1_reg[11] [1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [2]), + .I1(RD_PNTR_WR[2]), + .I2(\gic0.gc0.count_d1_reg[11] [3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [4]), + .I1(RD_PNTR_WR[4]), + .I2(\gic0.gc0.count_d1_reg[11] [5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [6]), + .I1(RD_PNTR_WR[6]), + .I2(\gic0.gc0.count_d1_reg[11] [7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp1,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gnxpm_cdc.rd_pntr_bin_reg[12] ,v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [8]), + .I1(RD_PNTR_WR[8]), + .I2(\gic0.gc0.count_d1_reg[11] [9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [10]), + .I1(RD_PNTR_WR[10]), + .I2(\gic0.gc0.count_d1_reg[11] [11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); + LUT4 #( + .INIT(16'hAEAA)) + ram_full_i_i_1 + (.I0(comp1), + .I1(wr_en), + .I2(out), + .I3(comp2), + .O(ram_full_i_reg)); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 + (comp2, + \gnxpm_cdc.rd_pntr_bin_reg[12] , + D, + RD_PNTR_WR); + output comp2; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; + input [11:0]D; + input [11:0]RD_PNTR_WR; + + wire [11:0]D; + wire [11:0]RD_PNTR_WR; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp2; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(D[0]), + .I1(RD_PNTR_WR[0]), + .I2(D[1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(D[2]), + .I1(RD_PNTR_WR[2]), + .I2(D[3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(D[4]), + .I1(RD_PNTR_WR[4]), + .I2(D[5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(D[6]), + .I1(RD_PNTR_WR[6]), + .I2(D[7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp2,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gnxpm_cdc.rd_pntr_bin_reg[12] ,v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(D[8]), + .I1(RD_PNTR_WR[8]), + .I2(D[9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(D[10]), + .I1(RD_PNTR_WR[10]), + .I2(D[11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 + (comp0, + \gc0.count_d1_reg[12] , + WR_PNTR_RD, + Q); + output comp0; + input \gc0.count_d1_reg[12] ; + input [11:0]WR_PNTR_RD; + input [11:0]Q; + + wire [11:0]Q; + wire [11:0]WR_PNTR_RD; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp0; + wire \gc0.count_d1_reg[12] ; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(Q[0]), + .I2(WR_PNTR_RD[1]), + .I3(Q[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(Q[2]), + .I2(WR_PNTR_RD[3]), + .I3(Q[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(Q[4]), + .I2(WR_PNTR_RD[5]), + .I3(Q[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(Q[6]), + .I2(WR_PNTR_RD[7]), + .I3(Q[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp0,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gc0.count_d1_reg[12] ,v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(Q[8]), + .I2(WR_PNTR_RD[9]), + .I3(Q[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(Q[10]), + .I2(WR_PNTR_RD[11]), + .I3(Q[11]), + .O(v1_reg[5])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 + (comp1, + \gc0.count_reg[12] , + WR_PNTR_RD, + D); + output comp1; + input \gc0.count_reg[12] ; + input [11:0]WR_PNTR_RD; + input [11:0]D; + + wire [11:0]D; + wire [11:0]WR_PNTR_RD; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp1; + wire \gc0.count_reg[12] ; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(D[0]), + .I2(WR_PNTR_RD[1]), + .I3(D[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(D[2]), + .I2(WR_PNTR_RD[3]), + .I3(D[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(D[4]), + .I2(WR_PNTR_RD[5]), + .I3(D[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(D[6]), + .I2(WR_PNTR_RD[7]), + .I3(D[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp1,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gc0.count_reg[12] ,v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(D[8]), + .I2(WR_PNTR_RD[9]), + .I3(D[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(D[10]), + .I2(WR_PNTR_RD[11]), + .I3(D[11]), + .O(v1_reg[5])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo + (dout, + empty, + full, + wr_en, + rd_en, + wr_clk, + rd_clk, + din); + output [23:0]dout; + output empty; + output full; + input wr_en; + input rd_en; + input wr_clk; + input rd_clk; + input [23:0]din; + + wire [11:0]bin2gray; + wire [23:0]din; + wire [23:0]dout; + wire empty; + wire full; + wire [1:1]\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; + wire [1:1]\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; + wire \gntv_or_sync_fifo.gcx.clkx_n_0 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_13 ; + wire \gntv_or_sync_fifo.gl0.rd_n_1 ; + wire \gntv_or_sync_fifo.gl0.rd_n_15 ; + wire \gntv_or_sync_fifo.gl0.rd_n_16 ; + wire \gntv_or_sync_fifo.gl0.rd_n_17 ; + wire \gntv_or_sync_fifo.gl0.rd_n_18 ; + wire \gntv_or_sync_fifo.gl0.rd_n_19 ; + wire \gntv_or_sync_fifo.gl0.rd_n_20 ; + wire \gntv_or_sync_fifo.gl0.rd_n_21 ; + wire \gntv_or_sync_fifo.gl0.rd_n_22 ; + wire \gntv_or_sync_fifo.gl0.rd_n_23 ; + wire \gntv_or_sync_fifo.gl0.rd_n_24 ; + wire \gntv_or_sync_fifo.gl0.rd_n_25 ; + wire \gntv_or_sync_fifo.gl0.rd_n_26 ; + wire \gntv_or_sync_fifo.gl0.rd_n_27 ; + wire \gntv_or_sync_fifo.gl0.rd_n_29 ; + wire \gntv_or_sync_fifo.gl0.wr_n_1 ; + wire \gntv_or_sync_fifo.gl0.wr_n_15 ; + wire \gntv_or_sync_fifo.gl0.wr_n_31 ; + wire [12:0]p_0_out; + wire [12:0]p_12_out; + wire [12:12]p_13_out; + wire [12:0]p_22_out; + wire [11:0]p_23_out; + wire rd_clk; + wire rd_en; + wire sel_pipe; + wire wr_clk; + wire wr_en; + wire [12:12]wr_pntr_plus2; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx + (.D(wr_pntr_plus2), + .I6({p_0_out[12],\gntv_or_sync_fifo.gl0.rd_n_16 ,\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 ,\gntv_or_sync_fifo.gl0.rd_n_26 ,\gntv_or_sync_fifo.gl0.rd_n_27 }), + .Q(p_13_out), + .RD_PNTR_WR(p_23_out), + .WR_PNTR_RD(p_22_out), + .bin2gray(bin2gray), + .\gic0.gc0.count_d2_reg[12] (p_12_out[12]), + .ram_full_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ), + .ram_full_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_13 ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.rd_n_1 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.rd_n_29 ), + .I6({\gntv_or_sync_fifo.gl0.rd_n_16 ,\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 ,\gntv_or_sync_fifo.gl0.rd_n_26 ,\gntv_or_sync_fifo.gl0.rd_n_27 }), + .Q(p_0_out), + .WR_PNTR_RD(p_22_out), + .empty(empty), + .enb_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_15 ), + .rd_clk(rd_clk), + .rd_en(rd_en), + .sel_pipe(sel_pipe)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.wr_n_1 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.wr_n_31 ), + .Q(p_12_out), + .RD_PNTR_WR(p_23_out), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_15 ), + .bin2gray(bin2gray), + .ena_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ), + .full(full), + .\gic0.gc0.count_d2_reg[12] (p_13_out), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gntv_or_sync_fifo.gcx.clkx_n_0 ), + .\gnxpm_cdc.rd_pntr_bin_reg[12]_0 (\gntv_or_sync_fifo.gcx.clkx_n_13 ), + .wr_clk(wr_clk), + .wr_en(wr_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem + (.Q(p_12_out), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_15 ), + .din(din), + .dout(dout), + .ena_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ), + .enb_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ), + .\gc0.count_d1_reg[12] (p_0_out), + .\gc0.count_d1_reg[12]_0 (\gntv_or_sync_fifo.gl0.rd_n_15 ), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_29 ), + .ram_empty_fb_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_1 ), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_31 ), + .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_1 ), + .rd_clk(rd_clk), + .sel_pipe(sel_pipe), + .wr_clk(wr_clk)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top + (dout, + empty, + full, + wr_en, + rd_en, + wr_clk, + rd_clk, + din); + output [23:0]dout; + output empty; + output full; + input wr_en; + input rd_en; + input wr_clk; + input rd_clk; + input [23:0]din; + + wire [23:0]din; + wire [23:0]dout; + wire empty; + wire full; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf + (.din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) +(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) +(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) +(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) +(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) +(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) +(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) +(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) +(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) +(* C_DATA_COUNT_WIDTH = "13" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "24" *) +(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) +(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) +(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "24" *) (* C_ENABLE_RLOCS = "0" *) +(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) +(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) +(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) +(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *) +(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) +(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) +(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) +(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) +(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) +(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) +(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) +(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) +(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) +(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) +(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) +(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) +(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "0" *) (* C_HAS_SLAVE_CE = "0" *) +(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) +(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) +(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) +(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) +(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) +(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) +(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) +(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "8kx4" *) +(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) +(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) +(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) +(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL = "8189" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "8188" *) (* C_PROG_FULL_TYPE = "0" *) +(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) +(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) +(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "13" *) +(* C_RD_DEPTH = "8192" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "13" *) +(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) +(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) +(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) +(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) +(* C_USE_DOUT_RST = "0" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) +(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) +(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) +(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) +(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) +(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "13" *) +(* C_WR_DEPTH = "8192" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) +(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) +(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "13" *) +(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) +(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) +(* C_WR_RESPONSE_LATENCY = "1" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 + (backup, + backup_marker, + clk, + rst, + srst, + wr_clk, + wr_rst, + rd_clk, + rd_rst, + din, + wr_en, + rd_en, + prog_empty_thresh, + prog_empty_thresh_assert, + prog_empty_thresh_negate, + prog_full_thresh, + prog_full_thresh_assert, + prog_full_thresh_negate, + int_clk, + injectdbiterr, + injectsbiterr, + sleep, + dout, + full, + almost_full, + wr_ack, + overflow, + empty, + almost_empty, + valid, + underflow, + data_count, + rd_data_count, + wr_data_count, + prog_full, + prog_empty, + sbiterr, + dbiterr, + wr_rst_busy, + rd_rst_busy, + m_aclk, + s_aclk, + s_aresetn, + m_aclk_en, + s_aclk_en, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awregion, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + m_axi_awregion, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arregion, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arqos, + m_axi_arregion, + m_axi_aruser, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_ruser, + m_axi_rvalid, + m_axi_rready, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tstrb, + s_axis_tkeep, + s_axis_tlast, + s_axis_tid, + s_axis_tdest, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tstrb, + m_axis_tkeep, + m_axis_tlast, + m_axis_tid, + m_axis_tdest, + m_axis_tuser, + axi_aw_injectsbiterr, + axi_aw_injectdbiterr, + axi_aw_prog_full_thresh, + axi_aw_prog_empty_thresh, + axi_aw_data_count, + axi_aw_wr_data_count, + axi_aw_rd_data_count, + axi_aw_sbiterr, + axi_aw_dbiterr, + axi_aw_overflow, + axi_aw_underflow, + axi_aw_prog_full, + axi_aw_prog_empty, + axi_w_injectsbiterr, + axi_w_injectdbiterr, + axi_w_prog_full_thresh, + axi_w_prog_empty_thresh, + axi_w_data_count, + axi_w_wr_data_count, + axi_w_rd_data_count, + axi_w_sbiterr, + axi_w_dbiterr, + axi_w_overflow, + axi_w_underflow, + axi_w_prog_full, + axi_w_prog_empty, + axi_b_injectsbiterr, + axi_b_injectdbiterr, + axi_b_prog_full_thresh, + axi_b_prog_empty_thresh, + axi_b_data_count, + axi_b_wr_data_count, + axi_b_rd_data_count, + axi_b_sbiterr, + axi_b_dbiterr, + axi_b_overflow, + axi_b_underflow, + axi_b_prog_full, + axi_b_prog_empty, + axi_ar_injectsbiterr, + axi_ar_injectdbiterr, + axi_ar_prog_full_thresh, + axi_ar_prog_empty_thresh, + axi_ar_data_count, + axi_ar_wr_data_count, + axi_ar_rd_data_count, + axi_ar_sbiterr, + axi_ar_dbiterr, + axi_ar_overflow, + axi_ar_underflow, + axi_ar_prog_full, + axi_ar_prog_empty, + axi_r_injectsbiterr, + axi_r_injectdbiterr, + axi_r_prog_full_thresh, + axi_r_prog_empty_thresh, + axi_r_data_count, + axi_r_wr_data_count, + axi_r_rd_data_count, + axi_r_sbiterr, + axi_r_dbiterr, + axi_r_overflow, + axi_r_underflow, + axi_r_prog_full, + axi_r_prog_empty, + axis_injectsbiterr, + axis_injectdbiterr, + axis_prog_full_thresh, + axis_prog_empty_thresh, + axis_data_count, + axis_wr_data_count, + axis_rd_data_count, + axis_sbiterr, + axis_dbiterr, + axis_overflow, + axis_underflow, + axis_prog_full, + axis_prog_empty); + input backup; + input backup_marker; + input clk; + input rst; + input srst; + input wr_clk; + input wr_rst; + input rd_clk; + input rd_rst; + input [23:0]din; + input wr_en; + input rd_en; + input [12:0]prog_empty_thresh; + input [12:0]prog_empty_thresh_assert; + input [12:0]prog_empty_thresh_negate; + input [12:0]prog_full_thresh; + input [12:0]prog_full_thresh_assert; + input [12:0]prog_full_thresh_negate; + input int_clk; + input injectdbiterr; + input injectsbiterr; + input sleep; + output [23:0]dout; + output full; + output almost_full; + output wr_ack; + output overflow; + output empty; + output almost_empty; + output valid; + output underflow; + output [12:0]data_count; + output [12:0]rd_data_count; + output [12:0]wr_data_count; + output prog_full; + output prog_empty; + output sbiterr; + output dbiterr; + output wr_rst_busy; + output rd_rst_busy; + input m_aclk; + input s_aclk; + input s_aresetn; + input m_aclk_en; + input s_aclk_en; + input [0:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [0:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awqos; + input [3:0]s_axi_awregion; + input [0:0]s_axi_awuser; + input s_axi_awvalid; + output s_axi_awready; + input [0:0]s_axi_wid; + input [63:0]s_axi_wdata; + input [7:0]s_axi_wstrb; + input s_axi_wlast; + input [0:0]s_axi_wuser; + input s_axi_wvalid; + output s_axi_wready; + output [0:0]s_axi_bid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_buser; + output s_axi_bvalid; + input s_axi_bready; + output [0:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [7:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [0:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awqos; + output [3:0]m_axi_awregion; + output [0:0]m_axi_awuser; + output m_axi_awvalid; + input m_axi_awready; + output [0:0]m_axi_wid; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output m_axi_wlast; + output [0:0]m_axi_wuser; + output m_axi_wvalid; + input m_axi_wready; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_buser; + input m_axi_bvalid; + output m_axi_bready; + input [0:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [0:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + input [3:0]s_axi_arregion; + input [0:0]s_axi_aruser; + input s_axi_arvalid; + output s_axi_arready; + output [0:0]s_axi_rid; + output [63:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output [0:0]s_axi_ruser; + output s_axi_rvalid; + input s_axi_rready; + output [0:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [7:0]m_axi_arlen; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [0:0]m_axi_arlock; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arqos; + output [3:0]m_axi_arregion; + output [0:0]m_axi_aruser; + output m_axi_arvalid; + input m_axi_arready; + input [0:0]m_axi_rid; + input [63:0]m_axi_rdata; + input [1:0]m_axi_rresp; + input m_axi_rlast; + input [0:0]m_axi_ruser; + input m_axi_rvalid; + output m_axi_rready; + input s_axis_tvalid; + output s_axis_tready; + input [7:0]s_axis_tdata; + input [0:0]s_axis_tstrb; + input [0:0]s_axis_tkeep; + input s_axis_tlast; + input [0:0]s_axis_tid; + input [0:0]s_axis_tdest; + input [3:0]s_axis_tuser; + output m_axis_tvalid; + input m_axis_tready; + output [7:0]m_axis_tdata; + output [0:0]m_axis_tstrb; + output [0:0]m_axis_tkeep; + output m_axis_tlast; + output [0:0]m_axis_tid; + output [0:0]m_axis_tdest; + output [3:0]m_axis_tuser; + input axi_aw_injectsbiterr; + input axi_aw_injectdbiterr; + input [3:0]axi_aw_prog_full_thresh; + input [3:0]axi_aw_prog_empty_thresh; + output [4:0]axi_aw_data_count; + output [4:0]axi_aw_wr_data_count; + output [4:0]axi_aw_rd_data_count; + output axi_aw_sbiterr; + output axi_aw_dbiterr; + output axi_aw_overflow; + output axi_aw_underflow; + output axi_aw_prog_full; + output axi_aw_prog_empty; + input axi_w_injectsbiterr; + input axi_w_injectdbiterr; + input [9:0]axi_w_prog_full_thresh; + input [9:0]axi_w_prog_empty_thresh; + output [10:0]axi_w_data_count; + output [10:0]axi_w_wr_data_count; + output [10:0]axi_w_rd_data_count; + output axi_w_sbiterr; + output axi_w_dbiterr; + output axi_w_overflow; + output axi_w_underflow; + output axi_w_prog_full; + output axi_w_prog_empty; + input axi_b_injectsbiterr; + input axi_b_injectdbiterr; + input [3:0]axi_b_prog_full_thresh; + input [3:0]axi_b_prog_empty_thresh; + output [4:0]axi_b_data_count; + output [4:0]axi_b_wr_data_count; + output [4:0]axi_b_rd_data_count; + output axi_b_sbiterr; + output axi_b_dbiterr; + output axi_b_overflow; + output axi_b_underflow; + output axi_b_prog_full; + output axi_b_prog_empty; + input axi_ar_injectsbiterr; + input axi_ar_injectdbiterr; + input [3:0]axi_ar_prog_full_thresh; + input [3:0]axi_ar_prog_empty_thresh; + output [4:0]axi_ar_data_count; + output [4:0]axi_ar_wr_data_count; + output [4:0]axi_ar_rd_data_count; + output axi_ar_sbiterr; + output axi_ar_dbiterr; + output axi_ar_overflow; + output axi_ar_underflow; + output axi_ar_prog_full; + output axi_ar_prog_empty; + input axi_r_injectsbiterr; + input axi_r_injectdbiterr; + input [9:0]axi_r_prog_full_thresh; + input [9:0]axi_r_prog_empty_thresh; + output [10:0]axi_r_data_count; + output [10:0]axi_r_wr_data_count; + output [10:0]axi_r_rd_data_count; + output axi_r_sbiterr; + output axi_r_dbiterr; + output axi_r_overflow; + output axi_r_underflow; + output axi_r_prog_full; + output axi_r_prog_empty; + input axis_injectsbiterr; + input axis_injectdbiterr; + input [9:0]axis_prog_full_thresh; + input [9:0]axis_prog_empty_thresh; + output [10:0]axis_data_count; + output [10:0]axis_wr_data_count; + output [10:0]axis_rd_data_count; + output axis_sbiterr; + output axis_dbiterr; + output axis_overflow; + output axis_underflow; + output axis_prog_full; + output axis_prog_empty; + + wire \ ; + wire \ ; + wire [23:0]din; + wire [23:0]dout; + wire empty; + wire full; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + assign almost_empty = \ ; + assign almost_full = \ ; + assign axi_ar_data_count[4] = \ ; + assign axi_ar_data_count[3] = \ ; + assign axi_ar_data_count[2] = \ ; + assign axi_ar_data_count[1] = \ ; + assign axi_ar_data_count[0] = \ ; + assign axi_ar_dbiterr = \ ; + assign axi_ar_overflow = \ ; + assign axi_ar_prog_empty = \ ; + assign axi_ar_prog_full = \ ; + assign axi_ar_rd_data_count[4] = \ ; + assign axi_ar_rd_data_count[3] = \ ; + assign axi_ar_rd_data_count[2] = \ ; + assign axi_ar_rd_data_count[1] = \ ; + assign axi_ar_rd_data_count[0] = \ ; + assign axi_ar_sbiterr = \ ; + assign axi_ar_underflow = \ ; + assign axi_ar_wr_data_count[4] = \ ; + assign axi_ar_wr_data_count[3] = \ ; + assign axi_ar_wr_data_count[2] = \ ; + assign axi_ar_wr_data_count[1] = \ ; + assign axi_ar_wr_data_count[0] = \ ; + assign axi_aw_data_count[4] = \ ; + assign axi_aw_data_count[3] = \ ; + assign axi_aw_data_count[2] = \ ; + assign axi_aw_data_count[1] = \ ; + assign axi_aw_data_count[0] = \ ; + assign axi_aw_dbiterr = \ ; + assign axi_aw_overflow = \ ; + assign axi_aw_prog_empty = \ ; + assign axi_aw_prog_full = \ ; + assign axi_aw_rd_data_count[4] = \ ; + assign axi_aw_rd_data_count[3] = \ ; + assign axi_aw_rd_data_count[2] = \ ; + assign axi_aw_rd_data_count[1] = \ ; + assign axi_aw_rd_data_count[0] = \ ; + assign axi_aw_sbiterr = \ ; + assign axi_aw_underflow = \ ; + assign axi_aw_wr_data_count[4] = \ ; + assign axi_aw_wr_data_count[3] = \ ; + assign axi_aw_wr_data_count[2] = \ ; + assign axi_aw_wr_data_count[1] = \ ; + assign axi_aw_wr_data_count[0] = \ ; + assign axi_b_data_count[4] = \ ; + assign axi_b_data_count[3] = \ ; + assign axi_b_data_count[2] = \ ; + assign axi_b_data_count[1] = \ ; + assign axi_b_data_count[0] = \ ; + assign axi_b_dbiterr = \ ; + assign axi_b_overflow = \ ; + assign axi_b_prog_empty = \ ; + assign axi_b_prog_full = \ ; + assign axi_b_rd_data_count[4] = \ ; + assign axi_b_rd_data_count[3] = \ ; + assign axi_b_rd_data_count[2] = \ ; + assign axi_b_rd_data_count[1] = \ ; + assign axi_b_rd_data_count[0] = \ ; + assign axi_b_sbiterr = \ ; + assign axi_b_underflow = \ ; + assign axi_b_wr_data_count[4] = \ ; + assign axi_b_wr_data_count[3] = \ ; + assign axi_b_wr_data_count[2] = \ ; + assign axi_b_wr_data_count[1] = \ ; + assign axi_b_wr_data_count[0] = \ ; + assign axi_r_data_count[10] = \ ; + assign axi_r_data_count[9] = \ ; + assign axi_r_data_count[8] = \ ; + assign axi_r_data_count[7] = \ ; + assign axi_r_data_count[6] = \ ; + assign axi_r_data_count[5] = \ ; + assign axi_r_data_count[4] = \ ; + assign axi_r_data_count[3] = \ ; + assign axi_r_data_count[2] = \ ; + assign axi_r_data_count[1] = \ ; + assign axi_r_data_count[0] = \ ; + assign axi_r_dbiterr = \ ; + assign axi_r_overflow = \ ; + assign axi_r_prog_empty = \ ; + assign axi_r_prog_full = \ ; + assign axi_r_rd_data_count[10] = \ ; + assign axi_r_rd_data_count[9] = \ ; + assign axi_r_rd_data_count[8] = \ ; + assign axi_r_rd_data_count[7] = \ ; + assign axi_r_rd_data_count[6] = \ ; + assign axi_r_rd_data_count[5] = \ ; + assign axi_r_rd_data_count[4] = \ ; + assign axi_r_rd_data_count[3] = \ ; + assign axi_r_rd_data_count[2] = \ ; + assign axi_r_rd_data_count[1] = \ ; + assign axi_r_rd_data_count[0] = \ ; + assign axi_r_sbiterr = \ ; + assign axi_r_underflow = \ ; + assign axi_r_wr_data_count[10] = \ ; + assign axi_r_wr_data_count[9] = \ ; + assign axi_r_wr_data_count[8] = \ ; + assign axi_r_wr_data_count[7] = \ ; + assign axi_r_wr_data_count[6] = \ ; + assign axi_r_wr_data_count[5] = \ ; + assign axi_r_wr_data_count[4] = \ ; + assign axi_r_wr_data_count[3] = \ ; + assign axi_r_wr_data_count[2] = \ ; + assign axi_r_wr_data_count[1] = \ ; + assign axi_r_wr_data_count[0] = \ ; + assign axi_w_data_count[10] = \ ; + assign axi_w_data_count[9] = \ ; + assign axi_w_data_count[8] = \ ; + assign axi_w_data_count[7] = \ ; + assign axi_w_data_count[6] = \ ; + assign axi_w_data_count[5] = \ ; + assign axi_w_data_count[4] = \ ; + assign axi_w_data_count[3] = \ ; + assign axi_w_data_count[2] = \ ; + assign axi_w_data_count[1] = \ ; + assign axi_w_data_count[0] = \ ; + assign axi_w_dbiterr = \ ; + assign axi_w_overflow = \ ; + assign axi_w_prog_empty = \ ; + assign axi_w_prog_full = \ ; + assign axi_w_rd_data_count[10] = \ ; + assign axi_w_rd_data_count[9] = \ ; + assign axi_w_rd_data_count[8] = \ ; + assign axi_w_rd_data_count[7] = \ ; + assign axi_w_rd_data_count[6] = \ ; + assign axi_w_rd_data_count[5] = \ ; + assign axi_w_rd_data_count[4] = \ ; + assign axi_w_rd_data_count[3] = \ ; + assign axi_w_rd_data_count[2] = \ ; + assign axi_w_rd_data_count[1] = \ ; + assign axi_w_rd_data_count[0] = \ ; + assign axi_w_sbiterr = \ ; + assign axi_w_underflow = \ ; + assign axi_w_wr_data_count[10] = \ ; + assign axi_w_wr_data_count[9] = \ ; + assign axi_w_wr_data_count[8] = \ ; + assign axi_w_wr_data_count[7] = \ ; + assign axi_w_wr_data_count[6] = \ ; + assign axi_w_wr_data_count[5] = \ ; + assign axi_w_wr_data_count[4] = \ ; + assign axi_w_wr_data_count[3] = \ ; + assign axi_w_wr_data_count[2] = \ ; + assign axi_w_wr_data_count[1] = \ ; + assign axi_w_wr_data_count[0] = \ ; + assign axis_data_count[10] = \ ; + assign axis_data_count[9] = \ ; + assign axis_data_count[8] = \ ; + assign axis_data_count[7] = \ ; + assign axis_data_count[6] = \ ; + assign axis_data_count[5] = \ ; + assign axis_data_count[4] = \ ; + assign axis_data_count[3] = \ ; + assign axis_data_count[2] = \ ; + assign axis_data_count[1] = \ ; + assign axis_data_count[0] = \ ; + assign axis_dbiterr = \ ; + assign axis_overflow = \ ; + assign axis_prog_empty = \ ; + assign axis_prog_full = \ ; + assign axis_rd_data_count[10] = \ ; + assign axis_rd_data_count[9] = \ ; + assign axis_rd_data_count[8] = \ ; + assign axis_rd_data_count[7] = \ ; + assign axis_rd_data_count[6] = \ ; + assign axis_rd_data_count[5] = \ ; + assign axis_rd_data_count[4] = \ ; + assign axis_rd_data_count[3] = \ ; + assign axis_rd_data_count[2] = \ ; + assign axis_rd_data_count[1] = \ ; + assign axis_rd_data_count[0] = \ ; + assign axis_sbiterr = \ ; + assign axis_underflow = \ ; + assign axis_wr_data_count[10] = \ ; + assign axis_wr_data_count[9] = \ ; + assign axis_wr_data_count[8] = \ ; + assign axis_wr_data_count[7] = \ ; + assign axis_wr_data_count[6] = \ ; + assign axis_wr_data_count[5] = \ ; + assign axis_wr_data_count[4] = \ ; + assign axis_wr_data_count[3] = \ ; + assign axis_wr_data_count[2] = \ ; + assign axis_wr_data_count[1] = \ ; + assign axis_wr_data_count[0] = \ ; + assign data_count[12] = \ ; + assign data_count[11] = \ ; + assign data_count[10] = \ ; + assign data_count[9] = \ ; + assign data_count[8] = \ ; + assign data_count[7] = \ ; + assign data_count[6] = \ ; + assign data_count[5] = \ ; + assign data_count[4] = \ ; + assign data_count[3] = \ ; + assign data_count[2] = \ ; + assign data_count[1] = \ ; + assign data_count[0] = \ ; + assign dbiterr = \ ; + assign m_axi_araddr[31] = \ ; + assign m_axi_araddr[30] = \ ; + assign m_axi_araddr[29] = \ ; + assign m_axi_araddr[28] = \ ; + assign m_axi_araddr[27] = \ ; + assign m_axi_araddr[26] = \ ; + assign m_axi_araddr[25] = \ ; + assign m_axi_araddr[24] = \ ; + assign m_axi_araddr[23] = \ ; + assign m_axi_araddr[22] = \ ; + assign m_axi_araddr[21] = \ ; + assign m_axi_araddr[20] = \ ; + assign m_axi_araddr[19] = \ ; + assign m_axi_araddr[18] = \ ; + assign m_axi_araddr[17] = \ ; + assign m_axi_araddr[16] = \ ; + assign m_axi_araddr[15] = \ ; + assign m_axi_araddr[14] = \ ; + assign m_axi_araddr[13] = \ ; + assign m_axi_araddr[12] = \ ; + assign m_axi_araddr[11] = \ ; + assign m_axi_araddr[10] = \ ; + assign m_axi_araddr[9] = \ ; + assign m_axi_araddr[8] = \ ; + assign m_axi_araddr[7] = \ ; + assign m_axi_araddr[6] = \ ; + assign m_axi_araddr[5] = \ ; + assign m_axi_araddr[4] = \ ; + assign m_axi_araddr[3] = \ ; + assign m_axi_araddr[2] = \ ; + assign m_axi_araddr[1] = \ ; + assign m_axi_araddr[0] = \ ; + assign m_axi_arburst[1] = \ ; + assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[3] = \ ; + assign m_axi_arcache[2] = \ ; + assign m_axi_arcache[1] = \ ; + assign m_axi_arcache[0] = \ ; + assign m_axi_arid[0] = \ ; + assign m_axi_arlen[7] = \ ; + assign m_axi_arlen[6] = \ ; + assign m_axi_arlen[5] = \ ; + assign m_axi_arlen[4] = \ ; + assign m_axi_arlen[3] = \ ; + assign m_axi_arlen[2] = \ ; + assign m_axi_arlen[1] = \ ; + assign m_axi_arlen[0] = \ ; + assign m_axi_arlock[0] = \ ; + assign m_axi_arprot[2] = \ ; + assign m_axi_arprot[1] = \ ; + assign m_axi_arprot[0] = \ ; + assign m_axi_arqos[3] = \ ; + assign m_axi_arqos[2] = \ ; + assign m_axi_arqos[1] = \ ; + assign m_axi_arqos[0] = \ ; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[2] = \ ; + assign m_axi_arsize[1] = \ ; + assign m_axi_arsize[0] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_arvalid = \ ; + assign m_axi_awaddr[31] = \ ; + assign m_axi_awaddr[30] = \ ; + assign m_axi_awaddr[29] = \ ; + assign m_axi_awaddr[28] = \ ; + assign m_axi_awaddr[27] = \ ; + assign m_axi_awaddr[26] = \ ; + assign m_axi_awaddr[25] = \ ; + assign m_axi_awaddr[24] = \ ; + assign m_axi_awaddr[23] = \ ; + assign m_axi_awaddr[22] = \ ; + assign m_axi_awaddr[21] = \ ; + assign m_axi_awaddr[20] = \ ; + assign m_axi_awaddr[19] = \ ; + assign m_axi_awaddr[18] = \ ; + assign m_axi_awaddr[17] = \ ; + assign m_axi_awaddr[16] = \ ; + assign m_axi_awaddr[15] = \ ; + assign m_axi_awaddr[14] = \ ; + assign m_axi_awaddr[13] = \ ; + assign m_axi_awaddr[12] = \ ; + assign m_axi_awaddr[11] = \ ; + assign m_axi_awaddr[10] = \ ; + assign m_axi_awaddr[9] = \ ; + assign m_axi_awaddr[8] = \ ; + assign m_axi_awaddr[7] = \ ; + assign m_axi_awaddr[6] = \ ; + assign m_axi_awaddr[5] = \ ; + assign m_axi_awaddr[4] = \ ; + assign m_axi_awaddr[3] = \ ; + assign m_axi_awaddr[2] = \ ; + assign m_axi_awaddr[1] = \ ; + assign m_axi_awaddr[0] = \ ; + assign m_axi_awburst[1] = \ ; + assign m_axi_awburst[0] = \ ; + assign m_axi_awcache[3] = \ ; + assign m_axi_awcache[2] = \ ; + assign m_axi_awcache[1] = \ ; + assign m_axi_awcache[0] = \ ; + assign m_axi_awid[0] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; + assign m_axi_awlen[3] = \ ; + assign m_axi_awlen[2] = \ ; + assign m_axi_awlen[1] = \ ; + assign m_axi_awlen[0] = \ ; + assign m_axi_awlock[0] = \ ; + assign m_axi_awprot[2] = \ ; + assign m_axi_awprot[1] = \ ; + assign m_axi_awprot[0] = \ ; + assign m_axi_awqos[3] = \ ; + assign m_axi_awqos[2] = \ ; + assign m_axi_awqos[1] = \ ; + assign m_axi_awqos[0] = \ ; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awsize[2] = \ ; + assign m_axi_awsize[1] = \ ; + assign m_axi_awsize[0] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_awvalid = \ ; + assign m_axi_bready = \ ; + assign m_axi_rready = \ ; + assign m_axi_wdata[63] = \ ; + assign m_axi_wdata[62] = \ ; + assign m_axi_wdata[61] = \ ; + assign m_axi_wdata[60] = \ ; + assign m_axi_wdata[59] = \ ; + assign m_axi_wdata[58] = \ ; + assign m_axi_wdata[57] = \ ; + assign m_axi_wdata[56] = \ ; + assign m_axi_wdata[55] = \ ; + assign m_axi_wdata[54] = \ ; + assign m_axi_wdata[53] = \ ; + assign m_axi_wdata[52] = \ ; + assign m_axi_wdata[51] = \ ; + assign m_axi_wdata[50] = \ ; + assign m_axi_wdata[49] = \ ; + assign m_axi_wdata[48] = \ ; + assign m_axi_wdata[47] = \ ; + assign m_axi_wdata[46] = \ ; + assign m_axi_wdata[45] = \ ; + assign m_axi_wdata[44] = \ ; + assign m_axi_wdata[43] = \ ; + assign m_axi_wdata[42] = \ ; + assign m_axi_wdata[41] = \ ; + assign m_axi_wdata[40] = \ ; + assign m_axi_wdata[39] = \ ; + assign m_axi_wdata[38] = \ ; + assign m_axi_wdata[37] = \ ; + assign m_axi_wdata[36] = \ ; + assign m_axi_wdata[35] = \ ; + assign m_axi_wdata[34] = \ ; + assign m_axi_wdata[33] = \ ; + assign m_axi_wdata[32] = \ ; + assign m_axi_wdata[31] = \ ; + assign m_axi_wdata[30] = \ ; + assign m_axi_wdata[29] = \ ; + assign m_axi_wdata[28] = \ ; + assign m_axi_wdata[27] = \ ; + assign m_axi_wdata[26] = \ ; + assign m_axi_wdata[25] = \ ; + assign m_axi_wdata[24] = \ ; + assign m_axi_wdata[23] = \ ; + assign m_axi_wdata[22] = \ ; + assign m_axi_wdata[21] = \ ; + assign m_axi_wdata[20] = \ ; + assign m_axi_wdata[19] = \ ; + assign m_axi_wdata[18] = \ ; + assign m_axi_wdata[17] = \ ; + assign m_axi_wdata[16] = \ ; + assign m_axi_wdata[15] = \ ; + assign m_axi_wdata[14] = \ ; + assign m_axi_wdata[13] = \ ; + assign m_axi_wdata[12] = \ ; + assign m_axi_wdata[11] = \ ; + assign m_axi_wdata[10] = \ ; + assign m_axi_wdata[9] = \ ; + assign m_axi_wdata[8] = \ ; + assign m_axi_wdata[7] = \ ; + assign m_axi_wdata[6] = \ ; + assign m_axi_wdata[5] = \ ; + assign m_axi_wdata[4] = \ ; + assign m_axi_wdata[3] = \ ; + assign m_axi_wdata[2] = \ ; + assign m_axi_wdata[1] = \ ; + assign m_axi_wdata[0] = \ ; + assign m_axi_wid[0] = \ ; + assign m_axi_wlast = \ ; + assign m_axi_wstrb[7] = \ ; + assign m_axi_wstrb[6] = \ ; + assign m_axi_wstrb[5] = \ ; + assign m_axi_wstrb[4] = \ ; + assign m_axi_wstrb[3] = \ ; + assign m_axi_wstrb[2] = \ ; + assign m_axi_wstrb[1] = \ ; + assign m_axi_wstrb[0] = \ ; + assign m_axi_wuser[0] = \ ; + assign m_axi_wvalid = \ ; + assign m_axis_tdata[7] = \ ; + assign m_axis_tdata[6] = \ ; + assign m_axis_tdata[5] = \ ; + assign m_axis_tdata[4] = \ ; + assign m_axis_tdata[3] = \ ; + assign m_axis_tdata[2] = \ ; + assign m_axis_tdata[1] = \ ; + assign m_axis_tdata[0] = \ ; + assign m_axis_tdest[0] = \ ; + assign m_axis_tid[0] = \ ; + assign m_axis_tkeep[0] = \ ; + assign m_axis_tlast = \ ; + assign m_axis_tstrb[0] = \ ; + assign m_axis_tuser[3] = \ ; + assign m_axis_tuser[2] = \ ; + assign m_axis_tuser[1] = \ ; + assign m_axis_tuser[0] = \ ; + assign m_axis_tvalid = \ ; + assign overflow = \ ; + assign prog_empty = \ ; + assign prog_full = \ ; + assign rd_data_count[12] = \ ; + assign rd_data_count[11] = \ ; + assign rd_data_count[10] = \ ; + assign rd_data_count[9] = \ ; + assign rd_data_count[8] = \ ; + assign rd_data_count[7] = \ ; + assign rd_data_count[6] = \ ; + assign rd_data_count[5] = \ ; + assign rd_data_count[4] = \ ; + assign rd_data_count[3] = \ ; + assign rd_data_count[2] = \ ; + assign rd_data_count[1] = \ ; + assign rd_data_count[0] = \ ; + assign rd_rst_busy = \ ; + assign s_axi_arready = \ ; + assign s_axi_awready = \ ; + assign s_axi_bid[0] = \ ; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_buser[0] = \ ; + assign s_axi_bvalid = \ ; + assign s_axi_rdata[63] = \ ; + assign s_axi_rdata[62] = \ ; + assign s_axi_rdata[61] = \ ; + assign s_axi_rdata[60] = \ ; + assign s_axi_rdata[59] = \ ; + assign s_axi_rdata[58] = \ ; + assign s_axi_rdata[57] = \ ; + assign s_axi_rdata[56] = \ ; + assign s_axi_rdata[55] = \ ; + assign s_axi_rdata[54] = \ ; + assign s_axi_rdata[53] = \ ; + assign s_axi_rdata[52] = \ ; + assign s_axi_rdata[51] = \ ; + assign s_axi_rdata[50] = \ ; + assign s_axi_rdata[49] = \ ; + assign s_axi_rdata[48] = \ ; + assign s_axi_rdata[47] = \ ; + assign s_axi_rdata[46] = \ ; + assign s_axi_rdata[45] = \ ; + assign s_axi_rdata[44] = \ ; + assign s_axi_rdata[43] = \ ; + assign s_axi_rdata[42] = \ ; + assign s_axi_rdata[41] = \ ; + assign s_axi_rdata[40] = \ ; + assign s_axi_rdata[39] = \ ; + assign s_axi_rdata[38] = \ ; + assign s_axi_rdata[37] = \ ; + assign s_axi_rdata[36] = \ ; + assign s_axi_rdata[35] = \ ; + assign s_axi_rdata[34] = \ ; + assign s_axi_rdata[33] = \ ; + assign s_axi_rdata[32] = \ ; + assign s_axi_rdata[31] = \ ; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1] = \ ; + assign s_axi_rdata[0] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + assign s_axi_ruser[0] = \ ; + assign s_axi_rvalid = \ ; + assign s_axi_wready = \ ; + assign s_axis_tready = \ ; + assign sbiterr = \ ; + assign underflow = \ ; + assign valid = \ ; + assign wr_ack = \ ; + assign wr_data_count[12] = \ ; + assign wr_data_count[11] = \ ; + assign wr_data_count[10] = \ ; + assign wr_data_count[9] = \ ; + assign wr_data_count[8] = \ ; + assign wr_data_count[7] = \ ; + assign wr_data_count[6] = \ ; + assign wr_data_count[5] = \ ; + assign wr_data_count[4] = \ ; + assign wr_data_count[3] = \ ; + assign wr_data_count[2] = \ ; + assign wr_data_count[1] = \ ; + assign wr_data_count[0] = \ ; + assign wr_rst_busy = \ ; + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen + (.din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth + (dout, + empty, + full, + wr_en, + rd_en, + wr_clk, + rd_clk, + din); + output [23:0]dout; + output empty; + output full; + input wr_en; + input rd_en; + input wr_clk; + input rd_clk; + input [23:0]din; + + wire [23:0]din; + wire [23:0]dout; + wire empty; + wire full; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf + (.din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory + (dout, + sel_pipe, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); + output [23:0]dout; + output sel_pipe; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; + + wire [12:0]Q; + wire [0:0]WEA; + wire [23:0]din; + wire [23:0]dout; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; + wire rd_clk; + wire sel_pipe; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (sel_pipe), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr + (D, + ram_empty_fb_i_reg, + Q, + ram_empty_fb_i_reg_0, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + enb_array, + I6, + E, + rd_clk, + WR_PNTR_RD, + rd_en, + out, + sel_pipe); + output [11:0]D; + output ram_empty_fb_i_reg; + output [12:0]Q; + output ram_empty_fb_i_reg_0; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + output [0:0]enb_array; + output [11:0]I6; + input [0:0]E; + input rd_clk; + input [0:0]WR_PNTR_RD; + input rd_en; + input out; + input sel_pipe; + + wire [11:0]D; + wire [0:0]E; + wire [11:0]I6; + wire [12:0]Q; + wire [0:0]WR_PNTR_RD; + wire [0:0]enb_array; + wire \gc0.count[0]_i_2_n_0 ; + wire \gc0.count[0]_i_3_n_0 ; + wire \gc0.count[0]_i_4_n_0 ; + wire \gc0.count[0]_i_5_n_0 ; + wire \gc0.count[12]_i_2_n_0 ; + wire \gc0.count[4]_i_2_n_0 ; + wire \gc0.count[4]_i_3_n_0 ; + wire \gc0.count[4]_i_4_n_0 ; + wire \gc0.count[4]_i_5_n_0 ; + wire \gc0.count[8]_i_2_n_0 ; + wire \gc0.count[8]_i_3_n_0 ; + wire \gc0.count[8]_i_4_n_0 ; + wire \gc0.count[8]_i_5_n_0 ; + wire \gc0.count_reg[0]_i_1_n_0 ; + wire \gc0.count_reg[0]_i_1_n_1 ; + wire \gc0.count_reg[0]_i_1_n_2 ; + wire \gc0.count_reg[0]_i_1_n_3 ; + wire \gc0.count_reg[0]_i_1_n_4 ; + wire \gc0.count_reg[0]_i_1_n_5 ; + wire \gc0.count_reg[0]_i_1_n_6 ; + wire \gc0.count_reg[0]_i_1_n_7 ; + wire \gc0.count_reg[12]_i_1_n_7 ; + wire \gc0.count_reg[4]_i_1_n_0 ; + wire \gc0.count_reg[4]_i_1_n_1 ; + wire \gc0.count_reg[4]_i_1_n_2 ; + wire \gc0.count_reg[4]_i_1_n_3 ; + wire \gc0.count_reg[4]_i_1_n_4 ; + wire \gc0.count_reg[4]_i_1_n_5 ; + wire \gc0.count_reg[4]_i_1_n_6 ; + wire \gc0.count_reg[4]_i_1_n_7 ; + wire \gc0.count_reg[8]_i_1_n_0 ; + wire \gc0.count_reg[8]_i_1_n_1 ; + wire \gc0.count_reg[8]_i_1_n_2 ; + wire \gc0.count_reg[8]_i_1_n_3 ; + wire \gc0.count_reg[8]_i_1_n_4 ; + wire \gc0.count_reg[8]_i_1_n_5 ; + wire \gc0.count_reg[8]_i_1_n_6 ; + wire \gc0.count_reg[8]_i_1_n_7 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire out; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire rd_clk; + wire rd_en; + wire [12:12]rd_pntr_plus1; + wire sel_pipe; + wire [3:0]\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED ; + + LUT3 #( + .INIT(8'h20)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 + (.I0(Q[12]), + .I1(out), + .I2(rd_en), + .O(enb_array)); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gc0.count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[12]_i_2 + (.I0(rd_pntr_plus1), + .O(\gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gc0.count[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[0] + (.C(rd_clk), + .CE(E), + .D(D[0]), + .Q(Q[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[10] + (.C(rd_clk), + .CE(E), + .D(D[10]), + .Q(Q[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[11] + (.C(rd_clk), + .CE(E), + .D(D[11]), + .Q(Q[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[12] + (.C(rd_clk), + .CE(E), + .D(rd_pntr_plus1), + .Q(Q[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[1] + (.C(rd_clk), + .CE(E), + .D(D[1]), + .Q(Q[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[2] + (.C(rd_clk), + .CE(E), + .D(D[2]), + .Q(Q[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[3] + (.C(rd_clk), + .CE(E), + .D(D[3]), + .Q(Q[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[4] + (.C(rd_clk), + .CE(E), + .D(D[4]), + .Q(Q[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[5] + (.C(rd_clk), + .CE(E), + .D(D[5]), + .Q(Q[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[6] + (.C(rd_clk), + .CE(E), + .D(D[6]), + .Q(Q[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[7] + (.C(rd_clk), + .CE(E), + .D(D[7]), + .Q(Q[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[8] + (.C(rd_clk), + .CE(E), + .D(D[8]), + .Q(Q[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[9] + (.C(rd_clk), + .CE(E), + .D(D[9]), + .Q(Q[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \gc0.count_reg[0] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_7 ), + .Q(D[0]), + .R(1'b0)); + CARRY4 \gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gc0.count_reg[0]_i_1_n_0 ,\gc0.count_reg[0]_i_1_n_1 ,\gc0.count_reg[0]_i_1_n_2 ,\gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gc0.count_reg[0]_i_1_n_4 ,\gc0.count_reg[0]_i_1_n_5 ,\gc0.count_reg[0]_i_1_n_6 ,\gc0.count_reg[0]_i_1_n_7 }), + .S({\gc0.count[0]_i_2_n_0 ,\gc0.count[0]_i_3_n_0 ,\gc0.count[0]_i_4_n_0 ,\gc0.count[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[10] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[11] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[12] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[12]_i_1_n_7 ), + .Q(rd_pntr_plus1), + .R(1'b0)); + CARRY4 \gc0.count_reg[12]_i_1 + (.CI(\gc0.count_reg[8]_i_1_n_0 ), + .CO(\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED [3:1],\gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,\gc0.count[12]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[1] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_6 ), + .Q(D[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[2] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[3] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[4] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4]), + .R(1'b0)); + CARRY4 \gc0.count_reg[4]_i_1 + (.CI(\gc0.count_reg[0]_i_1_n_0 ), + .CO({\gc0.count_reg[4]_i_1_n_0 ,\gc0.count_reg[4]_i_1_n_1 ,\gc0.count_reg[4]_i_1_n_2 ,\gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[4]_i_1_n_4 ,\gc0.count_reg[4]_i_1_n_5 ,\gc0.count_reg[4]_i_1_n_6 ,\gc0.count_reg[4]_i_1_n_7 }), + .S({\gc0.count[4]_i_2_n_0 ,\gc0.count[4]_i_3_n_0 ,\gc0.count[4]_i_4_n_0 ,\gc0.count[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[5] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[6] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[7] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[8] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8]), + .R(1'b0)); + CARRY4 \gc0.count_reg[8]_i_1 + (.CI(\gc0.count_reg[4]_i_1_n_0 ), + .CO({\gc0.count_reg[8]_i_1_n_0 ,\gc0.count_reg[8]_i_1_n_1 ,\gc0.count_reg[8]_i_1_n_2 ,\gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[8]_i_1_n_4 ,\gc0.count_reg[8]_i_1_n_5 ,\gc0.count_reg[8]_i_1_n_6 ,\gc0.count_reg[8]_i_1_n_7 }), + .S({\gc0.count[8]_i_2_n_0 ,\gc0.count[8]_i_3_n_0 ,\gc0.count[8]_i_4_n_0 ,\gc0.count[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[9] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9]), + .R(1'b0)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1__1 + (.I0(Q[12]), + .I1(WR_PNTR_RD), + .O(ram_empty_fb_i_reg)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1__2 + (.I0(rd_pntr_plus1), + .I1(WR_PNTR_RD), + .O(ram_empty_fb_i_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[0]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(I6[0])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[10]_i_1 + (.I0(Q[10]), + .I1(Q[11]), + .O(I6[10])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[11]_i_1 + (.I0(Q[11]), + .I1(Q[12]), + .O(I6[11])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[1]_i_1 + (.I0(Q[1]), + .I1(Q[2]), + .O(I6[1])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[2]_i_1 + (.I0(Q[2]), + .I1(Q[3]), + .O(I6[2])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[3]_i_1 + (.I0(Q[3]), + .I1(Q[4]), + .O(I6[3])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[4]_i_1 + (.I0(Q[4]), + .I1(Q[5]), + .O(I6[4])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[5]_i_1 + (.I0(Q[5]), + .I1(Q[6]), + .O(I6[5])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[6]_i_1 + (.I0(Q[6]), + .I1(Q[7]), + .O(I6[6])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[7]_i_1 + (.I0(Q[7]), + .I1(Q[8]), + .O(I6[7])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[8]_i_1 + (.I0(Q[8]), + .I1(Q[9]), + .O(I6[8])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[9]_i_1 + (.I0(Q[9]), + .I1(Q[10]), + .O(I6[9])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hFB08)) + \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1 + (.I0(Q[12]), + .I1(rd_en), + .I2(out), + .I3(sel_pipe), + .O(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] )); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic + (empty, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + Q, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + I6, + enb_array, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + rd_clk, + rd_en, + WR_PNTR_RD, + sel_pipe); + output empty; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [12:0]Q; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + output [11:0]I6; + output [0:0]enb_array; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input rd_clk; + input rd_en; + input [12:0]WR_PNTR_RD; + input sel_pipe; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [11:0]I6; + wire [12:0]Q; + wire [12:0]WR_PNTR_RD; + wire empty; + wire [0:0]enb_array; + wire \gras.rsts_n_3 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire p_2_out; + wire rd_clk; + wire rd_en; + wire [11:0]rd_pntr_plus1; + wire rpntr_n_12; + wire rpntr_n_26; + wire sel_pipe; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as \gras.rsts + (.D(rd_pntr_plus1), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .E(\gras.rsts_n_3 ), + .Q(Q), + .WR_PNTR_RD(WR_PNTR_RD[11:0]), + .empty(empty), + .\gc0.count_d1_reg[12] (rpntr_n_12), + .\gc0.count_reg[12] (rpntr_n_26), + .out(p_2_out), + .rd_clk(rd_clk), + .rd_en(rd_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr + (.D(rd_pntr_plus1), + .E(\gras.rsts_n_3 ), + .I6(I6), + .Q(Q), + .WR_PNTR_RD(WR_PNTR_RD[12]), + .enb_array(enb_array), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .out(p_2_out), + .ram_empty_fb_i_reg(rpntr_n_12), + .ram_empty_fb_i_reg_0(rpntr_n_26), + .rd_clk(rd_clk), + .rd_en(rd_en), + .sel_pipe(sel_pipe)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as + (empty, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + E, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \gc0.count_d1_reg[12] , + \gc0.count_reg[12] , + rd_clk, + rd_en, + Q, + WR_PNTR_RD, + D); + output empty; + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [0:0]E; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input \gc0.count_d1_reg[12] ; + input \gc0.count_reg[12] ; + input rd_clk; + input rd_en; + input [12:0]Q; + input [11:0]WR_PNTR_RD; + input [11:0]D; + + wire [11:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [0:0]E; + wire [12:0]Q; + wire [11:0]WR_PNTR_RD; + wire comp0; + wire comp1; + wire \gc0.count_d1_reg[12] ; + wire \gc0.count_reg[12] ; + (* DONT_TOUCH *) wire ram_empty_fb_i; + (* DONT_TOUCH *) wire ram_empty_i; + wire ram_empty_i_reg0_n_0; + wire rd_clk; + wire rd_en; + + assign empty = ram_empty_i; + assign out = ram_empty_fb_i; + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0 + (.I0(rd_en), + .I1(ram_empty_fb_i), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); + LUT3 #( + .INIT(8'h04)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1 + (.I0(ram_empty_fb_i), + .I1(rd_en), + .I2(Q[12]), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 c0 + (.Q(Q[11:0]), + .WR_PNTR_RD(WR_PNTR_RD), + .comp0(comp0), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 c1 + (.D(D), + .WR_PNTR_RD(WR_PNTR_RD), + .comp1(comp1), + .\gc0.count_reg[12] (\gc0.count_reg[12] )); + LUT2 #( + .INIT(4'h2)) + \gc0.count_d1[12]_i_1 + (.I0(rd_en), + .I1(ram_empty_fb_i), + .O(E)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + ram_empty_fb_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(ram_empty_i_reg0_n_0), + .Q(ram_empty_fb_i), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + ram_empty_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(ram_empty_i_reg0_n_0), + .Q(ram_empty_i), + .R(1'b0)); + LUT4 #( + .INIT(16'hAEAA)) + ram_empty_i_reg0 + (.I0(comp0), + .I1(rd_en), + .I2(ram_empty_fb_i), + .I3(comp1), + .O(ram_empty_i_reg0_n_0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff + (out, + in0, + rd_clk); + output [12:0]out; + input [12:0]in0; + input rd_clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire [12:0]in0; + wire rd_clk; + + assign out[12:0] = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(in0[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(in0[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(in0[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(in0[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(in0[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(in0[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(in0[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(in0[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(in0[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(in0[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(in0[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(in0[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(in0[9]), + .Q(Q_reg[9]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_3 + (out, + Q, + wr_clk); + output [12:0]out; + input [12:0]Q; + input wr_clk; + + wire [12:0]Q; + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire wr_clk; + + assign out[12:0] = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(Q[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(Q[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(Q[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(Q[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(Q[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(Q[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(Q[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(Q[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(Q[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(Q[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(Q[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(Q[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(Q[9]), + .Q(Q_reg[9]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_4 + (\gnxpm_cdc.wr_pntr_bin_reg[12] , + D, + out, + rd_clk); + output [0:0]\gnxpm_cdc.wr_pntr_bin_reg[12] ; + output [11:0]D; + input [12:0]out; + input rd_clk; + + wire [11:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ; + wire [12:0]out; + wire rd_clk; + + assign \gnxpm_cdc.wr_pntr_bin_reg[12] [0] = Q_reg[12]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(out[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(out[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(out[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(out[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(out[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(out[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(out[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(out[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(out[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(out[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(out[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(out[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(out[9]), + .Q(Q_reg[9]), + .R(1'b0)); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[0]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[1]), + .I2(Q_reg[0]), + .I3(Q_reg[3]), + .I4(Q_reg[2]), + .I5(D[7]), + .O(D[0])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[10]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[10]), + .I2(Q_reg[12]), + .O(D[10])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[11]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[12]), + .O(D[11])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[2]), + .I2(Q_reg[1]), + .I3(Q_reg[3]), + .I4(D[7]), + .O(D[1])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[1]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[4]), + .I2(Q_reg[6]), + .O(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[2]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), + .I1(Q_reg[7]), + .I2(Q_reg[3]), + .I3(Q_reg[2]), + .I4(Q_reg[4]), + .I5(D[8]), + .O(D[2])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[2]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[6]), + .O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[3]_i_1 + (.I0(Q_reg[6]), + .I1(Q_reg[7]), + .I2(Q_reg[4]), + .I3(Q_reg[3]), + .I4(Q_reg[5]), + .I5(D[8]), + .O(D[3])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[4]_i_1 + (.I0(Q_reg[7]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[4]), + .I4(Q_reg[6]), + .I5(D[9]), + .O(D[4])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[5]_i_1 + (.I0(Q_reg[7]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[6]), + .I4(D[9]), + .O(D[5])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[6]_i_1 + (.I0(Q_reg[8]), + .I1(Q_reg[9]), + .I2(Q_reg[6]), + .I3(Q_reg[7]), + .I4(D[10]), + .O(D[6])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[7]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[7]), + .I2(Q_reg[8]), + .I3(Q_reg[12]), + .I4(Q_reg[10]), + .I5(Q_reg[11]), + .O(D[7])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[8]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[12]), + .I4(Q_reg[11]), + .O(D[8])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.wr_pntr_bin[9]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[12]), + .I3(Q_reg[11]), + .O(D[9])); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_5 + (\gnxpm_cdc.rd_pntr_bin_reg[12] , + D, + out, + wr_clk); + output [0:0]\gnxpm_cdc.rd_pntr_bin_reg[12] ; + output [11:0]D; + input [12:0]out; + input wr_clk; + + wire [11:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ; + wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ; + wire [12:0]out; + wire wr_clk; + + assign \gnxpm_cdc.rd_pntr_bin_reg[12] [0] = Q_reg[12]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(out[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(out[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(out[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(out[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(out[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(out[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(out[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(out[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(out[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(out[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(out[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(out[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(out[9]), + .Q(Q_reg[9]), + .R(1'b0)); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[0]_i_1 + (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[1]), + .I2(Q_reg[0]), + .I3(Q_reg[3]), + .I4(Q_reg[2]), + .I5(D[7]), + .O(D[0])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.rd_pntr_bin[10]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[10]), + .I2(Q_reg[12]), + .O(D[10])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[11]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[12]), + .O(D[11])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[2]), + .I2(Q_reg[1]), + .I3(Q_reg[3]), + .I4(D[7]), + .O(D[1])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.rd_pntr_bin[1]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[4]), + .I2(Q_reg[6]), + .O(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[2]_i_1 + (.I0(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ), + .I1(Q_reg[7]), + .I2(Q_reg[3]), + .I3(Q_reg[2]), + .I4(Q_reg[4]), + .I5(D[8]), + .O(D[2])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[2]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[6]), + .O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[3]_i_1 + (.I0(Q_reg[6]), + .I1(Q_reg[7]), + .I2(Q_reg[4]), + .I3(Q_reg[3]), + .I4(Q_reg[5]), + .I5(D[8]), + .O(D[3])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[4]_i_1 + (.I0(Q_reg[7]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[4]), + .I4(Q_reg[6]), + .I5(D[9]), + .O(D[4])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[5]_i_1 + (.I0(Q_reg[7]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[6]), + .I4(D[9]), + .O(D[5])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[6]_i_1 + (.I0(Q_reg[8]), + .I1(Q_reg[9]), + .I2(Q_reg[6]), + .I3(Q_reg[7]), + .I4(D[10]), + .O(D[6])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[7]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[7]), + .I2(Q_reg[8]), + .I3(Q_reg[12]), + .I4(Q_reg[10]), + .I5(Q_reg[11]), + .O(D[7])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[8]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[12]), + .I4(Q_reg[11]), + .O(D[8])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[9]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[12]), + .I3(Q_reg[11]), + .O(D[9])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr + (D, + ena_array, + Q, + \gic0.gc0.count_d2_reg[12]_0 , + bin2gray, + ram_full_fb_i_reg, + wr_clk, + out, + wr_en); + output [12:0]D; + output [0:0]ena_array; + output [12:0]Q; + output [12:0]\gic0.gc0.count_d2_reg[12]_0 ; + output [11:0]bin2gray; + input ram_full_fb_i_reg; + input wr_clk; + input out; + input wr_en; + + wire [12:0]D; + wire [12:0]Q; + wire [11:0]bin2gray; + wire [0:0]ena_array; + wire \gic0.gc0.count[0]_i_2_n_0 ; + wire \gic0.gc0.count[0]_i_3_n_0 ; + wire \gic0.gc0.count[0]_i_4_n_0 ; + wire \gic0.gc0.count[0]_i_5_n_0 ; + wire \gic0.gc0.count[12]_i_2_n_0 ; + wire \gic0.gc0.count[4]_i_2_n_0 ; + wire \gic0.gc0.count[4]_i_3_n_0 ; + wire \gic0.gc0.count[4]_i_4_n_0 ; + wire \gic0.gc0.count[4]_i_5_n_0 ; + wire \gic0.gc0.count[8]_i_2_n_0 ; + wire \gic0.gc0.count[8]_i_3_n_0 ; + wire \gic0.gc0.count[8]_i_4_n_0 ; + wire \gic0.gc0.count[8]_i_5_n_0 ; + wire [12:0]\gic0.gc0.count_d2_reg[12]_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_1 ; + wire \gic0.gc0.count_reg[0]_i_1_n_2 ; + wire \gic0.gc0.count_reg[0]_i_1_n_3 ; + wire \gic0.gc0.count_reg[0]_i_1_n_4 ; + wire \gic0.gc0.count_reg[0]_i_1_n_5 ; + wire \gic0.gc0.count_reg[0]_i_1_n_6 ; + wire \gic0.gc0.count_reg[0]_i_1_n_7 ; + wire \gic0.gc0.count_reg[12]_i_1_n_7 ; + wire \gic0.gc0.count_reg[4]_i_1_n_0 ; + wire \gic0.gc0.count_reg[4]_i_1_n_1 ; + wire \gic0.gc0.count_reg[4]_i_1_n_2 ; + wire \gic0.gc0.count_reg[4]_i_1_n_3 ; + wire \gic0.gc0.count_reg[4]_i_1_n_4 ; + wire \gic0.gc0.count_reg[4]_i_1_n_5 ; + wire \gic0.gc0.count_reg[4]_i_1_n_6 ; + wire \gic0.gc0.count_reg[4]_i_1_n_7 ; + wire \gic0.gc0.count_reg[8]_i_1_n_0 ; + wire \gic0.gc0.count_reg[8]_i_1_n_1 ; + wire \gic0.gc0.count_reg[8]_i_1_n_2 ; + wire \gic0.gc0.count_reg[8]_i_1_n_3 ; + wire \gic0.gc0.count_reg[8]_i_1_n_4 ; + wire \gic0.gc0.count_reg[8]_i_1_n_5 ; + wire \gic0.gc0.count_reg[8]_i_1_n_6 ; + wire \gic0.gc0.count_reg[8]_i_1_n_7 ; + wire out; + wire ram_full_fb_i_reg; + wire wr_clk; + wire wr_en; + wire [3:0]\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED ; + + LUT3 #( + .INIT(8'h20)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 + (.I0(Q[12]), + .I1(out), + .I2(wr_en), + .O(ena_array)); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gic0.gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gic0.gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gic0.gc0.count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \gic0.gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gic0.gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[12]_i_2 + (.I0(D[12]), + .O(\gic0.gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gic0.gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gic0.gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gic0.gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gic0.gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gic0.gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gic0.gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gic0.gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gic0.gc0.count[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b1)) + \gic0.gc0.count_d1_reg[0] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[0]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[10]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[11]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[12] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[12]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[1] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[1]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[2] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[2]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[3] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[3]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[4] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[4]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[5] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[5]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[6] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[6]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[7] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[7]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[8] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[8]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[9] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[9]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[0] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [0]), + .Q(Q[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [10]), + .Q(Q[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [11]), + .Q(Q[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[12] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [12]), + .Q(Q[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[1] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [1]), + .Q(Q[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[2] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [2]), + .Q(Q[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[3] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [3]), + .Q(Q[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[4] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [4]), + .Q(Q[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[5] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [5]), + .Q(Q[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[6] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [6]), + .Q(Q[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[7] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [7]), + .Q(Q[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[8] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [8]), + .Q(Q[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[9] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [9]), + .Q(Q[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[0] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_7 ), + .Q(D[0]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gic0.gc0.count_reg[0]_i_1_n_0 ,\gic0.gc0.count_reg[0]_i_1_n_1 ,\gic0.gc0.count_reg[0]_i_1_n_2 ,\gic0.gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gic0.gc0.count_reg[0]_i_1_n_4 ,\gic0.gc0.count_reg[0]_i_1_n_5 ,\gic0.gc0.count_reg[0]_i_1_n_6 ,\gic0.gc0.count_reg[0]_i_1_n_7 }), + .S({\gic0.gc0.count[0]_i_2_n_0 ,\gic0.gc0.count[0]_i_3_n_0 ,\gic0.gc0.count[0]_i_4_n_0 ,\gic0.gc0.count[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[12] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[12]_i_1_n_7 ), + .Q(D[12]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[12]_i_1 + (.CI(\gic0.gc0.count_reg[8]_i_1_n_0 ), + .CO(\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED [3:1],\gic0.gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,\gic0.gc0.count[12]_i_2_n_0 })); + FDRE #( + .INIT(1'b1)) + \gic0.gc0.count_reg[1] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_6 ), + .Q(D[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[2] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[3] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[4] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[4]_i_1 + (.CI(\gic0.gc0.count_reg[0]_i_1_n_0 ), + .CO({\gic0.gc0.count_reg[4]_i_1_n_0 ,\gic0.gc0.count_reg[4]_i_1_n_1 ,\gic0.gc0.count_reg[4]_i_1_n_2 ,\gic0.gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[4]_i_1_n_4 ,\gic0.gc0.count_reg[4]_i_1_n_5 ,\gic0.gc0.count_reg[4]_i_1_n_6 ,\gic0.gc0.count_reg[4]_i_1_n_7 }), + .S({\gic0.gc0.count[4]_i_2_n_0 ,\gic0.gc0.count[4]_i_3_n_0 ,\gic0.gc0.count[4]_i_4_n_0 ,\gic0.gc0.count[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[5] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[6] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[7] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[8] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[8]_i_1 + (.CI(\gic0.gc0.count_reg[4]_i_1_n_0 ), + .CO({\gic0.gc0.count_reg[8]_i_1_n_0 ,\gic0.gc0.count_reg[8]_i_1_n_1 ,\gic0.gc0.count_reg[8]_i_1_n_2 ,\gic0.gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[8]_i_1_n_4 ,\gic0.gc0.count_reg[8]_i_1_n_5 ,\gic0.gc0.count_reg[8]_i_1_n_6 ,\gic0.gc0.count_reg[8]_i_1_n_7 }), + .S({\gic0.gc0.count[8]_i_2_n_0 ,\gic0.gc0.count[8]_i_3_n_0 ,\gic0.gc0.count[8]_i_4_n_0 ,\gic0.gc0.count[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[9] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9]), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[0]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(bin2gray[0])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[10]_i_1 + (.I0(Q[10]), + .I1(Q[11]), + .O(bin2gray[10])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[11]_i_1 + (.I0(Q[11]), + .I1(Q[12]), + .O(bin2gray[11])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[1]_i_1 + (.I0(Q[1]), + .I1(Q[2]), + .O(bin2gray[1])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[2]_i_1 + (.I0(Q[2]), + .I1(Q[3]), + .O(bin2gray[2])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[3]_i_1 + (.I0(Q[3]), + .I1(Q[4]), + .O(bin2gray[3])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[4]_i_1 + (.I0(Q[4]), + .I1(Q[5]), + .O(bin2gray[4])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[5]_i_1 + (.I0(Q[5]), + .I1(Q[6]), + .O(bin2gray[5])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[6]_i_1 + (.I0(Q[6]), + .I1(Q[7]), + .O(bin2gray[6])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[7]_i_1 + (.I0(Q[7]), + .I1(Q[8]), + .O(bin2gray[7])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[8]_i_1 + (.I0(Q[8]), + .I1(Q[9]), + .O(bin2gray[8])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[9]_i_1 + (.I0(Q[9]), + .I1(Q[10]), + .O(bin2gray[9])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic + (full, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + Q, + WEA, + D, + \gic0.gc0.count_d2_reg[12] , + bin2gray, + ena_array, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \gnxpm_cdc.rd_pntr_bin_reg[12] , + \gnxpm_cdc.rd_pntr_bin_reg[12]_0 , + wr_clk, + wr_en, + RD_PNTR_WR); + output full; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [12:0]Q; + output [0:0]WEA; + output [0:0]D; + output [0:0]\gic0.gc0.count_d2_reg[12] ; + output [11:0]bin2gray; + output [0:0]ena_array; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; + input \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; + input wr_clk; + input wr_en; + input [11:0]RD_PNTR_WR; + + wire [0:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [12:0]Q; + wire [11:0]RD_PNTR_WR; + wire [0:0]WEA; + wire [11:0]bin2gray; + wire [0:0]ena_array; + wire full; + wire [0:0]\gic0.gc0.count_d2_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; + wire \gwas.wsts_n_1 ; + wire [11:0]p_13_out; + wire wr_clk; + wire wr_en; + wire [11:0]wr_pntr_plus2; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as \gwas.wsts + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .Q(Q[12]), + .RD_PNTR_WR(RD_PNTR_WR), + .full(full), + .\gic0.gc0.count_d1_reg[11] (p_13_out), + .\gic0.gc0.count_d1_reg[12] (WEA), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12] ), + .\gnxpm_cdc.rd_pntr_bin_reg[12]_0 (\gnxpm_cdc.rd_pntr_bin_reg[12]_0 ), + .out(\gwas.wsts_n_1 ), + .wr_clk(wr_clk), + .wr_en(wr_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr + (.D({D,wr_pntr_plus2}), + .Q(Q), + .bin2gray(bin2gray), + .ena_array(ena_array), + .\gic0.gc0.count_d2_reg[12]_0 ({\gic0.gc0.count_d2_reg[12] ,p_13_out}), + .out(\gwas.wsts_n_1 ), + .ram_full_fb_i_reg(WEA), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as + (full, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + \gic0.gc0.count_d1_reg[12] , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \gnxpm_cdc.rd_pntr_bin_reg[12] , + \gnxpm_cdc.rd_pntr_bin_reg[12]_0 , + wr_clk, + wr_en, + Q, + \gic0.gc0.count_d1_reg[11] , + RD_PNTR_WR, + D); + output full; + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output \gic0.gc0.count_d1_reg[12] ; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; + input \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; + input wr_clk; + input wr_en; + input [0:0]Q; + input [11:0]\gic0.gc0.count_d1_reg[11] ; + input [11:0]RD_PNTR_WR; + input [11:0]D; + + wire [11:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [0:0]Q; + wire [11:0]RD_PNTR_WR; + wire c1_n_0; + wire comp2; + wire [11:0]\gic0.gc0.count_d1_reg[11] ; + wire \gic0.gc0.count_d1_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; + (* DONT_TOUCH *) wire ram_full_fb_i; + (* DONT_TOUCH *) wire ram_full_i; + wire wr_clk; + wire wr_en; + + assign full = ram_full_i; + assign out = ram_full_fb_i; + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); + LUT3 #( + .INIT(8'h04)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1 + (.I0(ram_full_fb_i), + .I1(wr_en), + .I2(Q), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(\gic0.gc0.count_d1_reg[12] )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c1 + (.RD_PNTR_WR(RD_PNTR_WR), + .comp2(comp2), + .\gic0.gc0.count_d1_reg[11] (\gic0.gc0.count_d1_reg[11] ), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12] ), + .out(ram_full_fb_i), + .ram_full_i_reg(c1_n_0), + .wr_en(wr_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 c2 + (.D(D), + .RD_PNTR_WR(RD_PNTR_WR), + .comp2(comp2), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12]_0 )); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_fb_i_reg + (.C(wr_clk), + .CE(1'b1), + .D(c1_n_0), + .Q(ram_full_fb_i), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_i_reg + (.C(wr_clk), + .CE(1'b1), + .D(c1_n_0), + .Q(ram_full_i), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/iq_sample_fifo_stub.v b/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/iq_sample_fifo_stub.v new file mode 100755 index 0000000..313c711 --- /dev/null +++ b/fpga/projects/rx_only/rx_only.cache/ip/4d72b0fa095d8e42/iq_sample_fifo_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 +// Date : Sat Apr 15 09:49:57 2017 +// Host : david-desktop-arch running 64-bit unknown +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ iq_sample_fifo_stub.v +// Design : iq_sample_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xc7a50tftg256-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty) +/* synthesis syn_black_box black_box_pad_pin="wr_clk,rd_clk,din[23:0],wr_en,rd_en,dout[23:0],full,empty" */; + input wr_clk; + input rd_clk; + input [23:0]din; + input wr_en; + input rd_en; + output [23:0]dout; + output full; + output empty; +endmodule diff --git a/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/848330eae6fd4c94.xci b/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/848330eae6fd4c94.xci new file mode 100644 index 0000000..99df361 --- /dev/null +++ b/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/848330eae6fd4c94.xci @@ -0,0 +1,204 @@ + + + xilinx.com + ipcache + 848330eae6fd4c94 + 0 + + + rx_packet_fifo + + + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + rx_packet_fifo + 64 + false + 14 + false + false + 0 + 1023 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 1024 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 0 + 16381 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 16380 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 32 + 16384 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 32 + 16384 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + Single_Programmable_Empty_Threshold_Constant + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 14 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + false + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + false + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 14 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + artix7 + + xc7a50t + ftg256 + VHDL + + MIXED + -2 + + TRUE + TRUE + f9fab666 + 848330eae6fd4c94 + IP_Unknown + 2 + TRUE + . + + . + 2016.3 + GLOBAL + + + + diff --git a/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/rx_packet_fifo_sim_netlist.v b/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/rx_packet_fifo_sim_netlist.v new file mode 100755 index 0000000..97ec0ec --- /dev/null +++ b/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/rx_packet_fifo_sim_netlist.v @@ -0,0 +1,11125 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 +// Date : Sat Apr 15 09:39:28 2017 +// Host : david-desktop-arch running 64-bit unknown +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rx_packet_fifo_sim_netlist.v +// Design : rx_packet_fifo +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a50tftg256-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "rx_packet_fifo,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + prog_empty); + (* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk; + (* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk; + (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [31:0]din; + (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; + (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; + (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [31:0]dout; + (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; + (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; + output prog_empty; + + wire [31:0]din; + wire [31:0]dout; + wire empty; + wire full; + wire prog_empty; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + wire NLW_U0_almost_empty_UNCONNECTED; + wire NLW_U0_almost_full_UNCONNECTED; + wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; + wire NLW_U0_axi_ar_overflow_UNCONNECTED; + wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; + wire NLW_U0_axi_ar_prog_full_UNCONNECTED; + wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; + wire NLW_U0_axi_ar_underflow_UNCONNECTED; + wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; + wire NLW_U0_axi_aw_overflow_UNCONNECTED; + wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; + wire NLW_U0_axi_aw_prog_full_UNCONNECTED; + wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; + wire NLW_U0_axi_aw_underflow_UNCONNECTED; + wire NLW_U0_axi_b_dbiterr_UNCONNECTED; + wire NLW_U0_axi_b_overflow_UNCONNECTED; + wire NLW_U0_axi_b_prog_empty_UNCONNECTED; + wire NLW_U0_axi_b_prog_full_UNCONNECTED; + wire NLW_U0_axi_b_sbiterr_UNCONNECTED; + wire NLW_U0_axi_b_underflow_UNCONNECTED; + wire NLW_U0_axi_r_dbiterr_UNCONNECTED; + wire NLW_U0_axi_r_overflow_UNCONNECTED; + wire NLW_U0_axi_r_prog_empty_UNCONNECTED; + wire NLW_U0_axi_r_prog_full_UNCONNECTED; + wire NLW_U0_axi_r_sbiterr_UNCONNECTED; + wire NLW_U0_axi_r_underflow_UNCONNECTED; + wire NLW_U0_axi_w_dbiterr_UNCONNECTED; + wire NLW_U0_axi_w_overflow_UNCONNECTED; + wire NLW_U0_axi_w_prog_empty_UNCONNECTED; + wire NLW_U0_axi_w_prog_full_UNCONNECTED; + wire NLW_U0_axi_w_sbiterr_UNCONNECTED; + wire NLW_U0_axi_w_underflow_UNCONNECTED; + wire NLW_U0_axis_dbiterr_UNCONNECTED; + wire NLW_U0_axis_overflow_UNCONNECTED; + wire NLW_U0_axis_prog_empty_UNCONNECTED; + wire NLW_U0_axis_prog_full_UNCONNECTED; + wire NLW_U0_axis_sbiterr_UNCONNECTED; + wire NLW_U0_axis_underflow_UNCONNECTED; + wire NLW_U0_dbiterr_UNCONNECTED; + wire NLW_U0_m_axi_arvalid_UNCONNECTED; + wire NLW_U0_m_axi_awvalid_UNCONNECTED; + wire NLW_U0_m_axi_bready_UNCONNECTED; + wire NLW_U0_m_axi_rready_UNCONNECTED; + wire NLW_U0_m_axi_wlast_UNCONNECTED; + wire NLW_U0_m_axi_wvalid_UNCONNECTED; + wire NLW_U0_m_axis_tlast_UNCONNECTED; + wire NLW_U0_m_axis_tvalid_UNCONNECTED; + wire NLW_U0_overflow_UNCONNECTED; + wire NLW_U0_prog_full_UNCONNECTED; + wire NLW_U0_rd_rst_busy_UNCONNECTED; + wire NLW_U0_s_axi_arready_UNCONNECTED; + wire NLW_U0_s_axi_awready_UNCONNECTED; + wire NLW_U0_s_axi_bvalid_UNCONNECTED; + wire NLW_U0_s_axi_rlast_UNCONNECTED; + wire NLW_U0_s_axi_rvalid_UNCONNECTED; + wire NLW_U0_s_axi_wready_UNCONNECTED; + wire NLW_U0_s_axis_tready_UNCONNECTED; + wire NLW_U0_sbiterr_UNCONNECTED; + wire NLW_U0_underflow_UNCONNECTED; + wire NLW_U0_valid_UNCONNECTED; + wire NLW_U0_wr_ack_UNCONNECTED; + wire NLW_U0_wr_rst_busy_UNCONNECTED; + wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; + wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; + wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; + wire [13:0]NLW_U0_data_count_UNCONNECTED; + wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; + wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; + wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; + wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; + wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; + wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; + wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; + wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; + wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; + wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; + wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; + wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; + wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; + wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; + wire [13:0]NLW_U0_rd_data_count_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; + wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; + wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; + wire [13:0]NLW_U0_wr_data_count_UNCONNECTED; + + (* C_ADD_NGC_CONSTRAINT = "0" *) + (* C_APPLICATION_TYPE_AXIS = "0" *) + (* C_APPLICATION_TYPE_RACH = "0" *) + (* C_APPLICATION_TYPE_RDCH = "0" *) + (* C_APPLICATION_TYPE_WACH = "0" *) + (* C_APPLICATION_TYPE_WDCH = "0" *) + (* C_APPLICATION_TYPE_WRCH = "0" *) + (* C_AXIS_TDATA_WIDTH = "8" *) + (* C_AXIS_TDEST_WIDTH = "1" *) + (* C_AXIS_TID_WIDTH = "1" *) + (* C_AXIS_TKEEP_WIDTH = "1" *) + (* C_AXIS_TSTRB_WIDTH = "1" *) + (* C_AXIS_TUSER_WIDTH = "4" *) + (* C_AXIS_TYPE = "0" *) + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "64" *) + (* C_AXI_ID_WIDTH = "1" *) + (* C_AXI_LEN_WIDTH = "8" *) + (* C_AXI_LOCK_WIDTH = "1" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_TYPE = "1" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_COMMON_CLOCK = "0" *) + (* C_COUNT_TYPE = "0" *) + (* C_DATA_COUNT_WIDTH = "14" *) + (* C_DEFAULT_VALUE = "BlankString" *) + (* C_DIN_WIDTH = "32" *) + (* C_DIN_WIDTH_AXIS = "1" *) + (* C_DIN_WIDTH_RACH = "32" *) + (* C_DIN_WIDTH_RDCH = "64" *) + (* C_DIN_WIDTH_WACH = "1" *) + (* C_DIN_WIDTH_WDCH = "64" *) + (* C_DIN_WIDTH_WRCH = "2" *) + (* C_DOUT_RST_VAL = "0" *) + (* C_DOUT_WIDTH = "32" *) + (* C_ENABLE_RLOCS = "0" *) + (* C_ENABLE_RST_SYNC = "1" *) + (* C_EN_SAFETY_CKT = "0" *) + (* C_ERROR_INJECTION_TYPE = "0" *) + (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) + (* C_ERROR_INJECTION_TYPE_RACH = "0" *) + (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WACH = "0" *) + (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) + (* C_FAMILY = "artix7" *) + (* C_FULL_FLAGS_RST_VAL = "0" *) + (* C_HAS_ALMOST_EMPTY = "0" *) + (* C_HAS_ALMOST_FULL = "0" *) + (* C_HAS_AXIS_TDATA = "1" *) + (* C_HAS_AXIS_TDEST = "0" *) + (* C_HAS_AXIS_TID = "0" *) + (* C_HAS_AXIS_TKEEP = "0" *) + (* C_HAS_AXIS_TLAST = "0" *) + (* C_HAS_AXIS_TREADY = "1" *) + (* C_HAS_AXIS_TSTRB = "0" *) + (* C_HAS_AXIS_TUSER = "1" *) + (* C_HAS_AXI_ARUSER = "0" *) + (* C_HAS_AXI_AWUSER = "0" *) + (* C_HAS_AXI_BUSER = "0" *) + (* C_HAS_AXI_ID = "0" *) + (* C_HAS_AXI_RD_CHANNEL = "1" *) + (* C_HAS_AXI_RUSER = "0" *) + (* C_HAS_AXI_WR_CHANNEL = "1" *) + (* C_HAS_AXI_WUSER = "0" *) + (* C_HAS_BACKUP = "0" *) + (* C_HAS_DATA_COUNT = "0" *) + (* C_HAS_DATA_COUNTS_AXIS = "0" *) + (* C_HAS_DATA_COUNTS_RACH = "0" *) + (* C_HAS_DATA_COUNTS_RDCH = "0" *) + (* C_HAS_DATA_COUNTS_WACH = "0" *) + (* C_HAS_DATA_COUNTS_WDCH = "0" *) + (* C_HAS_DATA_COUNTS_WRCH = "0" *) + (* C_HAS_INT_CLK = "0" *) + (* C_HAS_MASTER_CE = "0" *) + (* C_HAS_MEMINIT_FILE = "0" *) + (* C_HAS_OVERFLOW = "0" *) + (* C_HAS_PROG_FLAGS_AXIS = "0" *) + (* C_HAS_PROG_FLAGS_RACH = "0" *) + (* C_HAS_PROG_FLAGS_RDCH = "0" *) + (* C_HAS_PROG_FLAGS_WACH = "0" *) + (* C_HAS_PROG_FLAGS_WDCH = "0" *) + (* C_HAS_PROG_FLAGS_WRCH = "0" *) + (* C_HAS_RD_DATA_COUNT = "0" *) + (* C_HAS_RD_RST = "0" *) + (* C_HAS_RST = "0" *) + (* C_HAS_SLAVE_CE = "0" *) + (* C_HAS_SRST = "0" *) + (* C_HAS_UNDERFLOW = "0" *) + (* C_HAS_VALID = "0" *) + (* C_HAS_WR_ACK = "0" *) + (* C_HAS_WR_DATA_COUNT = "0" *) + (* C_HAS_WR_RST = "0" *) + (* C_IMPLEMENTATION_TYPE = "2" *) + (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) + (* C_IMPLEMENTATION_TYPE_RACH = "1" *) + (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WACH = "1" *) + (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) + (* C_INIT_WR_PNTR_VAL = "0" *) + (* C_INTERFACE_TYPE = "0" *) + (* C_MEMORY_TYPE = "1" *) + (* C_MIF_FILE_NAME = "BlankString" *) + (* C_MSGON_VAL = "1" *) + (* C_OPTIMIZATION_MODE = "0" *) + (* C_OVERFLOW_LOW = "0" *) + (* C_POWER_SAVING_MODE = "0" *) + (* C_PRELOAD_LATENCY = "1" *) + (* C_PRELOAD_REGS = "0" *) + (* C_PRIM_FIFO_TYPE = "8kx4" *) + (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) + (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) + (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) + (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "1023" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) + (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "1024" *) + (* C_PROG_EMPTY_TYPE = "1" *) + (* C_PROG_EMPTY_TYPE_AXIS = "0" *) + (* C_PROG_EMPTY_TYPE_RACH = "0" *) + (* C_PROG_EMPTY_TYPE_RDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WACH = "0" *) + (* C_PROG_EMPTY_TYPE_WDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WRCH = "0" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL = "16381" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) + (* C_PROG_FULL_THRESH_NEGATE_VAL = "16380" *) + (* C_PROG_FULL_TYPE = "0" *) + (* C_PROG_FULL_TYPE_AXIS = "0" *) + (* C_PROG_FULL_TYPE_RACH = "0" *) + (* C_PROG_FULL_TYPE_RDCH = "0" *) + (* C_PROG_FULL_TYPE_WACH = "0" *) + (* C_PROG_FULL_TYPE_WDCH = "0" *) + (* C_PROG_FULL_TYPE_WRCH = "0" *) + (* C_RACH_TYPE = "0" *) + (* C_RDCH_TYPE = "0" *) + (* C_RD_DATA_COUNT_WIDTH = "14" *) + (* C_RD_DEPTH = "16384" *) + (* C_RD_FREQ = "1" *) + (* C_RD_PNTR_WIDTH = "14" *) + (* C_REG_SLICE_MODE_AXIS = "0" *) + (* C_REG_SLICE_MODE_RACH = "0" *) + (* C_REG_SLICE_MODE_RDCH = "0" *) + (* C_REG_SLICE_MODE_WACH = "0" *) + (* C_REG_SLICE_MODE_WDCH = "0" *) + (* C_REG_SLICE_MODE_WRCH = "0" *) + (* C_SELECT_XPM = "0" *) + (* C_SYNCHRONIZER_STAGE = "2" *) + (* C_UNDERFLOW_LOW = "0" *) + (* C_USE_COMMON_OVERFLOW = "0" *) + (* C_USE_COMMON_UNDERFLOW = "0" *) + (* C_USE_DEFAULT_SETTINGS = "0" *) + (* C_USE_DOUT_RST = "0" *) + (* C_USE_ECC = "0" *) + (* C_USE_ECC_AXIS = "0" *) + (* C_USE_ECC_RACH = "0" *) + (* C_USE_ECC_RDCH = "0" *) + (* C_USE_ECC_WACH = "0" *) + (* C_USE_ECC_WDCH = "0" *) + (* C_USE_ECC_WRCH = "0" *) + (* C_USE_EMBEDDED_REG = "0" *) + (* C_USE_FIFO16_FLAGS = "0" *) + (* C_USE_FWFT_DATA_COUNT = "0" *) + (* C_USE_PIPELINE_REG = "0" *) + (* C_VALID_LOW = "0" *) + (* C_WACH_TYPE = "0" *) + (* C_WDCH_TYPE = "0" *) + (* C_WRCH_TYPE = "0" *) + (* C_WR_ACK_LOW = "0" *) + (* C_WR_DATA_COUNT_WIDTH = "14" *) + (* C_WR_DEPTH = "16384" *) + (* C_WR_DEPTH_AXIS = "1024" *) + (* C_WR_DEPTH_RACH = "16" *) + (* C_WR_DEPTH_RDCH = "1024" *) + (* C_WR_DEPTH_WACH = "16" *) + (* C_WR_DEPTH_WDCH = "1024" *) + (* C_WR_DEPTH_WRCH = "16" *) + (* C_WR_FREQ = "1" *) + (* C_WR_PNTR_WIDTH = "14" *) + (* C_WR_PNTR_WIDTH_AXIS = "10" *) + (* C_WR_PNTR_WIDTH_RACH = "4" *) + (* C_WR_PNTR_WIDTH_RDCH = "10" *) + (* C_WR_PNTR_WIDTH_WACH = "4" *) + (* C_WR_PNTR_WIDTH_WDCH = "10" *) + (* C_WR_PNTR_WIDTH_WRCH = "4" *) + (* C_WR_RESPONSE_LATENCY = "1" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0 + (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), + .almost_full(NLW_U0_almost_full_UNCONNECTED), + .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), + .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), + .axi_ar_injectdbiterr(1'b0), + .axi_ar_injectsbiterr(1'b0), + .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), + .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), + .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), + .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), + .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), + .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), + .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), + .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), + .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), + .axi_aw_injectdbiterr(1'b0), + .axi_aw_injectsbiterr(1'b0), + .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), + .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), + .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), + .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), + .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), + .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), + .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), + .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), + .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), + .axi_b_injectdbiterr(1'b0), + .axi_b_injectsbiterr(1'b0), + .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), + .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), + .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), + .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), + .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), + .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), + .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), + .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), + .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), + .axi_r_injectdbiterr(1'b0), + .axi_r_injectsbiterr(1'b0), + .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), + .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), + .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), + .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), + .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), + .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), + .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), + .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), + .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), + .axi_w_injectdbiterr(1'b0), + .axi_w_injectsbiterr(1'b0), + .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), + .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), + .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), + .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), + .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), + .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), + .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), + .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), + .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), + .axis_injectdbiterr(1'b0), + .axis_injectsbiterr(1'b0), + .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), + .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), + .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), + .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), + .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), + .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), + .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), + .backup(1'b0), + .backup_marker(1'b0), + .clk(1'b0), + .data_count(NLW_U0_data_count_UNCONNECTED[13:0]), + .dbiterr(NLW_U0_dbiterr_UNCONNECTED), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .int_clk(1'b0), + .m_aclk(1'b0), + .m_aclk_en(1'b0), + .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), + .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), + .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), + .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), + .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), + .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), + .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), + .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), + .m_axi_arready(1'b0), + .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), + .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), + .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), + .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), + .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), + .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), + .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), + .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), + .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), + .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), + .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), + .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), + .m_axi_awready(1'b0), + .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), + .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), + .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), + .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), + .m_axi_bid(1'b0), + .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), + .m_axi_bresp({1'b0,1'b0}), + .m_axi_buser(1'b0), + .m_axi_bvalid(1'b0), + .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_rid(1'b0), + .m_axi_rlast(1'b0), + .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), + .m_axi_rresp({1'b0,1'b0}), + .m_axi_ruser(1'b0), + .m_axi_rvalid(1'b0), + .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), + .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), + .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), + .m_axi_wready(1'b0), + .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), + .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), + .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), + .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]), + .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), + .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), + .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]), + .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), + .m_axis_tready(1'b0), + .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]), + .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), + .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), + .overflow(NLW_U0_overflow_UNCONNECTED), + .prog_empty(prog_empty), + .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full(NLW_U0_prog_full_UNCONNECTED), + .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .rd_clk(rd_clk), + .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[13:0]), + .rd_en(rd_en), + .rd_rst(1'b0), + .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), + .rst(1'b0), + .s_aclk(1'b0), + .s_aclk_en(1'b0), + .s_aresetn(1'b0), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid(1'b0), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlock(1'b0), + .s_axi_arprot({1'b0,1'b0,1'b0}), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(1'b0), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid(1'b0), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock(1'b0), + .s_axi_awprot({1'b0,1'b0,1'b0}), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(1'b0), + .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), + .s_axi_bready(1'b0), + .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), + .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), + .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), + .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), + .s_axi_rready(1'b0), + .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), + .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), + .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wid(1'b0), + .s_axi_wlast(1'b0), + .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), + .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wuser(1'b0), + .s_axi_wvalid(1'b0), + .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tdest(1'b0), + .s_axis_tid(1'b0), + .s_axis_tkeep(1'b0), + .s_axis_tlast(1'b0), + .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), + .s_axis_tstrb(1'b0), + .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tvalid(1'b0), + .sbiterr(NLW_U0_sbiterr_UNCONNECTED), + .sleep(1'b0), + .srst(1'b0), + .underflow(NLW_U0_underflow_UNCONNECTED), + .valid(NLW_U0_valid_UNCONNECTED), + .wr_ack(NLW_U0_wr_ack_UNCONNECTED), + .wr_clk(wr_clk), + .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[13:0]), + .wr_en(wr_en), + .wr_rst(1'b0), + .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bindec + (ena_array, + out, + wr_en, + Q); + output [2:0]ena_array; + input out; + input wr_en; + input [1:0]Q; + + wire [1:0]Q; + wire [2:0]ena_array; + wire out; + wire wr_en; + + LUT4 #( + .INIT(16'h0004)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 + (.I0(out), + .I1(wr_en), + .I2(Q[0]), + .I3(Q[1]), + .O(ena_array[0])); + LUT4 #( + .INIT(16'h0040)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(wr_en), + .I3(out), + .O(ena_array[1])); + LUT4 #( + .INIT(16'h0400)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1 + (.I0(Q[0]), + .I1(wr_en), + .I2(out), + .I3(Q[1]), + .O(ena_array[2])); +endmodule + +(* ORIG_REF_NAME = "bindec" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bindec_0 + (enb_array, + ram_empty_fb_i_reg, + rd_en, + \gc0.count_d1_reg[13] ); + output [2:0]enb_array; + input ram_empty_fb_i_reg; + input rd_en; + input [1:0]\gc0.count_d1_reg[13] ; + + wire [2:0]enb_array; + wire [1:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire rd_en; + + LUT4 #( + .INIT(16'h0004)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 + (.I0(ram_empty_fb_i_reg), + .I1(rd_en), + .I2(\gc0.count_d1_reg[13] [0]), + .I3(\gc0.count_d1_reg[13] [1]), + .O(enb_array[0])); + LUT4 #( + .INIT(16'h0040)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0 + (.I0(\gc0.count_d1_reg[13] [1]), + .I1(\gc0.count_d1_reg[13] [0]), + .I2(rd_en), + .I3(ram_empty_fb_i_reg), + .O(enb_array[1])); + LUT4 #( + .INIT(16'h0400)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1 + (.I0(\gc0.count_d1_reg[13] [0]), + .I1(rd_en), + .I2(ram_empty_fb_i_reg), + .I3(\gc0.count_d1_reg[13] [1]), + .O(enb_array[2])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr + (dout, + wr_clk, + rd_clk, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg, + WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , + ram_full_fb_i_reg_0, + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); + output [31:0]dout; + input wr_clk; + input rd_clk; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [31:0]din; + input [0:0]ram_full_fb_i_reg; + input [0:0]WEA; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; + + wire [13:0]Q; + wire [0:0]WEA; + wire [31:0]din; + wire [31:0]dout; + wire [2:0]ena_array; + wire [2:0]enb_array; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; + wire ram_empty_fb_i_reg; + wire ram_ena_n_0; + wire ram_enb_n_0; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire \ramloop[10].ram.r_n_0 ; + wire \ramloop[10].ram.r_n_1 ; + wire \ramloop[10].ram.r_n_2 ; + wire \ramloop[10].ram.r_n_3 ; + wire \ramloop[10].ram.r_n_4 ; + wire \ramloop[10].ram.r_n_5 ; + wire \ramloop[10].ram.r_n_6 ; + wire \ramloop[10].ram.r_n_7 ; + wire \ramloop[10].ram.r_n_8 ; + wire \ramloop[11].ram.r_n_0 ; + wire \ramloop[11].ram.r_n_1 ; + wire \ramloop[11].ram.r_n_2 ; + wire \ramloop[11].ram.r_n_3 ; + wire \ramloop[11].ram.r_n_4 ; + wire \ramloop[11].ram.r_n_5 ; + wire \ramloop[11].ram.r_n_6 ; + wire \ramloop[11].ram.r_n_7 ; + wire \ramloop[11].ram.r_n_8 ; + wire \ramloop[12].ram.r_n_0 ; + wire \ramloop[12].ram.r_n_1 ; + wire \ramloop[12].ram.r_n_2 ; + wire \ramloop[12].ram.r_n_3 ; + wire \ramloop[12].ram.r_n_4 ; + wire \ramloop[12].ram.r_n_5 ; + wire \ramloop[12].ram.r_n_6 ; + wire \ramloop[12].ram.r_n_7 ; + wire \ramloop[12].ram.r_n_8 ; + wire \ramloop[13].ram.r_n_0 ; + wire \ramloop[13].ram.r_n_1 ; + wire \ramloop[13].ram.r_n_2 ; + wire \ramloop[13].ram.r_n_3 ; + wire \ramloop[13].ram.r_n_4 ; + wire \ramloop[13].ram.r_n_5 ; + wire \ramloop[13].ram.r_n_6 ; + wire \ramloop[13].ram.r_n_7 ; + wire \ramloop[13].ram.r_n_8 ; + wire \ramloop[14].ram.r_n_0 ; + wire \ramloop[14].ram.r_n_1 ; + wire \ramloop[14].ram.r_n_2 ; + wire \ramloop[14].ram.r_n_3 ; + wire \ramloop[14].ram.r_n_4 ; + wire \ramloop[14].ram.r_n_5 ; + wire \ramloop[14].ram.r_n_6 ; + wire \ramloop[14].ram.r_n_7 ; + wire \ramloop[14].ram.r_n_8 ; + wire \ramloop[3].ram.r_n_0 ; + wire \ramloop[3].ram.r_n_1 ; + wire \ramloop[3].ram.r_n_2 ; + wire \ramloop[3].ram.r_n_3 ; + wire \ramloop[3].ram.r_n_4 ; + wire \ramloop[3].ram.r_n_5 ; + wire \ramloop[3].ram.r_n_6 ; + wire \ramloop[3].ram.r_n_7 ; + wire \ramloop[3].ram.r_n_8 ; + wire \ramloop[4].ram.r_n_0 ; + wire \ramloop[4].ram.r_n_1 ; + wire \ramloop[4].ram.r_n_2 ; + wire \ramloop[4].ram.r_n_3 ; + wire \ramloop[4].ram.r_n_4 ; + wire \ramloop[4].ram.r_n_5 ; + wire \ramloop[4].ram.r_n_6 ; + wire \ramloop[4].ram.r_n_7 ; + wire \ramloop[4].ram.r_n_8 ; + wire \ramloop[5].ram.r_n_0 ; + wire \ramloop[5].ram.r_n_1 ; + wire \ramloop[5].ram.r_n_2 ; + wire \ramloop[5].ram.r_n_3 ; + wire \ramloop[5].ram.r_n_4 ; + wire \ramloop[5].ram.r_n_5 ; + wire \ramloop[5].ram.r_n_6 ; + wire \ramloop[5].ram.r_n_7 ; + wire \ramloop[5].ram.r_n_8 ; + wire \ramloop[6].ram.r_n_0 ; + wire \ramloop[6].ram.r_n_1 ; + wire \ramloop[6].ram.r_n_2 ; + wire \ramloop[6].ram.r_n_3 ; + wire \ramloop[6].ram.r_n_4 ; + wire \ramloop[6].ram.r_n_5 ; + wire \ramloop[6].ram.r_n_6 ; + wire \ramloop[6].ram.r_n_7 ; + wire \ramloop[6].ram.r_n_8 ; + wire \ramloop[7].ram.r_n_0 ; + wire \ramloop[7].ram.r_n_1 ; + wire \ramloop[7].ram.r_n_2 ; + wire \ramloop[7].ram.r_n_3 ; + wire \ramloop[7].ram.r_n_4 ; + wire \ramloop[7].ram.r_n_5 ; + wire \ramloop[7].ram.r_n_6 ; + wire \ramloop[7].ram.r_n_7 ; + wire \ramloop[7].ram.r_n_8 ; + wire \ramloop[8].ram.r_n_0 ; + wire \ramloop[8].ram.r_n_1 ; + wire \ramloop[8].ram.r_n_2 ; + wire \ramloop[8].ram.r_n_3 ; + wire \ramloop[8].ram.r_n_4 ; + wire \ramloop[8].ram.r_n_5 ; + wire \ramloop[8].ram.r_n_6 ; + wire \ramloop[8].ram.r_n_7 ; + wire \ramloop[8].ram.r_n_8 ; + wire \ramloop[9].ram.r_n_0 ; + wire \ramloop[9].ram.r_n_1 ; + wire \ramloop[9].ram.r_n_2 ; + wire \ramloop[9].ram.r_n_3 ; + wire \ramloop[9].ram.r_n_4 ; + wire \ramloop[9].ram.r_n_5 ; + wire \ramloop[9].ram.r_n_6 ; + wire \ramloop[9].ram.r_n_7 ; + wire \ramloop[9].ram.r_n_8 ; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bindec \bindec_a.bindec_inst_a + (.Q(Q[13:12]), + .ena_array(ena_array), + .out(out), + .wr_en(wr_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bindec_0 \bindec_b.bindec_inst_b + (.enb_array(enb_array), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] [13:12]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .rd_en(rd_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux__parameterized0 \has_mux_b.B + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 (\ramloop[8].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 (\ramloop[9].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 (\ramloop[7].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ({\ramloop[14].ram.r_n_0 ,\ramloop[14].ram.r_n_1 ,\ramloop[14].ram.r_n_2 ,\ramloop[14].ram.r_n_3 ,\ramloop[14].ram.r_n_4 ,\ramloop[14].ram.r_n_5 ,\ramloop[14].ram.r_n_6 ,\ramloop[14].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ({\ramloop[12].ram.r_n_0 ,\ramloop[12].ram.r_n_1 ,\ramloop[12].ram.r_n_2 ,\ramloop[12].ram.r_n_3 ,\ramloop[12].ram.r_n_4 ,\ramloop[12].ram.r_n_5 ,\ramloop[12].ram.r_n_6 ,\ramloop[12].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ({\ramloop[13].ram.r_n_0 ,\ramloop[13].ram.r_n_1 ,\ramloop[13].ram.r_n_2 ,\ramloop[13].ram.r_n_3 ,\ramloop[13].ram.r_n_4 ,\ramloop[13].ram.r_n_5 ,\ramloop[13].ram.r_n_6 ,\ramloop[13].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ({\ramloop[11].ram.r_n_0 ,\ramloop[11].ram.r_n_1 ,\ramloop[11].ram.r_n_2 ,\ramloop[11].ram.r_n_3 ,\ramloop[11].ram.r_n_4 ,\ramloop[11].ram.r_n_5 ,\ramloop[11].ram.r_n_6 ,\ramloop[11].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 (\ramloop[14].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 (\ramloop[12].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 (\ramloop[13].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\ramloop[4].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 (\ramloop[11].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\ramloop[5].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 (\ramloop[3].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ({\ramloop[10].ram.r_n_0 ,\ramloop[10].ram.r_n_1 ,\ramloop[10].ram.r_n_2 ,\ramloop[10].ram.r_n_3 ,\ramloop[10].ram.r_n_4 ,\ramloop[10].ram.r_n_5 ,\ramloop[10].ram.r_n_6 ,\ramloop[10].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 (\ramloop[10].ram.r_n_8 ), + .DOBDO({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }), + .DOPBDOP(\ramloop[6].ram.r_n_8 ), + .dout(dout[31:5]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] [13:12]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .rd_clk(rd_clk), + .rd_en(rd_en)); + LUT2 #( + .INIT(4'h2)) + ram_ena + (.I0(wr_en), + .I1(out), + .O(ram_ena_n_0)); + LUT2 #( + .INIT(4'h2)) + ram_enb + (.I0(rd_en), + .I1(ram_empty_fb_i_reg), + .O(ram_enb_n_0)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r + (.Q(Q), + .din(din[0]), + .dout(dout[0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_enb_n_0), + .ram_full_fb_i_reg(ram_ena_n_0), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r + (.Q(Q[11:0]), + .din(din[22:14]), + .\dout[21] ({\ramloop[10].ram.r_n_0 ,\ramloop[10].ram.r_n_1 ,\ramloop[10].ram.r_n_2 ,\ramloop[10].ram.r_n_3 ,\ramloop[10].ram.r_n_4 ,\ramloop[10].ram.r_n_5 ,\ramloop[10].ram.r_n_6 ,\ramloop[10].ram.r_n_7 }), + .\dout[22] (\ramloop[10].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[31:23]), + .\dout[30] ({\ramloop[11].ram.r_n_0 ,\ramloop[11].ram.r_n_1 ,\ramloop[11].ram.r_n_2 ,\ramloop[11].ram.r_n_3 ,\ramloop[11].ram.r_n_4 ,\ramloop[11].ram.r_n_5 ,\ramloop[11].ram.r_n_6 ,\ramloop[11].ram.r_n_7 }), + .\dout[31] (\ramloop[11].ram.r_n_8 ), + .ena_array(ena_array[0]), + .enb_array(enb_array[0]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r + (.Q(Q[11:0]), + .din(din[31:23]), + .\dout[30] ({\ramloop[12].ram.r_n_0 ,\ramloop[12].ram.r_n_1 ,\ramloop[12].ram.r_n_2 ,\ramloop[12].ram.r_n_3 ,\ramloop[12].ram.r_n_4 ,\ramloop[12].ram.r_n_5 ,\ramloop[12].ram.r_n_6 ,\ramloop[12].ram.r_n_7 }), + .\dout[31] (\ramloop[12].ram.r_n_8 ), + .ena_array(ena_array[1]), + .enb_array(enb_array[1]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[31:23]), + .\dout[30] ({\ramloop[13].ram.r_n_0 ,\ramloop[13].ram.r_n_1 ,\ramloop[13].ram.r_n_2 ,\ramloop[13].ram.r_n_3 ,\ramloop[13].ram.r_n_4 ,\ramloop[13].ram.r_n_5 ,\ramloop[13].ram.r_n_6 ,\ramloop[13].ram.r_n_7 }), + .\dout[31] (\ramloop[13].ram.r_n_8 ), + .ena_array(ena_array[2]), + .enb_array(enb_array[2]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r + (.Q(Q[11:0]), + .din(din[31:23]), + .\dout[30] ({\ramloop[14].ram.r_n_0 ,\ramloop[14].ram.r_n_1 ,\ramloop[14].ram.r_n_2 ,\ramloop[14].ram.r_n_3 ,\ramloop[14].ram.r_n_4 ,\ramloop[14].ram.r_n_5 ,\ramloop[14].ram.r_n_6 ,\ramloop[14].ram.r_n_7 }), + .\dout[31] (\ramloop[14].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r + (.Q(Q), + .din(din[2:1]), + .dout(dout[2:1]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_enb_n_0), + .ram_full_fb_i_reg(ram_ena_n_0), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r + (.Q(Q), + .din(din[4:3]), + .dout(dout[4:3]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_enb_n_0), + .ram_full_fb_i_reg(ram_ena_n_0), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r + (.Q(Q[11:0]), + .din(din[13:5]), + .\dout[12] ({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .\dout[13] (\ramloop[3].ram.r_n_8 ), + .ena_array(ena_array[0]), + .enb_array(enb_array[0]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r + (.Q(Q[11:0]), + .din(din[13:5]), + .\dout[12] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\dout[13] (\ramloop[4].ram.r_n_8 ), + .ena_array(ena_array[1]), + .enb_array(enb_array[1]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[13:5]), + .\dout[12] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\dout[13] (\ramloop[5].ram.r_n_8 ), + .ena_array(ena_array[2]), + .enb_array(enb_array[2]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r + (.DOBDO({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }), + .DOPBDOP(\ramloop[6].ram.r_n_8 ), + .Q(Q[11:0]), + .din(din[13:5]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[22:14]), + .\dout[21] ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }), + .\dout[22] (\ramloop[7].ram.r_n_8 ), + .ena_array(ena_array[0]), + .enb_array(enb_array[0]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r + (.Q(Q[11:0]), + .din(din[22:14]), + .\dout[21] ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }), + .\dout[22] (\ramloop[8].ram.r_n_8 ), + .ena_array(ena_array[1]), + .enb_array(enb_array[1]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[22:14]), + .\dout[21] ({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }), + .\dout[22] (\ramloop[9].ram.r_n_8 ), + .ena_array(ena_array[2]), + .enb_array(enb_array[2]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_mux" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_mux__parameterized0 + (dout, + \gc0.count_d1_reg[13] , + rd_en, + ram_empty_fb_i_reg, + rd_clk, + DOBDO, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 , + DOPBDOP, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ); + output [26:0]dout; + input [1:0]\gc0.count_d1_reg[13] ; + input rd_en; + input ram_empty_fb_i_reg; + input rd_clk; + input [7:0]DOBDO; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + input [0:0]DOPBDOP; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ; + + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ; + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [26:0]dout; + wire [1:0]\gc0.count_d1_reg[13] ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 ; + wire ram_empty_fb_i_reg; + wire rd_clk; + wire rd_en; + wire [1:0]sel_pipe; + + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[10]_INST_0 + (.I0(DOBDO[5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [5]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [5]), + .I5(sel_pipe[0]), + .O(dout[5])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[11]_INST_0 + (.I0(DOBDO[6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [6]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [6]), + .I5(sel_pipe[0]), + .O(dout[6])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[12]_INST_0 + (.I0(DOBDO[7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [7]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [7]), + .I5(sel_pipe[0]), + .O(dout[7])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[13]_INST_0 + (.I0(DOPBDOP), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ), + .I5(sel_pipe[0]), + .O(dout[8])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[14]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [0]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [0]), + .I5(sel_pipe[0]), + .O(dout[9])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[15]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [1]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [1]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [1]), + .I5(sel_pipe[0]), + .O(dout[10])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[16]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [2]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [2]), + .I5(sel_pipe[0]), + .O(dout[11])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[17]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [3]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [3]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [3]), + .I5(sel_pipe[0]), + .O(dout[12])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[18]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [4]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [4]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [4]), + .I5(sel_pipe[0]), + .O(dout[13])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[19]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [5]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [5]), + .I5(sel_pipe[0]), + .O(dout[14])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[20]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [6]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [6]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [6]), + .I5(sel_pipe[0]), + .O(dout[15])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[21]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [7]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [7]), + .I5(sel_pipe[0]), + .O(dout[16])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[22]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ), + .I5(sel_pipe[0]), + .O(dout[17])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[23]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [0]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [0]), + .I5(sel_pipe[0]), + .O(dout[18])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[24]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [1]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [1]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [1]), + .I5(sel_pipe[0]), + .O(dout[19])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[25]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [2]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [2]), + .I5(sel_pipe[0]), + .O(dout[20])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[26]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [3]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [3]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [3]), + .I5(sel_pipe[0]), + .O(dout[21])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[27]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [4]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [4]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [4]), + .I5(sel_pipe[0]), + .O(dout[22])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[28]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [5]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [5]), + .I5(sel_pipe[0]), + .O(dout[23])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[29]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [6]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [6]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [6]), + .I5(sel_pipe[0]), + .O(dout[24])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[30]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [7]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [7]), + .I5(sel_pipe[0]), + .O(dout[25])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[31]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ), + .I5(sel_pipe[0]), + .O(dout[26])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[5]_INST_0 + (.I0(DOBDO[0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [0]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [0]), + .I5(sel_pipe[0]), + .O(dout[0])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[6]_INST_0 + (.I0(DOBDO[1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [1]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [1]), + .I5(sel_pipe[0]), + .O(dout[1])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[7]_INST_0 + (.I0(DOBDO[2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [2]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [2]), + .I5(sel_pipe[0]), + .O(dout[2])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[8]_INST_0 + (.I0(DOBDO[3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [3]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [3]), + .I5(sel_pipe[0]), + .O(dout[3])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[9]_INST_0 + (.I0(DOBDO[4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [4]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [4]), + .I5(sel_pipe[0]), + .O(dout[4])); + LUT4 #( + .INIT(16'hFB08)) + \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1 + (.I0(\gc0.count_d1_reg[13] [0]), + .I1(rd_en), + .I2(ram_empty_fb_i_reg), + .I3(sel_pipe[0]), + .O(\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1 + (.I0(\gc0.count_d1_reg[13] [1]), + .I1(rd_en), + .I2(ram_empty_fb_i_reg), + .I3(sel_pipe[1]), + .O(\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 ), + .Q(sel_pipe[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 ), + .Q(sel_pipe[1]), + .R(1'b0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg_0); + output [0:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [0:0]din; + input [0:0]ram_full_fb_i_reg_0; + + wire [13:0]Q; + wire [0:0]din; + wire [0:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg_0); + output [1:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; + + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg_0); + output [1:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; + + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[12] (\dout[12] ), + .\dout[13] (\dout[13] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[12] (\dout[12] ), + .\dout[13] (\dout[13] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[12] (\dout[12] ), + .\dout[13] (\dout[13] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 + (DOBDO, + DOPBDOP, + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]DOBDO; + output [0:0]DOPBDOP; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [11:0]Q; + wire [8:0]din; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram + (.DOBDO(DOBDO), + .DOPBDOP(DOPBDOP), + .Q(Q), + .din(din), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg_0); + output [0:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [0:0]din; + input [0:0]ram_full_fb_i_reg_0; + + wire [13:0]Q; + wire [0:0]din; + wire [0:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; + wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; + wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; + wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB18E1 #( + .DOA_REG(0), + .DOB_REG(0), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(18'h00000), + .INIT_B(18'h00000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(1), + .READ_WIDTH_B(1), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(18'h00000), + .SRVAL_B(18'h00000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(1), + .WRITE_WIDTH_B(1)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram + (.ADDRARDADDR(Q), + .ADDRBWRADDR(\gc0.count_d1_reg[13] ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:1],dout}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .WEA({ram_full_fb_i_reg_0,ram_full_fb_i_reg_0}), + .WEBWE({1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg_0); + output [1:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; + + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(2), + .READ_WIDTH_B(2), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(2), + .WRITE_WIDTH_B(2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[13] ,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],dout}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg_0); + output [1:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; + + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(2), + .READ_WIDTH_B(2), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(2), + .WRITE_WIDTH_B(2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[13] ,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],dout}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(\gic0.gc0.count_d2_reg[13] ), + .ENBWREN(\gc0.count_d1_reg[13] ), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[12] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[13] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[12] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[13] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[12] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[13] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 + (DOBDO, + DOPBDOP, + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]DOBDO; + output [0:0]DOPBDOP; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [11:0]Q; + wire [8:0]din; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],DOBDO}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(\gic0.gc0.count_d2_reg[13] ), + .ENBWREN(\gc0.count_d1_reg[13] ), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(\gic0.gc0.count_d2_reg[13] ), + .ENBWREN(\gc0.count_d1_reg[13] ), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top + (dout, + wr_clk, + rd_clk, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg, + WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , + ram_full_fb_i_reg_0, + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); + output [31:0]dout; + input wr_clk; + input rd_clk; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [31:0]din; + input [0:0]ram_full_fb_i_reg; + input [0:0]WEA; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; + + wire [13:0]Q; + wire [0:0]WEA; + wire [31:0]din; + wire [31:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; + wire ram_empty_fb_i_reg; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 + (dout, + wr_clk, + rd_clk, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg, + WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , + ram_full_fb_i_reg_0, + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); + output [31:0]dout; + input wr_clk; + input rd_clk; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [31:0]din; + input [0:0]ram_full_fb_i_reg; + input [0:0]WEA; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; + + wire [13:0]Q; + wire [0:0]WEA; + wire [31:0]din; + wire [31:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; + wire ram_empty_fb_i_reg; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth + (dout, + wr_clk, + rd_clk, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg, + WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , + ram_full_fb_i_reg_0, + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); + output [31:0]dout; + input wr_clk; + input rd_clk; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [31:0]din; + input [0:0]ram_full_fb_i_reg; + input [0:0]WEA; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; + + wire [13:0]Q; + wire [0:0]WEA; + wire [31:0]din; + wire [31:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; + wire ram_empty_fb_i_reg; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs + (S, + WR_PNTR_RD, + \gdiff.diff_pntr_pad_reg[12] , + \gdiff.diff_pntr_pad_reg[12]_0 , + \gdiff.diff_pntr_pad_reg[14] , + RD_PNTR_WR, + Q, + \gic0.gc0.count_d2_reg[13] , + rd_clk, + wr_clk); + output [3:0]S; + output [13:0]WR_PNTR_RD; + output [3:0]\gdiff.diff_pntr_pad_reg[12] ; + output [3:0]\gdiff.diff_pntr_pad_reg[12]_0 ; + output [1:0]\gdiff.diff_pntr_pad_reg[14] ; + output [13:0]RD_PNTR_WR; + input [13:0]Q; + input [13:0]\gic0.gc0.count_d2_reg[13] ; + input rd_clk; + input wr_clk; + + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; + wire [3:0]S; + wire [13:0]WR_PNTR_RD; + wire [12:0]bin2gray; + wire [3:0]\gdiff.diff_pntr_pad_reg[12] ; + wire [3:0]\gdiff.diff_pntr_pad_reg[12]_0 ; + wire [1:0]\gdiff.diff_pntr_pad_reg[14] ; + wire [13:0]\gic0.gc0.count_d2_reg[13] ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_13 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ; + wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[10]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[11]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[12]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ; + wire [11:0]gray2bin; + wire p_0_out; + wire [13:0]p_3_out; + wire [13:0]p_4_out; + wire [13:13]p_5_out; + wire [13:13]p_6_out; + wire rd_clk; + wire [13:0]rd_pntr_gc; + wire wr_clk; + wire [13:0]wr_pntr_gc; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \gnxpm_cdc.gsync_stage[1].rd_stg_inst + (.in0(wr_pntr_gc), + .out(p_3_out), + .rd_clk(rd_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_4 \gnxpm_cdc.gsync_stage[1].wr_stg_inst + (.Q(rd_pntr_gc), + .out(p_4_out), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_5 \gnxpm_cdc.gsync_stage[2].rd_stg_inst + (.D({p_0_out,gray2bin}), + .\gnxpm_cdc.wr_pntr_bin_reg[13] (p_5_out), + .out(p_3_out), + .rd_clk(rd_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_6 \gnxpm_cdc.gsync_stage[2].wr_stg_inst + (.D({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_13 }), + .\gnxpm_cdc.rd_pntr_bin_reg[13] (p_6_out), + .out(p_4_out), + .wr_clk(wr_clk)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_13 ), + .Q(RD_PNTR_WR[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), + .Q(RD_PNTR_WR[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), + .Q(RD_PNTR_WR[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), + .Q(RD_PNTR_WR[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[13] + (.C(wr_clk), + .CE(1'b1), + .D(p_6_out), + .Q(RD_PNTR_WR[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ), + .Q(RD_PNTR_WR[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ), + .Q(RD_PNTR_WR[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ), + .Q(RD_PNTR_WR[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ), + .Q(RD_PNTR_WR[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), + .Q(RD_PNTR_WR[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), + .Q(RD_PNTR_WR[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), + .Q(RD_PNTR_WR[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), + .Q(RD_PNTR_WR[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), + .Q(RD_PNTR_WR[9]), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[0]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[10]_i_1 + (.I0(Q[10]), + .I1(Q[11]), + .O(\gnxpm_cdc.rd_pntr_gc[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[11]_i_1 + (.I0(Q[11]), + .I1(Q[12]), + .O(\gnxpm_cdc.rd_pntr_gc[11]_i_1_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[12]_i_1 + (.I0(Q[12]), + .I1(Q[13]), + .O(\gnxpm_cdc.rd_pntr_gc[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[1]_i_1 + (.I0(Q[1]), + .I1(Q[2]), + .O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[2]_i_1 + (.I0(Q[2]), + .I1(Q[3]), + .O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[3]_i_1 + (.I0(Q[3]), + .I1(Q[4]), + .O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[4]_i_1 + (.I0(Q[4]), + .I1(Q[5]), + .O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[5]_i_1 + (.I0(Q[5]), + .I1(Q[6]), + .O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[6]_i_1 + (.I0(Q[6]), + .I1(Q[7]), + .O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[7]_i_1 + (.I0(Q[7]), + .I1(Q[8]), + .O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[8]_i_1 + (.I0(Q[8]), + .I1(Q[9]), + .O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[9]_i_1 + (.I0(Q[9]), + .I1(Q[10]), + .O(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ), + .Q(rd_pntr_gc[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[10]_i_1_n_0 ), + .Q(rd_pntr_gc[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[11]_i_1_n_0 ), + .Q(rd_pntr_gc[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[12]_i_1_n_0 ), + .Q(rd_pntr_gc[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(Q[13]), + .Q(rd_pntr_gc[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ), + .Q(rd_pntr_gc[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ), + .Q(rd_pntr_gc[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ), + .Q(rd_pntr_gc[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ), + .Q(rd_pntr_gc[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ), + .Q(rd_pntr_gc[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ), + .Q(rd_pntr_gc[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ), + .Q(rd_pntr_gc[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ), + .Q(rd_pntr_gc[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ), + .Q(rd_pntr_gc[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[0]), + .Q(WR_PNTR_RD[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[10]), + .Q(WR_PNTR_RD[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[11]), + .Q(WR_PNTR_RD[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(p_0_out), + .Q(WR_PNTR_RD[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(p_5_out), + .Q(WR_PNTR_RD[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[1]), + .Q(WR_PNTR_RD[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[2]), + .Q(WR_PNTR_RD[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[3]), + .Q(WR_PNTR_RD[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[4]), + .Q(WR_PNTR_RD[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[5]), + .Q(WR_PNTR_RD[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[6]), + .Q(WR_PNTR_RD[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[7]), + .Q(WR_PNTR_RD[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[8]), + .Q(WR_PNTR_RD[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[9]), + .Q(WR_PNTR_RD[9]), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[0]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [0]), + .I1(\gic0.gc0.count_d2_reg[13] [1]), + .O(bin2gray[0])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[10]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [10]), + .I1(\gic0.gc0.count_d2_reg[13] [11]), + .O(bin2gray[10])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[11]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [11]), + .I1(\gic0.gc0.count_d2_reg[13] [12]), + .O(bin2gray[11])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[12]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [12]), + .I1(\gic0.gc0.count_d2_reg[13] [13]), + .O(bin2gray[12])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[1]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [1]), + .I1(\gic0.gc0.count_d2_reg[13] [2]), + .O(bin2gray[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[2]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [2]), + .I1(\gic0.gc0.count_d2_reg[13] [3]), + .O(bin2gray[2])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[3]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [3]), + .I1(\gic0.gc0.count_d2_reg[13] [4]), + .O(bin2gray[3])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[4]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [4]), + .I1(\gic0.gc0.count_d2_reg[13] [5]), + .O(bin2gray[4])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[5]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [5]), + .I1(\gic0.gc0.count_d2_reg[13] [6]), + .O(bin2gray[5])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[6]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [6]), + .I1(\gic0.gc0.count_d2_reg[13] [7]), + .O(bin2gray[6])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[7]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [7]), + .I1(\gic0.gc0.count_d2_reg[13] [8]), + .O(bin2gray[7])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[8]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [8]), + .I1(\gic0.gc0.count_d2_reg[13] [9]), + .O(bin2gray[8])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[9]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [9]), + .I1(\gic0.gc0.count_d2_reg[13] [10]), + .O(bin2gray[9])); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[0]), + .Q(wr_pntr_gc[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[10]), + .Q(wr_pntr_gc[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[11]), + .Q(wr_pntr_gc[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[12]), + .Q(wr_pntr_gc[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[13] + (.C(wr_clk), + .CE(1'b1), + .D(\gic0.gc0.count_d2_reg[13] [13]), + .Q(wr_pntr_gc[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[1]), + .Q(wr_pntr_gc[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[2]), + .Q(wr_pntr_gc[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[3]), + .Q(wr_pntr_gc[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[4]), + .Q(wr_pntr_gc[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[5]), + .Q(wr_pntr_gc[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[6]), + .Q(wr_pntr_gc[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[7]), + .Q(wr_pntr_gc[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[8]), + .Q(wr_pntr_gc[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[9]), + .Q(wr_pntr_gc[9]), + .R(1'b0)); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__0_i_1 + (.I0(WR_PNTR_RD[7]), + .I1(Q[7]), + .O(\gdiff.diff_pntr_pad_reg[12] [3])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__0_i_2 + (.I0(WR_PNTR_RD[6]), + .I1(Q[6]), + .O(\gdiff.diff_pntr_pad_reg[12] [2])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__0_i_3 + (.I0(WR_PNTR_RD[5]), + .I1(Q[5]), + .O(\gdiff.diff_pntr_pad_reg[12] [1])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__0_i_4 + (.I0(WR_PNTR_RD[4]), + .I1(Q[4]), + .O(\gdiff.diff_pntr_pad_reg[12] [0])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__1_i_1 + (.I0(WR_PNTR_RD[11]), + .I1(Q[11]), + .O(\gdiff.diff_pntr_pad_reg[12]_0 [3])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__1_i_2 + (.I0(WR_PNTR_RD[10]), + .I1(Q[10]), + .O(\gdiff.diff_pntr_pad_reg[12]_0 [2])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__1_i_3 + (.I0(WR_PNTR_RD[9]), + .I1(Q[9]), + .O(\gdiff.diff_pntr_pad_reg[12]_0 [1])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__1_i_4 + (.I0(WR_PNTR_RD[8]), + .I1(Q[8]), + .O(\gdiff.diff_pntr_pad_reg[12]_0 [0])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__2_i_1 + (.I0(WR_PNTR_RD[13]), + .I1(Q[13]), + .O(\gdiff.diff_pntr_pad_reg[14] [1])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__2_i_2 + (.I0(WR_PNTR_RD[12]), + .I1(Q[12]), + .O(\gdiff.diff_pntr_pad_reg[14] [0])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry_i_2 + (.I0(WR_PNTR_RD[3]), + .I1(Q[3]), + .O(S[3])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry_i_3 + (.I0(WR_PNTR_RD[2]), + .I1(Q[2]), + .O(S[2])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry_i_4 + (.I0(WR_PNTR_RD[1]), + .I1(Q[1]), + .O(S[1])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry_i_5 + (.I0(WR_PNTR_RD[0]), + .I1(Q[0]), + .O(S[0])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare + (ram_full_i_reg, + wr_en, + out, + comp2, + Q, + RD_PNTR_WR); + output ram_full_i_reg; + input wr_en; + input out; + input comp2; + input [13:0]Q; + input [13:0]RD_PNTR_WR; + + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp1; + wire comp2; + wire out; + wire ram_full_i_reg; + wire [6:0]v1_reg; + wire wr_en; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(Q[0]), + .I1(RD_PNTR_WR[0]), + .I2(Q[1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(Q[2]), + .I1(RD_PNTR_WR[2]), + .I2(Q[3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(Q[4]), + .I1(RD_PNTR_WR[4]), + .I2(Q[5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(Q[6]), + .I1(RD_PNTR_WR[6]), + .I2(Q[7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp1,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(Q[8]), + .I1(RD_PNTR_WR[8]), + .I2(Q[9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(Q[10]), + .I1(RD_PNTR_WR[10]), + .I2(Q[11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(Q[12]), + .I1(RD_PNTR_WR[12]), + .I2(Q[13]), + .I3(RD_PNTR_WR[13]), + .O(v1_reg[6])); + LUT4 #( + .INIT(16'hAEAA)) + ram_full_i_i_1 + (.I0(comp1), + .I1(wr_en), + .I2(out), + .I3(comp2), + .O(ram_full_i_reg)); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 + (comp2, + D, + RD_PNTR_WR); + output comp2; + input [13:0]D; + input [13:0]RD_PNTR_WR; + + wire [13:0]D; + wire [13:0]RD_PNTR_WR; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp2; + wire [6:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(D[0]), + .I1(RD_PNTR_WR[0]), + .I2(D[1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(D[2]), + .I1(RD_PNTR_WR[2]), + .I2(D[3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(D[4]), + .I1(RD_PNTR_WR[4]), + .I2(D[5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(D[6]), + .I1(RD_PNTR_WR[6]), + .I2(D[7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp2,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(D[8]), + .I1(RD_PNTR_WR[8]), + .I2(D[9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(D[10]), + .I1(RD_PNTR_WR[10]), + .I2(D[11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(D[12]), + .I1(RD_PNTR_WR[12]), + .I2(D[13]), + .I3(RD_PNTR_WR[13]), + .O(v1_reg[6])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 + (comp0, + WR_PNTR_RD, + Q); + output comp0; + input [13:0]WR_PNTR_RD; + input [13:0]Q; + + wire [13:0]Q; + wire [13:0]WR_PNTR_RD; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp0; + wire [6:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(Q[0]), + .I2(WR_PNTR_RD[1]), + .I3(Q[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(Q[2]), + .I2(WR_PNTR_RD[3]), + .I3(Q[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(Q[4]), + .I2(WR_PNTR_RD[5]), + .I3(Q[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(Q[6]), + .I2(WR_PNTR_RD[7]), + .I3(Q[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp0,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(Q[8]), + .I2(WR_PNTR_RD[9]), + .I3(Q[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(Q[10]), + .I2(WR_PNTR_RD[11]), + .I3(Q[11]), + .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(WR_PNTR_RD[12]), + .I1(Q[12]), + .I2(WR_PNTR_RD[13]), + .I3(Q[13]), + .O(v1_reg[6])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 + (comp1, + WR_PNTR_RD, + D); + output comp1; + input [13:0]WR_PNTR_RD; + input [13:0]D; + + wire [13:0]D; + wire [13:0]WR_PNTR_RD; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp1; + wire [6:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(D[0]), + .I2(WR_PNTR_RD[1]), + .I3(D[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(D[2]), + .I2(WR_PNTR_RD[3]), + .I3(D[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(D[4]), + .I2(WR_PNTR_RD[5]), + .I3(D[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(D[6]), + .I2(WR_PNTR_RD[7]), + .I3(D[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp1,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(D[8]), + .I2(WR_PNTR_RD[9]), + .I3(D[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(D[10]), + .I2(WR_PNTR_RD[11]), + .I3(D[11]), + .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(WR_PNTR_RD[12]), + .I1(D[12]), + .I2(WR_PNTR_RD[13]), + .I3(D[13]), + .O(v1_reg[6])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo + (dout, + empty, + full, + prog_empty, + wr_en, + rd_en, + wr_clk, + rd_clk, + din); + output [31:0]dout; + output empty; + output full; + output prog_empty; + input wr_en; + input rd_en; + input wr_clk; + input rd_clk; + input [31:0]din; + + wire [31:0]din; + wire [31:0]dout; + wire empty; + wire full; + wire \gntv_or_sync_fifo.gcx.clkx_n_0 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_1 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_18 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_19 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_2 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_20 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_21 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_22 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_23 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_24 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_25 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_26 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_27 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_3 ; + wire \gntv_or_sync_fifo.gl0.rd_n_3 ; + wire \gntv_or_sync_fifo.gl0.wr_n_1 ; + wire \gntv_or_sync_fifo.gl0.wr_n_17 ; + wire \gntv_or_sync_fifo.gl0.wr_n_18 ; + wire \gntv_or_sync_fifo.gl0.wr_n_19 ; + wire \gntv_or_sync_fifo.gl0.wr_n_2 ; + wire [13:0]p_0_out_0; + wire [13:0]p_12_out; + wire [13:0]p_22_out; + wire [13:0]p_23_out; + wire p_2_out; + wire prog_empty; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx + (.Q(p_0_out_0), + .RD_PNTR_WR(p_23_out), + .S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 ,\gntv_or_sync_fifo.gcx.clkx_n_2 ,\gntv_or_sync_fifo.gcx.clkx_n_3 }), + .WR_PNTR_RD(p_22_out), + .\gdiff.diff_pntr_pad_reg[12] ({\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 ,\gntv_or_sync_fifo.gcx.clkx_n_20 ,\gntv_or_sync_fifo.gcx.clkx_n_21 }), + .\gdiff.diff_pntr_pad_reg[12]_0 ({\gntv_or_sync_fifo.gcx.clkx_n_22 ,\gntv_or_sync_fifo.gcx.clkx_n_23 ,\gntv_or_sync_fifo.gcx.clkx_n_24 ,\gntv_or_sync_fifo.gcx.clkx_n_25 }), + .\gdiff.diff_pntr_pad_reg[14] ({\gntv_or_sync_fifo.gcx.clkx_n_26 ,\gntv_or_sync_fifo.gcx.clkx_n_27 }), + .\gic0.gc0.count_d2_reg[13] (p_12_out), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .Q(p_0_out_0), + .S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 ,\gntv_or_sync_fifo.gcx.clkx_n_2 ,\gntv_or_sync_fifo.gcx.clkx_n_3 }), + .WR_PNTR_RD(p_22_out), + .empty(empty), + .\gnxpm_cdc.wr_pntr_bin_reg[11] ({\gntv_or_sync_fifo.gcx.clkx_n_22 ,\gntv_or_sync_fifo.gcx.clkx_n_23 ,\gntv_or_sync_fifo.gcx.clkx_n_24 ,\gntv_or_sync_fifo.gcx.clkx_n_25 }), + .\gnxpm_cdc.wr_pntr_bin_reg[13] ({\gntv_or_sync_fifo.gcx.clkx_n_26 ,\gntv_or_sync_fifo.gcx.clkx_n_27 }), + .\gnxpm_cdc.wr_pntr_bin_reg[7] ({\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 ,\gntv_or_sync_fifo.gcx.clkx_n_20 ,\gntv_or_sync_fifo.gcx.clkx_n_21 }), + .out(p_2_out), + .prog_empty(prog_empty), + .rd_clk(rd_clk), + .rd_en(rd_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.wr_n_2 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.wr_n_18 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\gntv_or_sync_fifo.gl0.wr_n_19 ), + .Q(p_12_out), + .RD_PNTR_WR(p_23_out), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_17 ), + .full(full), + .out(\gntv_or_sync_fifo.gl0.wr_n_1 ), + .wr_clk(wr_clk), + .wr_en(wr_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem + (.Q(p_12_out), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_17 ), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (p_0_out_0), + .\gc0.count_d1_reg[13]_0 (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .\gic0.gc0.count_d2_reg[13] (\gntv_or_sync_fifo.gl0.wr_n_2 ), + .out(\gntv_or_sync_fifo.gl0.wr_n_1 ), + .ram_empty_fb_i_reg(p_2_out), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_18 ), + .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_19 ), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top + (dout, + empty, + full, + prog_empty, + wr_en, + rd_en, + wr_clk, + rd_clk, + din); + output [31:0]dout; + output empty; + output full; + output prog_empty; + input wr_en; + input rd_en; + input wr_clk; + input rd_clk; + input [31:0]din; + + wire [31:0]din; + wire [31:0]dout; + wire empty; + wire full; + wire prog_empty; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf + (.din(din), + .dout(dout), + .empty(empty), + .full(full), + .prog_empty(prog_empty), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) +(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) +(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) +(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) +(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) +(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) +(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) +(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) +(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) +(* C_DATA_COUNT_WIDTH = "14" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *) +(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) +(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) +(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *) +(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) +(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) +(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) +(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *) +(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) +(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) +(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) +(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) +(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) +(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) +(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) +(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) +(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) +(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) +(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) +(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) +(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "0" *) (* C_HAS_SLAVE_CE = "0" *) +(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) +(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) +(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) +(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) +(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) +(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) +(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) +(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "8kx4" *) +(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) +(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "1023" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "1024" *) (* C_PROG_EMPTY_TYPE = "1" *) +(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) +(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL = "16381" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "16380" *) (* C_PROG_FULL_TYPE = "0" *) +(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) +(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) +(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "14" *) +(* C_RD_DEPTH = "16384" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "14" *) +(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) +(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) +(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) +(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) +(* C_USE_DOUT_RST = "0" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) +(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) +(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) +(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) +(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) +(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "14" *) +(* C_WR_DEPTH = "16384" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) +(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) +(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "14" *) +(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) +(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) +(* C_WR_RESPONSE_LATENCY = "1" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 + (backup, + backup_marker, + clk, + rst, + srst, + wr_clk, + wr_rst, + rd_clk, + rd_rst, + din, + wr_en, + rd_en, + prog_empty_thresh, + prog_empty_thresh_assert, + prog_empty_thresh_negate, + prog_full_thresh, + prog_full_thresh_assert, + prog_full_thresh_negate, + int_clk, + injectdbiterr, + injectsbiterr, + sleep, + dout, + full, + almost_full, + wr_ack, + overflow, + empty, + almost_empty, + valid, + underflow, + data_count, + rd_data_count, + wr_data_count, + prog_full, + prog_empty, + sbiterr, + dbiterr, + wr_rst_busy, + rd_rst_busy, + m_aclk, + s_aclk, + s_aresetn, + m_aclk_en, + s_aclk_en, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awregion, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + m_axi_awregion, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arregion, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arqos, + m_axi_arregion, + m_axi_aruser, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_ruser, + m_axi_rvalid, + m_axi_rready, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tstrb, + s_axis_tkeep, + s_axis_tlast, + s_axis_tid, + s_axis_tdest, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tstrb, + m_axis_tkeep, + m_axis_tlast, + m_axis_tid, + m_axis_tdest, + m_axis_tuser, + axi_aw_injectsbiterr, + axi_aw_injectdbiterr, + axi_aw_prog_full_thresh, + axi_aw_prog_empty_thresh, + axi_aw_data_count, + axi_aw_wr_data_count, + axi_aw_rd_data_count, + axi_aw_sbiterr, + axi_aw_dbiterr, + axi_aw_overflow, + axi_aw_underflow, + axi_aw_prog_full, + axi_aw_prog_empty, + axi_w_injectsbiterr, + axi_w_injectdbiterr, + axi_w_prog_full_thresh, + axi_w_prog_empty_thresh, + axi_w_data_count, + axi_w_wr_data_count, + axi_w_rd_data_count, + axi_w_sbiterr, + axi_w_dbiterr, + axi_w_overflow, + axi_w_underflow, + axi_w_prog_full, + axi_w_prog_empty, + axi_b_injectsbiterr, + axi_b_injectdbiterr, + axi_b_prog_full_thresh, + axi_b_prog_empty_thresh, + axi_b_data_count, + axi_b_wr_data_count, + axi_b_rd_data_count, + axi_b_sbiterr, + axi_b_dbiterr, + axi_b_overflow, + axi_b_underflow, + axi_b_prog_full, + axi_b_prog_empty, + axi_ar_injectsbiterr, + axi_ar_injectdbiterr, + axi_ar_prog_full_thresh, + axi_ar_prog_empty_thresh, + axi_ar_data_count, + axi_ar_wr_data_count, + axi_ar_rd_data_count, + axi_ar_sbiterr, + axi_ar_dbiterr, + axi_ar_overflow, + axi_ar_underflow, + axi_ar_prog_full, + axi_ar_prog_empty, + axi_r_injectsbiterr, + axi_r_injectdbiterr, + axi_r_prog_full_thresh, + axi_r_prog_empty_thresh, + axi_r_data_count, + axi_r_wr_data_count, + axi_r_rd_data_count, + axi_r_sbiterr, + axi_r_dbiterr, + axi_r_overflow, + axi_r_underflow, + axi_r_prog_full, + axi_r_prog_empty, + axis_injectsbiterr, + axis_injectdbiterr, + axis_prog_full_thresh, + axis_prog_empty_thresh, + axis_data_count, + axis_wr_data_count, + axis_rd_data_count, + axis_sbiterr, + axis_dbiterr, + axis_overflow, + axis_underflow, + axis_prog_full, + axis_prog_empty); + input backup; + input backup_marker; + input clk; + input rst; + input srst; + input wr_clk; + input wr_rst; + input rd_clk; + input rd_rst; + input [31:0]din; + input wr_en; + input rd_en; + input [13:0]prog_empty_thresh; + input [13:0]prog_empty_thresh_assert; + input [13:0]prog_empty_thresh_negate; + input [13:0]prog_full_thresh; + input [13:0]prog_full_thresh_assert; + input [13:0]prog_full_thresh_negate; + input int_clk; + input injectdbiterr; + input injectsbiterr; + input sleep; + output [31:0]dout; + output full; + output almost_full; + output wr_ack; + output overflow; + output empty; + output almost_empty; + output valid; + output underflow; + output [13:0]data_count; + output [13:0]rd_data_count; + output [13:0]wr_data_count; + output prog_full; + output prog_empty; + output sbiterr; + output dbiterr; + output wr_rst_busy; + output rd_rst_busy; + input m_aclk; + input s_aclk; + input s_aresetn; + input m_aclk_en; + input s_aclk_en; + input [0:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [0:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awqos; + input [3:0]s_axi_awregion; + input [0:0]s_axi_awuser; + input s_axi_awvalid; + output s_axi_awready; + input [0:0]s_axi_wid; + input [63:0]s_axi_wdata; + input [7:0]s_axi_wstrb; + input s_axi_wlast; + input [0:0]s_axi_wuser; + input s_axi_wvalid; + output s_axi_wready; + output [0:0]s_axi_bid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_buser; + output s_axi_bvalid; + input s_axi_bready; + output [0:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [7:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [0:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awqos; + output [3:0]m_axi_awregion; + output [0:0]m_axi_awuser; + output m_axi_awvalid; + input m_axi_awready; + output [0:0]m_axi_wid; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output m_axi_wlast; + output [0:0]m_axi_wuser; + output m_axi_wvalid; + input m_axi_wready; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_buser; + input m_axi_bvalid; + output m_axi_bready; + input [0:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [0:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + input [3:0]s_axi_arregion; + input [0:0]s_axi_aruser; + input s_axi_arvalid; + output s_axi_arready; + output [0:0]s_axi_rid; + output [63:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output [0:0]s_axi_ruser; + output s_axi_rvalid; + input s_axi_rready; + output [0:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [7:0]m_axi_arlen; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [0:0]m_axi_arlock; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arqos; + output [3:0]m_axi_arregion; + output [0:0]m_axi_aruser; + output m_axi_arvalid; + input m_axi_arready; + input [0:0]m_axi_rid; + input [63:0]m_axi_rdata; + input [1:0]m_axi_rresp; + input m_axi_rlast; + input [0:0]m_axi_ruser; + input m_axi_rvalid; + output m_axi_rready; + input s_axis_tvalid; + output s_axis_tready; + input [7:0]s_axis_tdata; + input [0:0]s_axis_tstrb; + input [0:0]s_axis_tkeep; + input s_axis_tlast; + input [0:0]s_axis_tid; + input [0:0]s_axis_tdest; + input [3:0]s_axis_tuser; + output m_axis_tvalid; + input m_axis_tready; + output [7:0]m_axis_tdata; + output [0:0]m_axis_tstrb; + output [0:0]m_axis_tkeep; + output m_axis_tlast; + output [0:0]m_axis_tid; + output [0:0]m_axis_tdest; + output [3:0]m_axis_tuser; + input axi_aw_injectsbiterr; + input axi_aw_injectdbiterr; + input [3:0]axi_aw_prog_full_thresh; + input [3:0]axi_aw_prog_empty_thresh; + output [4:0]axi_aw_data_count; + output [4:0]axi_aw_wr_data_count; + output [4:0]axi_aw_rd_data_count; + output axi_aw_sbiterr; + output axi_aw_dbiterr; + output axi_aw_overflow; + output axi_aw_underflow; + output axi_aw_prog_full; + output axi_aw_prog_empty; + input axi_w_injectsbiterr; + input axi_w_injectdbiterr; + input [9:0]axi_w_prog_full_thresh; + input [9:0]axi_w_prog_empty_thresh; + output [10:0]axi_w_data_count; + output [10:0]axi_w_wr_data_count; + output [10:0]axi_w_rd_data_count; + output axi_w_sbiterr; + output axi_w_dbiterr; + output axi_w_overflow; + output axi_w_underflow; + output axi_w_prog_full; + output axi_w_prog_empty; + input axi_b_injectsbiterr; + input axi_b_injectdbiterr; + input [3:0]axi_b_prog_full_thresh; + input [3:0]axi_b_prog_empty_thresh; + output [4:0]axi_b_data_count; + output [4:0]axi_b_wr_data_count; + output [4:0]axi_b_rd_data_count; + output axi_b_sbiterr; + output axi_b_dbiterr; + output axi_b_overflow; + output axi_b_underflow; + output axi_b_prog_full; + output axi_b_prog_empty; + input axi_ar_injectsbiterr; + input axi_ar_injectdbiterr; + input [3:0]axi_ar_prog_full_thresh; + input [3:0]axi_ar_prog_empty_thresh; + output [4:0]axi_ar_data_count; + output [4:0]axi_ar_wr_data_count; + output [4:0]axi_ar_rd_data_count; + output axi_ar_sbiterr; + output axi_ar_dbiterr; + output axi_ar_overflow; + output axi_ar_underflow; + output axi_ar_prog_full; + output axi_ar_prog_empty; + input axi_r_injectsbiterr; + input axi_r_injectdbiterr; + input [9:0]axi_r_prog_full_thresh; + input [9:0]axi_r_prog_empty_thresh; + output [10:0]axi_r_data_count; + output [10:0]axi_r_wr_data_count; + output [10:0]axi_r_rd_data_count; + output axi_r_sbiterr; + output axi_r_dbiterr; + output axi_r_overflow; + output axi_r_underflow; + output axi_r_prog_full; + output axi_r_prog_empty; + input axis_injectsbiterr; + input axis_injectdbiterr; + input [9:0]axis_prog_full_thresh; + input [9:0]axis_prog_empty_thresh; + output [10:0]axis_data_count; + output [10:0]axis_wr_data_count; + output [10:0]axis_rd_data_count; + output axis_sbiterr; + output axis_dbiterr; + output axis_overflow; + output axis_underflow; + output axis_prog_full; + output axis_prog_empty; + + wire \ ; + wire \ ; + wire [31:0]din; + wire [31:0]dout; + wire empty; + wire full; + wire prog_empty; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + assign almost_empty = \ ; + assign almost_full = \ ; + assign axi_ar_data_count[4] = \ ; + assign axi_ar_data_count[3] = \ ; + assign axi_ar_data_count[2] = \ ; + assign axi_ar_data_count[1] = \ ; + assign axi_ar_data_count[0] = \ ; + assign axi_ar_dbiterr = \ ; + assign axi_ar_overflow = \ ; + assign axi_ar_prog_empty = \ ; + assign axi_ar_prog_full = \ ; + assign axi_ar_rd_data_count[4] = \ ; + assign axi_ar_rd_data_count[3] = \ ; + assign axi_ar_rd_data_count[2] = \ ; + assign axi_ar_rd_data_count[1] = \ ; + assign axi_ar_rd_data_count[0] = \ ; + assign axi_ar_sbiterr = \ ; + assign axi_ar_underflow = \ ; + assign axi_ar_wr_data_count[4] = \ ; + assign axi_ar_wr_data_count[3] = \ ; + assign axi_ar_wr_data_count[2] = \ ; + assign axi_ar_wr_data_count[1] = \ ; + assign axi_ar_wr_data_count[0] = \ ; + assign axi_aw_data_count[4] = \ ; + assign axi_aw_data_count[3] = \ ; + assign axi_aw_data_count[2] = \ ; + assign axi_aw_data_count[1] = \ ; + assign axi_aw_data_count[0] = \ ; + assign axi_aw_dbiterr = \ ; + assign axi_aw_overflow = \ ; + assign axi_aw_prog_empty = \ ; + assign axi_aw_prog_full = \ ; + assign axi_aw_rd_data_count[4] = \ ; + assign axi_aw_rd_data_count[3] = \ ; + assign axi_aw_rd_data_count[2] = \ ; + assign axi_aw_rd_data_count[1] = \ ; + assign axi_aw_rd_data_count[0] = \ ; + assign axi_aw_sbiterr = \ ; + assign axi_aw_underflow = \ ; + assign axi_aw_wr_data_count[4] = \ ; + assign axi_aw_wr_data_count[3] = \ ; + assign axi_aw_wr_data_count[2] = \ ; + assign axi_aw_wr_data_count[1] = \ ; + assign axi_aw_wr_data_count[0] = \ ; + assign axi_b_data_count[4] = \ ; + assign axi_b_data_count[3] = \ ; + assign axi_b_data_count[2] = \ ; + assign axi_b_data_count[1] = \ ; + assign axi_b_data_count[0] = \ ; + assign axi_b_dbiterr = \ ; + assign axi_b_overflow = \ ; + assign axi_b_prog_empty = \ ; + assign axi_b_prog_full = \ ; + assign axi_b_rd_data_count[4] = \ ; + assign axi_b_rd_data_count[3] = \ ; + assign axi_b_rd_data_count[2] = \ ; + assign axi_b_rd_data_count[1] = \ ; + assign axi_b_rd_data_count[0] = \ ; + assign axi_b_sbiterr = \ ; + assign axi_b_underflow = \ ; + assign axi_b_wr_data_count[4] = \ ; + assign axi_b_wr_data_count[3] = \ ; + assign axi_b_wr_data_count[2] = \ ; + assign axi_b_wr_data_count[1] = \ ; + assign axi_b_wr_data_count[0] = \ ; + assign axi_r_data_count[10] = \ ; + assign axi_r_data_count[9] = \ ; + assign axi_r_data_count[8] = \ ; + assign axi_r_data_count[7] = \ ; + assign axi_r_data_count[6] = \ ; + assign axi_r_data_count[5] = \ ; + assign axi_r_data_count[4] = \ ; + assign axi_r_data_count[3] = \ ; + assign axi_r_data_count[2] = \ ; + assign axi_r_data_count[1] = \ ; + assign axi_r_data_count[0] = \ ; + assign axi_r_dbiterr = \ ; + assign axi_r_overflow = \ ; + assign axi_r_prog_empty = \ ; + assign axi_r_prog_full = \ ; + assign axi_r_rd_data_count[10] = \ ; + assign axi_r_rd_data_count[9] = \ ; + assign axi_r_rd_data_count[8] = \ ; + assign axi_r_rd_data_count[7] = \ ; + assign axi_r_rd_data_count[6] = \ ; + assign axi_r_rd_data_count[5] = \ ; + assign axi_r_rd_data_count[4] = \ ; + assign axi_r_rd_data_count[3] = \ ; + assign axi_r_rd_data_count[2] = \ ; + assign axi_r_rd_data_count[1] = \ ; + assign axi_r_rd_data_count[0] = \ ; + assign axi_r_sbiterr = \ ; + assign axi_r_underflow = \ ; + assign axi_r_wr_data_count[10] = \ ; + assign axi_r_wr_data_count[9] = \ ; + assign axi_r_wr_data_count[8] = \ ; + assign axi_r_wr_data_count[7] = \ ; + assign axi_r_wr_data_count[6] = \ ; + assign axi_r_wr_data_count[5] = \ ; + assign axi_r_wr_data_count[4] = \ ; + assign axi_r_wr_data_count[3] = \ ; + assign axi_r_wr_data_count[2] = \ ; + assign axi_r_wr_data_count[1] = \ ; + assign axi_r_wr_data_count[0] = \ ; + assign axi_w_data_count[10] = \ ; + assign axi_w_data_count[9] = \ ; + assign axi_w_data_count[8] = \ ; + assign axi_w_data_count[7] = \ ; + assign axi_w_data_count[6] = \ ; + assign axi_w_data_count[5] = \ ; + assign axi_w_data_count[4] = \ ; + assign axi_w_data_count[3] = \ ; + assign axi_w_data_count[2] = \ ; + assign axi_w_data_count[1] = \ ; + assign axi_w_data_count[0] = \ ; + assign axi_w_dbiterr = \ ; + assign axi_w_overflow = \ ; + assign axi_w_prog_empty = \ ; + assign axi_w_prog_full = \ ; + assign axi_w_rd_data_count[10] = \ ; + assign axi_w_rd_data_count[9] = \ ; + assign axi_w_rd_data_count[8] = \ ; + assign axi_w_rd_data_count[7] = \ ; + assign axi_w_rd_data_count[6] = \ ; + assign axi_w_rd_data_count[5] = \ ; + assign axi_w_rd_data_count[4] = \ ; + assign axi_w_rd_data_count[3] = \ ; + assign axi_w_rd_data_count[2] = \ ; + assign axi_w_rd_data_count[1] = \ ; + assign axi_w_rd_data_count[0] = \ ; + assign axi_w_sbiterr = \ ; + assign axi_w_underflow = \ ; + assign axi_w_wr_data_count[10] = \ ; + assign axi_w_wr_data_count[9] = \ ; + assign axi_w_wr_data_count[8] = \ ; + assign axi_w_wr_data_count[7] = \ ; + assign axi_w_wr_data_count[6] = \ ; + assign axi_w_wr_data_count[5] = \ ; + assign axi_w_wr_data_count[4] = \ ; + assign axi_w_wr_data_count[3] = \ ; + assign axi_w_wr_data_count[2] = \ ; + assign axi_w_wr_data_count[1] = \ ; + assign axi_w_wr_data_count[0] = \ ; + assign axis_data_count[10] = \ ; + assign axis_data_count[9] = \ ; + assign axis_data_count[8] = \ ; + assign axis_data_count[7] = \ ; + assign axis_data_count[6] = \ ; + assign axis_data_count[5] = \ ; + assign axis_data_count[4] = \ ; + assign axis_data_count[3] = \ ; + assign axis_data_count[2] = \ ; + assign axis_data_count[1] = \ ; + assign axis_data_count[0] = \ ; + assign axis_dbiterr = \ ; + assign axis_overflow = \ ; + assign axis_prog_empty = \ ; + assign axis_prog_full = \ ; + assign axis_rd_data_count[10] = \ ; + assign axis_rd_data_count[9] = \ ; + assign axis_rd_data_count[8] = \ ; + assign axis_rd_data_count[7] = \ ; + assign axis_rd_data_count[6] = \ ; + assign axis_rd_data_count[5] = \ ; + assign axis_rd_data_count[4] = \ ; + assign axis_rd_data_count[3] = \ ; + assign axis_rd_data_count[2] = \ ; + assign axis_rd_data_count[1] = \ ; + assign axis_rd_data_count[0] = \ ; + assign axis_sbiterr = \ ; + assign axis_underflow = \ ; + assign axis_wr_data_count[10] = \ ; + assign axis_wr_data_count[9] = \ ; + assign axis_wr_data_count[8] = \ ; + assign axis_wr_data_count[7] = \ ; + assign axis_wr_data_count[6] = \ ; + assign axis_wr_data_count[5] = \ ; + assign axis_wr_data_count[4] = \ ; + assign axis_wr_data_count[3] = \ ; + assign axis_wr_data_count[2] = \ ; + assign axis_wr_data_count[1] = \ ; + assign axis_wr_data_count[0] = \ ; + assign data_count[13] = \ ; + assign data_count[12] = \ ; + assign data_count[11] = \ ; + assign data_count[10] = \ ; + assign data_count[9] = \ ; + assign data_count[8] = \ ; + assign data_count[7] = \ ; + assign data_count[6] = \ ; + assign data_count[5] = \ ; + assign data_count[4] = \ ; + assign data_count[3] = \ ; + assign data_count[2] = \ ; + assign data_count[1] = \ ; + assign data_count[0] = \ ; + assign dbiterr = \ ; + assign m_axi_araddr[31] = \ ; + assign m_axi_araddr[30] = \ ; + assign m_axi_araddr[29] = \ ; + assign m_axi_araddr[28] = \ ; + assign m_axi_araddr[27] = \ ; + assign m_axi_araddr[26] = \ ; + assign m_axi_araddr[25] = \ ; + assign m_axi_araddr[24] = \ ; + assign m_axi_araddr[23] = \ ; + assign m_axi_araddr[22] = \ ; + assign m_axi_araddr[21] = \ ; + assign m_axi_araddr[20] = \ ; + assign m_axi_araddr[19] = \ ; + assign m_axi_araddr[18] = \ ; + assign m_axi_araddr[17] = \ ; + assign m_axi_araddr[16] = \ ; + assign m_axi_araddr[15] = \ ; + assign m_axi_araddr[14] = \ ; + assign m_axi_araddr[13] = \ ; + assign m_axi_araddr[12] = \ ; + assign m_axi_araddr[11] = \ ; + assign m_axi_araddr[10] = \ ; + assign m_axi_araddr[9] = \ ; + assign m_axi_araddr[8] = \ ; + assign m_axi_araddr[7] = \ ; + assign m_axi_araddr[6] = \ ; + assign m_axi_araddr[5] = \ ; + assign m_axi_araddr[4] = \ ; + assign m_axi_araddr[3] = \ ; + assign m_axi_araddr[2] = \ ; + assign m_axi_araddr[1] = \ ; + assign m_axi_araddr[0] = \ ; + assign m_axi_arburst[1] = \ ; + assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[3] = \ ; + assign m_axi_arcache[2] = \ ; + assign m_axi_arcache[1] = \ ; + assign m_axi_arcache[0] = \ ; + assign m_axi_arid[0] = \ ; + assign m_axi_arlen[7] = \ ; + assign m_axi_arlen[6] = \ ; + assign m_axi_arlen[5] = \ ; + assign m_axi_arlen[4] = \ ; + assign m_axi_arlen[3] = \ ; + assign m_axi_arlen[2] = \ ; + assign m_axi_arlen[1] = \ ; + assign m_axi_arlen[0] = \ ; + assign m_axi_arlock[0] = \ ; + assign m_axi_arprot[2] = \ ; + assign m_axi_arprot[1] = \ ; + assign m_axi_arprot[0] = \ ; + assign m_axi_arqos[3] = \ ; + assign m_axi_arqos[2] = \ ; + assign m_axi_arqos[1] = \ ; + assign m_axi_arqos[0] = \ ; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[2] = \ ; + assign m_axi_arsize[1] = \ ; + assign m_axi_arsize[0] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_arvalid = \ ; + assign m_axi_awaddr[31] = \ ; + assign m_axi_awaddr[30] = \ ; + assign m_axi_awaddr[29] = \ ; + assign m_axi_awaddr[28] = \ ; + assign m_axi_awaddr[27] = \ ; + assign m_axi_awaddr[26] = \ ; + assign m_axi_awaddr[25] = \ ; + assign m_axi_awaddr[24] = \ ; + assign m_axi_awaddr[23] = \ ; + assign m_axi_awaddr[22] = \ ; + assign m_axi_awaddr[21] = \ ; + assign m_axi_awaddr[20] = \ ; + assign m_axi_awaddr[19] = \ ; + assign m_axi_awaddr[18] = \ ; + assign m_axi_awaddr[17] = \ ; + assign m_axi_awaddr[16] = \ ; + assign m_axi_awaddr[15] = \ ; + assign m_axi_awaddr[14] = \ ; + assign m_axi_awaddr[13] = \ ; + assign m_axi_awaddr[12] = \ ; + assign m_axi_awaddr[11] = \ ; + assign m_axi_awaddr[10] = \ ; + assign m_axi_awaddr[9] = \ ; + assign m_axi_awaddr[8] = \ ; + assign m_axi_awaddr[7] = \ ; + assign m_axi_awaddr[6] = \ ; + assign m_axi_awaddr[5] = \ ; + assign m_axi_awaddr[4] = \ ; + assign m_axi_awaddr[3] = \ ; + assign m_axi_awaddr[2] = \ ; + assign m_axi_awaddr[1] = \ ; + assign m_axi_awaddr[0] = \ ; + assign m_axi_awburst[1] = \ ; + assign m_axi_awburst[0] = \ ; + assign m_axi_awcache[3] = \ ; + assign m_axi_awcache[2] = \ ; + assign m_axi_awcache[1] = \ ; + assign m_axi_awcache[0] = \ ; + assign m_axi_awid[0] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; + assign m_axi_awlen[3] = \ ; + assign m_axi_awlen[2] = \ ; + assign m_axi_awlen[1] = \ ; + assign m_axi_awlen[0] = \ ; + assign m_axi_awlock[0] = \ ; + assign m_axi_awprot[2] = \ ; + assign m_axi_awprot[1] = \ ; + assign m_axi_awprot[0] = \ ; + assign m_axi_awqos[3] = \ ; + assign m_axi_awqos[2] = \ ; + assign m_axi_awqos[1] = \ ; + assign m_axi_awqos[0] = \ ; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awsize[2] = \ ; + assign m_axi_awsize[1] = \ ; + assign m_axi_awsize[0] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_awvalid = \ ; + assign m_axi_bready = \ ; + assign m_axi_rready = \ ; + assign m_axi_wdata[63] = \ ; + assign m_axi_wdata[62] = \ ; + assign m_axi_wdata[61] = \ ; + assign m_axi_wdata[60] = \ ; + assign m_axi_wdata[59] = \ ; + assign m_axi_wdata[58] = \ ; + assign m_axi_wdata[57] = \ ; + assign m_axi_wdata[56] = \ ; + assign m_axi_wdata[55] = \ ; + assign m_axi_wdata[54] = \ ; + assign m_axi_wdata[53] = \ ; + assign m_axi_wdata[52] = \ ; + assign m_axi_wdata[51] = \ ; + assign m_axi_wdata[50] = \ ; + assign m_axi_wdata[49] = \ ; + assign m_axi_wdata[48] = \ ; + assign m_axi_wdata[47] = \ ; + assign m_axi_wdata[46] = \ ; + assign m_axi_wdata[45] = \ ; + assign m_axi_wdata[44] = \ ; + assign m_axi_wdata[43] = \ ; + assign m_axi_wdata[42] = \ ; + assign m_axi_wdata[41] = \ ; + assign m_axi_wdata[40] = \ ; + assign m_axi_wdata[39] = \ ; + assign m_axi_wdata[38] = \ ; + assign m_axi_wdata[37] = \ ; + assign m_axi_wdata[36] = \ ; + assign m_axi_wdata[35] = \ ; + assign m_axi_wdata[34] = \ ; + assign m_axi_wdata[33] = \ ; + assign m_axi_wdata[32] = \ ; + assign m_axi_wdata[31] = \ ; + assign m_axi_wdata[30] = \ ; + assign m_axi_wdata[29] = \ ; + assign m_axi_wdata[28] = \ ; + assign m_axi_wdata[27] = \ ; + assign m_axi_wdata[26] = \ ; + assign m_axi_wdata[25] = \ ; + assign m_axi_wdata[24] = \ ; + assign m_axi_wdata[23] = \ ; + assign m_axi_wdata[22] = \ ; + assign m_axi_wdata[21] = \ ; + assign m_axi_wdata[20] = \ ; + assign m_axi_wdata[19] = \ ; + assign m_axi_wdata[18] = \ ; + assign m_axi_wdata[17] = \ ; + assign m_axi_wdata[16] = \ ; + assign m_axi_wdata[15] = \ ; + assign m_axi_wdata[14] = \ ; + assign m_axi_wdata[13] = \ ; + assign m_axi_wdata[12] = \ ; + assign m_axi_wdata[11] = \ ; + assign m_axi_wdata[10] = \ ; + assign m_axi_wdata[9] = \ ; + assign m_axi_wdata[8] = \ ; + assign m_axi_wdata[7] = \ ; + assign m_axi_wdata[6] = \ ; + assign m_axi_wdata[5] = \ ; + assign m_axi_wdata[4] = \ ; + assign m_axi_wdata[3] = \ ; + assign m_axi_wdata[2] = \ ; + assign m_axi_wdata[1] = \ ; + assign m_axi_wdata[0] = \ ; + assign m_axi_wid[0] = \ ; + assign m_axi_wlast = \ ; + assign m_axi_wstrb[7] = \ ; + assign m_axi_wstrb[6] = \ ; + assign m_axi_wstrb[5] = \ ; + assign m_axi_wstrb[4] = \ ; + assign m_axi_wstrb[3] = \ ; + assign m_axi_wstrb[2] = \ ; + assign m_axi_wstrb[1] = \ ; + assign m_axi_wstrb[0] = \ ; + assign m_axi_wuser[0] = \ ; + assign m_axi_wvalid = \ ; + assign m_axis_tdata[7] = \ ; + assign m_axis_tdata[6] = \ ; + assign m_axis_tdata[5] = \ ; + assign m_axis_tdata[4] = \ ; + assign m_axis_tdata[3] = \ ; + assign m_axis_tdata[2] = \ ; + assign m_axis_tdata[1] = \ ; + assign m_axis_tdata[0] = \ ; + assign m_axis_tdest[0] = \ ; + assign m_axis_tid[0] = \ ; + assign m_axis_tkeep[0] = \ ; + assign m_axis_tlast = \ ; + assign m_axis_tstrb[0] = \ ; + assign m_axis_tuser[3] = \ ; + assign m_axis_tuser[2] = \ ; + assign m_axis_tuser[1] = \ ; + assign m_axis_tuser[0] = \ ; + assign m_axis_tvalid = \ ; + assign overflow = \ ; + assign prog_full = \ ; + assign rd_data_count[13] = \ ; + assign rd_data_count[12] = \ ; + assign rd_data_count[11] = \ ; + assign rd_data_count[10] = \ ; + assign rd_data_count[9] = \ ; + assign rd_data_count[8] = \ ; + assign rd_data_count[7] = \ ; + assign rd_data_count[6] = \ ; + assign rd_data_count[5] = \ ; + assign rd_data_count[4] = \ ; + assign rd_data_count[3] = \ ; + assign rd_data_count[2] = \ ; + assign rd_data_count[1] = \ ; + assign rd_data_count[0] = \ ; + assign rd_rst_busy = \ ; + assign s_axi_arready = \ ; + assign s_axi_awready = \ ; + assign s_axi_bid[0] = \ ; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_buser[0] = \ ; + assign s_axi_bvalid = \ ; + assign s_axi_rdata[63] = \ ; + assign s_axi_rdata[62] = \ ; + assign s_axi_rdata[61] = \ ; + assign s_axi_rdata[60] = \ ; + assign s_axi_rdata[59] = \ ; + assign s_axi_rdata[58] = \ ; + assign s_axi_rdata[57] = \ ; + assign s_axi_rdata[56] = \ ; + assign s_axi_rdata[55] = \ ; + assign s_axi_rdata[54] = \ ; + assign s_axi_rdata[53] = \ ; + assign s_axi_rdata[52] = \ ; + assign s_axi_rdata[51] = \ ; + assign s_axi_rdata[50] = \ ; + assign s_axi_rdata[49] = \ ; + assign s_axi_rdata[48] = \ ; + assign s_axi_rdata[47] = \ ; + assign s_axi_rdata[46] = \ ; + assign s_axi_rdata[45] = \ ; + assign s_axi_rdata[44] = \ ; + assign s_axi_rdata[43] = \ ; + assign s_axi_rdata[42] = \ ; + assign s_axi_rdata[41] = \ ; + assign s_axi_rdata[40] = \ ; + assign s_axi_rdata[39] = \ ; + assign s_axi_rdata[38] = \ ; + assign s_axi_rdata[37] = \ ; + assign s_axi_rdata[36] = \ ; + assign s_axi_rdata[35] = \ ; + assign s_axi_rdata[34] = \ ; + assign s_axi_rdata[33] = \ ; + assign s_axi_rdata[32] = \ ; + assign s_axi_rdata[31] = \ ; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1] = \ ; + assign s_axi_rdata[0] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + assign s_axi_ruser[0] = \ ; + assign s_axi_rvalid = \ ; + assign s_axi_wready = \ ; + assign s_axis_tready = \ ; + assign sbiterr = \ ; + assign underflow = \ ; + assign valid = \ ; + assign wr_ack = \ ; + assign wr_data_count[13] = \ ; + assign wr_data_count[12] = \ ; + assign wr_data_count[11] = \ ; + assign wr_data_count[10] = \ ; + assign wr_data_count[9] = \ ; + assign wr_data_count[8] = \ ; + assign wr_data_count[7] = \ ; + assign wr_data_count[6] = \ ; + assign wr_data_count[5] = \ ; + assign wr_data_count[4] = \ ; + assign wr_data_count[3] = \ ; + assign wr_data_count[2] = \ ; + assign wr_data_count[1] = \ ; + assign wr_data_count[0] = \ ; + assign wr_rst_busy = \ ; + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen + (.din(din), + .dout(dout), + .empty(empty), + .full(full), + .prog_empty(prog_empty), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth + (dout, + empty, + full, + prog_empty, + wr_en, + rd_en, + wr_clk, + rd_clk, + din); + output [31:0]dout; + output empty; + output full; + output prog_empty; + input wr_en; + input rd_en; + input wr_clk; + input rd_clk; + input [31:0]din; + + wire [31:0]din; + wire [31:0]dout; + wire empty; + wire full; + wire prog_empty; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf + (.din(din), + .dout(dout), + .empty(empty), + .full(full), + .prog_empty(prog_empty), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory + (dout, + wr_clk, + rd_clk, + Q, + \gc0.count_d1_reg[13] , + din, + ram_full_fb_i_reg, + WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , + ram_full_fb_i_reg_0, + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); + output [31:0]dout; + input wr_clk; + input rd_clk; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [31:0]din; + input [0:0]ram_full_fb_i_reg; + input [0:0]WEA; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; + + wire [13:0]Q; + wire [0:0]WEA; + wire [31:0]din; + wire [31:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; + wire ram_empty_fb_i_reg; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire rd_en; + wire wr_clk; + wire wr_en; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr + (D, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + Q, + E, + rd_clk, + rd_en, + out); + output [13:0]D; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [13:0]Q; + input [0:0]E; + input rd_clk; + input rd_en; + input out; + + wire [13:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]E; + wire [13:0]Q; + wire \gc0.count[0]_i_2_n_0 ; + wire \gc0.count[0]_i_3_n_0 ; + wire \gc0.count[0]_i_4_n_0 ; + wire \gc0.count[0]_i_5_n_0 ; + wire \gc0.count[12]_i_2_n_0 ; + wire \gc0.count[12]_i_3_n_0 ; + wire \gc0.count[4]_i_2_n_0 ; + wire \gc0.count[4]_i_3_n_0 ; + wire \gc0.count[4]_i_4_n_0 ; + wire \gc0.count[4]_i_5_n_0 ; + wire \gc0.count[8]_i_2_n_0 ; + wire \gc0.count[8]_i_3_n_0 ; + wire \gc0.count[8]_i_4_n_0 ; + wire \gc0.count[8]_i_5_n_0 ; + wire \gc0.count_reg[0]_i_1_n_0 ; + wire \gc0.count_reg[0]_i_1_n_1 ; + wire \gc0.count_reg[0]_i_1_n_2 ; + wire \gc0.count_reg[0]_i_1_n_3 ; + wire \gc0.count_reg[0]_i_1_n_4 ; + wire \gc0.count_reg[0]_i_1_n_5 ; + wire \gc0.count_reg[0]_i_1_n_6 ; + wire \gc0.count_reg[0]_i_1_n_7 ; + wire \gc0.count_reg[12]_i_1_n_3 ; + wire \gc0.count_reg[12]_i_1_n_6 ; + wire \gc0.count_reg[12]_i_1_n_7 ; + wire \gc0.count_reg[4]_i_1_n_0 ; + wire \gc0.count_reg[4]_i_1_n_1 ; + wire \gc0.count_reg[4]_i_1_n_2 ; + wire \gc0.count_reg[4]_i_1_n_3 ; + wire \gc0.count_reg[4]_i_1_n_4 ; + wire \gc0.count_reg[4]_i_1_n_5 ; + wire \gc0.count_reg[4]_i_1_n_6 ; + wire \gc0.count_reg[4]_i_1_n_7 ; + wire \gc0.count_reg[8]_i_1_n_0 ; + wire \gc0.count_reg[8]_i_1_n_1 ; + wire \gc0.count_reg[8]_i_1_n_2 ; + wire \gc0.count_reg[8]_i_1_n_3 ; + wire \gc0.count_reg[8]_i_1_n_4 ; + wire \gc0.count_reg[8]_i_1_n_5 ; + wire \gc0.count_reg[8]_i_1_n_6 ; + wire \gc0.count_reg[8]_i_1_n_7 ; + wire out; + wire rd_clk; + wire rd_en; + wire [3:1]\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:2]\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED ; + + LUT4 #( + .INIT(16'h0080)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 + (.I0(Q[13]), + .I1(Q[12]), + .I2(rd_en), + .I3(out), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gc0.count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[12]_i_2 + (.I0(D[13]), + .O(\gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[12]_i_3 + (.I0(D[12]), + .O(\gc0.count[12]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gc0.count[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[0] + (.C(rd_clk), + .CE(E), + .D(D[0]), + .Q(Q[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[10] + (.C(rd_clk), + .CE(E), + .D(D[10]), + .Q(Q[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[11] + (.C(rd_clk), + .CE(E), + .D(D[11]), + .Q(Q[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[12] + (.C(rd_clk), + .CE(E), + .D(D[12]), + .Q(Q[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[13] + (.C(rd_clk), + .CE(E), + .D(D[13]), + .Q(Q[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[1] + (.C(rd_clk), + .CE(E), + .D(D[1]), + .Q(Q[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[2] + (.C(rd_clk), + .CE(E), + .D(D[2]), + .Q(Q[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[3] + (.C(rd_clk), + .CE(E), + .D(D[3]), + .Q(Q[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[4] + (.C(rd_clk), + .CE(E), + .D(D[4]), + .Q(Q[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[5] + (.C(rd_clk), + .CE(E), + .D(D[5]), + .Q(Q[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[6] + (.C(rd_clk), + .CE(E), + .D(D[6]), + .Q(Q[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[7] + (.C(rd_clk), + .CE(E), + .D(D[7]), + .Q(Q[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[8] + (.C(rd_clk), + .CE(E), + .D(D[8]), + .Q(Q[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[9] + (.C(rd_clk), + .CE(E), + .D(D[9]), + .Q(Q[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \gc0.count_reg[0] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_7 ), + .Q(D[0]), + .R(1'b0)); + CARRY4 \gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gc0.count_reg[0]_i_1_n_0 ,\gc0.count_reg[0]_i_1_n_1 ,\gc0.count_reg[0]_i_1_n_2 ,\gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gc0.count_reg[0]_i_1_n_4 ,\gc0.count_reg[0]_i_1_n_5 ,\gc0.count_reg[0]_i_1_n_6 ,\gc0.count_reg[0]_i_1_n_7 }), + .S({\gc0.count[0]_i_2_n_0 ,\gc0.count[0]_i_3_n_0 ,\gc0.count[0]_i_4_n_0 ,\gc0.count[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[10] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[11] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[12] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[12]_i_1_n_7 ), + .Q(D[12]), + .R(1'b0)); + CARRY4 \gc0.count_reg[12]_i_1 + (.CI(\gc0.count_reg[8]_i_1_n_0 ), + .CO({\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:1],\gc0.count_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED [3:2],\gc0.count_reg[12]_i_1_n_6 ,\gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,\gc0.count[12]_i_2_n_0 ,\gc0.count[12]_i_3_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[13] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[12]_i_1_n_6 ), + .Q(D[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[1] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_6 ), + .Q(D[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[2] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[3] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[4] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4]), + .R(1'b0)); + CARRY4 \gc0.count_reg[4]_i_1 + (.CI(\gc0.count_reg[0]_i_1_n_0 ), + .CO({\gc0.count_reg[4]_i_1_n_0 ,\gc0.count_reg[4]_i_1_n_1 ,\gc0.count_reg[4]_i_1_n_2 ,\gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[4]_i_1_n_4 ,\gc0.count_reg[4]_i_1_n_5 ,\gc0.count_reg[4]_i_1_n_6 ,\gc0.count_reg[4]_i_1_n_7 }), + .S({\gc0.count[4]_i_2_n_0 ,\gc0.count[4]_i_3_n_0 ,\gc0.count[4]_i_4_n_0 ,\gc0.count[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[5] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[6] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[7] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[8] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8]), + .R(1'b0)); + CARRY4 \gc0.count_reg[8]_i_1 + (.CI(\gc0.count_reg[4]_i_1_n_0 ), + .CO({\gc0.count_reg[8]_i_1_n_0 ,\gc0.count_reg[8]_i_1_n_1 ,\gc0.count_reg[8]_i_1_n_2 ,\gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[8]_i_1_n_4 ,\gc0.count_reg[8]_i_1_n_5 ,\gc0.count_reg[8]_i_1_n_6 ,\gc0.count_reg[8]_i_1_n_7 }), + .S({\gc0.count[8]_i_2_n_0 ,\gc0.count[8]_i_3_n_0 ,\gc0.count[8]_i_4_n_0 ,\gc0.count[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[9] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9]), + .R(1'b0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic + (empty, + out, + prog_empty, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + Q, + rd_clk, + rd_en, + WR_PNTR_RD, + S, + \gnxpm_cdc.wr_pntr_bin_reg[7] , + \gnxpm_cdc.wr_pntr_bin_reg[11] , + \gnxpm_cdc.wr_pntr_bin_reg[13] ); + output empty; + output out; + output prog_empty; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [13:0]Q; + input rd_clk; + input rd_en; + input [13:0]WR_PNTR_RD; + input [3:0]S; + input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; + input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; + input [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [13:0]Q; + wire [3:0]S; + wire [13:0]WR_PNTR_RD; + wire empty; + wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; + wire [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; + wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; + wire \gras.rsts_n_2 ; + wire out; + wire p_0_out; + wire prog_empty; + wire rd_clk; + wire rd_en; + wire [13:0]rd_pntr_plus1; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as \gras.gpe.rdpe + (.S(S), + .WR_PNTR_RD(WR_PNTR_RD[12:0]), + .\gnxpm_cdc.wr_pntr_bin_reg[11] (\gnxpm_cdc.wr_pntr_bin_reg[11] ), + .\gnxpm_cdc.wr_pntr_bin_reg[13] (\gnxpm_cdc.wr_pntr_bin_reg[13] ), + .\gnxpm_cdc.wr_pntr_bin_reg[7] (\gnxpm_cdc.wr_pntr_bin_reg[7] ), + .out(out), + .p_0_out(p_0_out), + .prog_empty(prog_empty), + .rd_clk(rd_clk)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as \gras.rsts + (.D(rd_pntr_plus1), + .E(\gras.rsts_n_2 ), + .Q(Q), + .WR_PNTR_RD(WR_PNTR_RD), + .empty(empty), + .out(out), + .p_0_out(p_0_out), + .rd_clk(rd_clk), + .rd_en(rd_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr + (.D(rd_pntr_plus1), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .E(\gras.rsts_n_2 ), + .Q(Q), + .out(out), + .rd_clk(rd_clk), + .rd_en(rd_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as + (prog_empty, + p_0_out, + WR_PNTR_RD, + S, + \gnxpm_cdc.wr_pntr_bin_reg[7] , + \gnxpm_cdc.wr_pntr_bin_reg[11] , + \gnxpm_cdc.wr_pntr_bin_reg[13] , + rd_clk, + out); + output prog_empty; + input p_0_out; + input [12:0]WR_PNTR_RD; + input [3:0]S; + input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; + input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; + input [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; + input rd_clk; + input out; + + wire [3:0]S; + wire [12:0]WR_PNTR_RD; + wire [14:11]diff_pntr_pad; + wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; + wire [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; + wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; + wire \gpe1.prog_empty_i_i_1_n_0 ; + wire out; + wire p_0_out; + wire [14:11]plusOp; + wire plusOp_carry__0_n_0; + wire plusOp_carry__0_n_1; + wire plusOp_carry__0_n_2; + wire plusOp_carry__0_n_3; + wire plusOp_carry__1_n_0; + wire plusOp_carry__1_n_1; + wire plusOp_carry__1_n_2; + wire plusOp_carry__1_n_3; + wire plusOp_carry__2_n_3; + wire plusOp_carry_n_0; + wire plusOp_carry_n_1; + wire plusOp_carry_n_2; + wire plusOp_carry_n_3; + wire prog_empty; + wire rd_clk; + wire [3:0]NLW_plusOp_carry_O_UNCONNECTED; + wire [3:0]NLW_plusOp_carry__0_O_UNCONNECTED; + wire [1:0]NLW_plusOp_carry__1_O_UNCONNECTED; + wire [3:1]NLW_plusOp_carry__2_CO_UNCONNECTED; + wire [3:2]NLW_plusOp_carry__2_O_UNCONNECTED; + + FDRE #( + .INIT(1'b0)) + \gdiff.diff_pntr_pad_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(plusOp[11]), + .Q(diff_pntr_pad[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gdiff.diff_pntr_pad_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(plusOp[12]), + .Q(diff_pntr_pad[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gdiff.diff_pntr_pad_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(plusOp[13]), + .Q(diff_pntr_pad[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gdiff.diff_pntr_pad_reg[14] + (.C(rd_clk), + .CE(1'b1), + .D(plusOp[14]), + .Q(diff_pntr_pad[14]), + .R(1'b0)); + LUT6 #( + .INIT(64'h888888888888888B)) + \gpe1.prog_empty_i_i_1 + (.I0(prog_empty), + .I1(out), + .I2(diff_pntr_pad[13]), + .I3(diff_pntr_pad[14]), + .I4(diff_pntr_pad[12]), + .I5(diff_pntr_pad[11]), + .O(\gpe1.prog_empty_i_i_1_n_0 )); + FDRE #( + .INIT(1'b1)) + \gpe1.prog_empty_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(\gpe1.prog_empty_i_i_1_n_0 ), + .Q(prog_empty), + .R(1'b0)); + CARRY4 plusOp_carry + (.CI(1'b0), + .CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}), + .CYINIT(p_0_out), + .DI(WR_PNTR_RD[3:0]), + .O(NLW_plusOp_carry_O_UNCONNECTED[3:0]), + .S(S)); + CARRY4 plusOp_carry__0 + (.CI(plusOp_carry_n_0), + .CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI(WR_PNTR_RD[7:4]), + .O(NLW_plusOp_carry__0_O_UNCONNECTED[3:0]), + .S(\gnxpm_cdc.wr_pntr_bin_reg[7] )); + CARRY4 plusOp_carry__1 + (.CI(plusOp_carry__0_n_0), + .CO({plusOp_carry__1_n_0,plusOp_carry__1_n_1,plusOp_carry__1_n_2,plusOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI(WR_PNTR_RD[11:8]), + .O({plusOp[12:11],NLW_plusOp_carry__1_O_UNCONNECTED[1:0]}), + .S(\gnxpm_cdc.wr_pntr_bin_reg[11] )); + CARRY4 plusOp_carry__2 + (.CI(plusOp_carry__1_n_0), + .CO({NLW_plusOp_carry__2_CO_UNCONNECTED[3:1],plusOp_carry__2_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,WR_PNTR_RD[12]}), + .O({NLW_plusOp_carry__2_O_UNCONNECTED[3:2],plusOp[14:13]}), + .S({1'b0,1'b0,\gnxpm_cdc.wr_pntr_bin_reg[13] })); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as + (empty, + out, + E, + p_0_out, + rd_clk, + rd_en, + WR_PNTR_RD, + Q, + D); + output empty; + output out; + output [0:0]E; + output p_0_out; + input rd_clk; + input rd_en; + input [13:0]WR_PNTR_RD; + input [13:0]Q; + input [13:0]D; + + wire [13:0]D; + wire [0:0]E; + wire [13:0]Q; + wire [13:0]WR_PNTR_RD; + wire comp0; + wire comp1; + wire p_0_out; + (* DONT_TOUCH *) wire ram_empty_fb_i; + (* DONT_TOUCH *) wire ram_empty_i; + wire ram_empty_i_reg0_n_0; + wire rd_clk; + wire rd_en; + + assign empty = ram_empty_i; + assign out = ram_empty_fb_i; + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 c0 + (.Q(Q), + .WR_PNTR_RD(WR_PNTR_RD), + .comp0(comp0)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c1 + (.D(D), + .WR_PNTR_RD(WR_PNTR_RD), + .comp1(comp1)); + LUT2 #( + .INIT(4'h2)) + \gc0.count_d1[13]_i_1 + (.I0(rd_en), + .I1(ram_empty_fb_i), + .O(E)); + LUT2 #( + .INIT(4'hB)) + plusOp_carry_i_1 + (.I0(ram_empty_fb_i), + .I1(rd_en), + .O(p_0_out)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + ram_empty_fb_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(ram_empty_i_reg0_n_0), + .Q(ram_empty_fb_i), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + ram_empty_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(ram_empty_i_reg0_n_0), + .Q(ram_empty_i), + .R(1'b0)); + LUT4 #( + .INIT(16'hAEAA)) + ram_empty_i_reg0 + (.I0(comp0), + .I1(rd_en), + .I2(ram_empty_fb_i), + .I3(comp1), + .O(ram_empty_i_reg0_n_0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff + (out, + in0, + rd_clk); + output [13:0]out; + input [13:0]in0; + input rd_clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; + wire [13:0]in0; + wire rd_clk; + + assign out[13:0] = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(in0[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(in0[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(in0[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(in0[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(in0[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(in0[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(in0[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(in0[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(in0[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(in0[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(in0[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(in0[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(in0[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(in0[9]), + .Q(Q_reg[9]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_4 + (out, + Q, + wr_clk); + output [13:0]out; + input [13:0]Q; + input wr_clk; + + wire [13:0]Q; + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; + wire wr_clk; + + assign out[13:0] = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(Q[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(Q[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(Q[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(Q[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(wr_clk), + .CE(1'b1), + .D(Q[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(Q[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(Q[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(Q[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(Q[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(Q[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(Q[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(Q[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(Q[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(Q[9]), + .Q(Q_reg[9]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_5 + (\gnxpm_cdc.wr_pntr_bin_reg[13] , + D, + out, + rd_clk); + output [0:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; + output [12:0]D; + input [13:0]out; + input rd_clk; + + wire [12:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; + wire \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[2]_i_3_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[5]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[5]_i_3_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[5]_i_4_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[6]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 ; + wire [13:0]out; + wire rd_clk; + + assign \gnxpm_cdc.wr_pntr_bin_reg[13] [0] = Q_reg[13]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(out[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(out[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(out[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(out[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(out[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(out[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(out[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(rd_clk), + .CE(1'b1), + .D(out[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(rd_clk), + .CE(1'b1), + .D(out[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(rd_clk), + .CE(1'b1), + .D(out[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(rd_clk), + .CE(1'b1), + .D(out[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(rd_clk), + .CE(1'b1), + .D(out[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(rd_clk), + .CE(1'b1), + .D(out[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(rd_clk), + .CE(1'b1), + .D(out[9]), + .Q(Q_reg[9]), + .R(1'b0)); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[0]_i_1 + (.I0(Q_reg[1]), + .I1(Q_reg[0]), + .I2(D[2]), + .O(D[0])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.wr_pntr_bin[10]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[10]), + .I2(Q_reg[13]), + .I3(Q_reg[12]), + .O(D[10])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[11]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(Q_reg[13]), + .O(D[11])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[12]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[13]), + .O(D[12])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 ), + .I1(Q_reg[7]), + .I2(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), + .O(D[1])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[1]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[6]), + .I2(Q_reg[2]), + .I3(Q_reg[1]), + .I4(Q_reg[4]), + .I5(Q_reg[3]), + .O(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[2]_i_1 + (.I0(Q_reg[4]), + .I1(Q_reg[5]), + .I2(Q_reg[2]), + .I3(Q_reg[3]), + .I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), + .I5(\gnxpm_cdc.wr_pntr_bin[2]_i_3_n_0 ), + .O(D[2])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[2]_i_2 + (.I0(Q_reg[10]), + .I1(Q_reg[6]), + .O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[2]_i_3 + (.I0(Q_reg[8]), + .I1(Q_reg[7]), + .I2(Q_reg[12]), + .I3(Q_reg[9]), + .I4(Q_reg[13]), + .I5(Q_reg[11]), + .O(\gnxpm_cdc.wr_pntr_bin[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[3]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[12]), + .I2(Q_reg[7]), + .I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ), + .I4(Q_reg[13]), + .I5(Q_reg[8]), + .O(D[3])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[3]_i_2 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[4]), + .I3(Q_reg[3]), + .I4(Q_reg[6]), + .I5(Q_reg[5]), + .O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[4]_i_1 + (.I0(Q_reg[7]), + .I1(\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ), + .I2(Q_reg[11]), + .I3(Q_reg[8]), + .I4(Q_reg[13]), + .O(D[4])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[4]_i_2 + (.I0(Q_reg[9]), + .I1(Q_reg[12]), + .I2(Q_reg[5]), + .I3(Q_reg[4]), + .I4(Q_reg[10]), + .I5(Q_reg[6]), + .O(\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[5]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(\gnxpm_cdc.wr_pntr_bin[5]_i_2_n_0 ), + .I3(\gnxpm_cdc.wr_pntr_bin[5]_i_3_n_0 ), + .I4(Q_reg[7]), + .I5(\gnxpm_cdc.wr_pntr_bin[5]_i_4_n_0 ), + .O(D[5])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[5]_i_2 + (.I0(Q_reg[6]), + .I1(Q_reg[5]), + .O(\gnxpm_cdc.wr_pntr_bin[5]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[5]_i_3 + (.I0(Q_reg[9]), + .I1(Q_reg[10]), + .O(\gnxpm_cdc.wr_pntr_bin[5]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[5]_i_4 + (.I0(Q_reg[13]), + .I1(Q_reg[8]), + .O(\gnxpm_cdc.wr_pntr_bin[5]_i_4_n_0 )); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[6]_i_1 + (.I0(Q_reg[7]), + .I1(Q_reg[8]), + .I2(\gnxpm_cdc.wr_pntr_bin[6]_i_2_n_0 ), + .O(D[6])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[6]_i_2 + (.I0(Q_reg[11]), + .I1(Q_reg[13]), + .I2(Q_reg[10]), + .I3(Q_reg[6]), + .I4(Q_reg[12]), + .I5(Q_reg[9]), + .O(\gnxpm_cdc.wr_pntr_bin[6]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[7]_i_1 + (.I0(Q_reg[7]), + .I1(\gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 ), + .O(D[7])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[7]_i_2 + (.I0(Q_reg[13]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[10]), + .I4(Q_reg[11]), + .I5(Q_reg[12]), + .O(\gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[8]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[13]), + .I4(Q_reg[11]), + .I5(Q_reg[12]), + .O(D[8])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[9]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[9]), + .I2(Q_reg[10]), + .I3(Q_reg[13]), + .I4(Q_reg[12]), + .O(D[9])); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_6 + (\gnxpm_cdc.rd_pntr_bin_reg[13] , + D, + out, + wr_clk); + output [0:0]\gnxpm_cdc.rd_pntr_bin_reg[13] ; + output [12:0]D; + input [13:0]out; + input wr_clk; + + wire [12:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; + wire \gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 ; + wire \gnxpm_cdc.rd_pntr_bin[7]_i_2_n_0 ; + wire [13:0]out; + wire wr_clk; + + assign \gnxpm_cdc.rd_pntr_bin_reg[13] [0] = Q_reg[13]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(out[0]), + .Q(Q_reg[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(out[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(out[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(out[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(wr_clk), + .CE(1'b1), + .D(out[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(out[1]), + .Q(Q_reg[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(out[2]), + .Q(Q_reg[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(wr_clk), + .CE(1'b1), + .D(out[3]), + .Q(Q_reg[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(wr_clk), + .CE(1'b1), + .D(out[4]), + .Q(Q_reg[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(wr_clk), + .CE(1'b1), + .D(out[5]), + .Q(Q_reg[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(wr_clk), + .CE(1'b1), + .D(out[6]), + .Q(Q_reg[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(wr_clk), + .CE(1'b1), + .D(out[7]), + .Q(Q_reg[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(wr_clk), + .CE(1'b1), + .D(out[8]), + .Q(Q_reg[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(wr_clk), + .CE(1'b1), + .D(out[9]), + .Q(Q_reg[9]), + .R(1'b0)); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[0]_i_1 + (.I0(Q_reg[1]), + .I1(Q_reg[0]), + .I2(Q_reg[2]), + .I3(Q_reg[4]), + .I4(D[5]), + .I5(Q_reg[3]), + .O(D[0])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[10]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[10]), + .I2(Q_reg[13]), + .I3(Q_reg[12]), + .O(D[10])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.rd_pntr_bin[11]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(Q_reg[13]), + .O(D[11])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[12]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[13]), + .O(D[12])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[1]_i_1 + (.I0(Q_reg[2]), + .I1(Q_reg[4]), + .I2(D[5]), + .I3(Q_reg[3]), + .I4(Q_reg[1]), + .O(D[1])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[2]_i_1 + (.I0(Q_reg[3]), + .I1(Q_reg[5]), + .I2(D[7]), + .I3(Q_reg[6]), + .I4(Q_reg[4]), + .I5(Q_reg[2]), + .O(D[2])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[3]_i_1 + (.I0(Q_reg[4]), + .I1(Q_reg[6]), + .I2(D[7]), + .I3(Q_reg[5]), + .I4(Q_reg[3]), + .O(D[3])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[4]_i_1 + (.I0(Q_reg[5]), + .I1(D[7]), + .I2(Q_reg[6]), + .I3(Q_reg[4]), + .O(D[4])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[5]_i_1 + (.I0(Q_reg[6]), + .I1(Q_reg[13]), + .I2(Q_reg[7]), + .I3(Q_reg[8]), + .I4(\gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 ), + .I5(Q_reg[5]), + .O(D[5])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[6]_i_1 + (.I0(\gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 ), + .I1(Q_reg[8]), + .I2(Q_reg[7]), + .I3(Q_reg[13]), + .I4(Q_reg[6]), + .O(D[6])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[6]_i_2 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(Q_reg[10]), + .I3(Q_reg[9]), + .O(\gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[7]_i_1 + (.I0(Q_reg[13]), + .I1(Q_reg[7]), + .I2(Q_reg[8]), + .I3(\gnxpm_cdc.rd_pntr_bin[7]_i_2_n_0 ), + .I4(Q_reg[11]), + .I5(Q_reg[12]), + .O(D[7])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[7]_i_2 + (.I0(Q_reg[9]), + .I1(Q_reg[10]), + .O(\gnxpm_cdc.rd_pntr_bin[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[8]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[13]), + .I4(Q_reg[11]), + .I5(Q_reg[12]), + .O(D[8])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[9]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[9]), + .I2(Q_reg[10]), + .I3(Q_reg[13]), + .I4(Q_reg[12]), + .O(D[9])); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr + (D, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + Q, + \gic0.gc0.count_d2_reg[13]_0 , + E, + wr_clk, + wr_en, + out); + output [13:0]D; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [13:0]Q; + output [13:0]\gic0.gc0.count_d2_reg[13]_0 ; + input [0:0]E; + input wr_clk; + input wr_en; + input out; + + wire [13:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]E; + wire [13:0]Q; + wire \gic0.gc0.count[0]_i_2_n_0 ; + wire \gic0.gc0.count[0]_i_3_n_0 ; + wire \gic0.gc0.count[0]_i_4_n_0 ; + wire \gic0.gc0.count[0]_i_5_n_0 ; + wire \gic0.gc0.count[12]_i_2_n_0 ; + wire \gic0.gc0.count[12]_i_3_n_0 ; + wire \gic0.gc0.count[4]_i_2_n_0 ; + wire \gic0.gc0.count[4]_i_3_n_0 ; + wire \gic0.gc0.count[4]_i_4_n_0 ; + wire \gic0.gc0.count[4]_i_5_n_0 ; + wire \gic0.gc0.count[8]_i_2_n_0 ; + wire \gic0.gc0.count[8]_i_3_n_0 ; + wire \gic0.gc0.count[8]_i_4_n_0 ; + wire \gic0.gc0.count[8]_i_5_n_0 ; + wire [13:0]\gic0.gc0.count_d2_reg[13]_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_1 ; + wire \gic0.gc0.count_reg[0]_i_1_n_2 ; + wire \gic0.gc0.count_reg[0]_i_1_n_3 ; + wire \gic0.gc0.count_reg[0]_i_1_n_4 ; + wire \gic0.gc0.count_reg[0]_i_1_n_5 ; + wire \gic0.gc0.count_reg[0]_i_1_n_6 ; + wire \gic0.gc0.count_reg[0]_i_1_n_7 ; + wire \gic0.gc0.count_reg[12]_i_1_n_3 ; + wire \gic0.gc0.count_reg[12]_i_1_n_6 ; + wire \gic0.gc0.count_reg[12]_i_1_n_7 ; + wire \gic0.gc0.count_reg[4]_i_1_n_0 ; + wire \gic0.gc0.count_reg[4]_i_1_n_1 ; + wire \gic0.gc0.count_reg[4]_i_1_n_2 ; + wire \gic0.gc0.count_reg[4]_i_1_n_3 ; + wire \gic0.gc0.count_reg[4]_i_1_n_4 ; + wire \gic0.gc0.count_reg[4]_i_1_n_5 ; + wire \gic0.gc0.count_reg[4]_i_1_n_6 ; + wire \gic0.gc0.count_reg[4]_i_1_n_7 ; + wire \gic0.gc0.count_reg[8]_i_1_n_0 ; + wire \gic0.gc0.count_reg[8]_i_1_n_1 ; + wire \gic0.gc0.count_reg[8]_i_1_n_2 ; + wire \gic0.gc0.count_reg[8]_i_1_n_3 ; + wire \gic0.gc0.count_reg[8]_i_1_n_4 ; + wire \gic0.gc0.count_reg[8]_i_1_n_5 ; + wire \gic0.gc0.count_reg[8]_i_1_n_6 ; + wire \gic0.gc0.count_reg[8]_i_1_n_7 ; + wire out; + wire wr_clk; + wire wr_en; + wire [3:1]\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:2]\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED ; + + LUT4 #( + .INIT(16'h0080)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 + (.I0(Q[13]), + .I1(Q[12]), + .I2(wr_en), + .I3(out), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gic0.gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gic0.gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gic0.gc0.count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \gic0.gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gic0.gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[12]_i_2 + (.I0(D[13]), + .O(\gic0.gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[12]_i_3 + (.I0(D[12]), + .O(\gic0.gc0.count[12]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gic0.gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gic0.gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gic0.gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gic0.gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gic0.gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gic0.gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gic0.gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gic0.gc0.count[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b1)) + \gic0.gc0.count_d1_reg[0] + (.C(wr_clk), + .CE(E), + .D(D[0]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[10] + (.C(wr_clk), + .CE(E), + .D(D[10]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[11] + (.C(wr_clk), + .CE(E), + .D(D[11]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[12] + (.C(wr_clk), + .CE(E), + .D(D[12]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[13] + (.C(wr_clk), + .CE(E), + .D(D[13]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[1] + (.C(wr_clk), + .CE(E), + .D(D[1]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[2] + (.C(wr_clk), + .CE(E), + .D(D[2]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[3] + (.C(wr_clk), + .CE(E), + .D(D[3]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[4] + (.C(wr_clk), + .CE(E), + .D(D[4]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[5] + (.C(wr_clk), + .CE(E), + .D(D[5]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[6] + (.C(wr_clk), + .CE(E), + .D(D[6]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[7] + (.C(wr_clk), + .CE(E), + .D(D[7]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[8] + (.C(wr_clk), + .CE(E), + .D(D[8]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[9] + (.C(wr_clk), + .CE(E), + .D(D[9]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[0] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [0]), + .Q(Q[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[10] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [10]), + .Q(Q[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[11] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [11]), + .Q(Q[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[12] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [12]), + .Q(Q[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[13] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [13]), + .Q(Q[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[1] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [1]), + .Q(Q[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[2] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [2]), + .Q(Q[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[3] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [3]), + .Q(Q[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[4] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [4]), + .Q(Q[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[5] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [5]), + .Q(Q[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[6] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [6]), + .Q(Q[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[7] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [7]), + .Q(Q[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[8] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [8]), + .Q(Q[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[9] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [9]), + .Q(Q[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[0] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[0]_i_1_n_7 ), + .Q(D[0]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gic0.gc0.count_reg[0]_i_1_n_0 ,\gic0.gc0.count_reg[0]_i_1_n_1 ,\gic0.gc0.count_reg[0]_i_1_n_2 ,\gic0.gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gic0.gc0.count_reg[0]_i_1_n_4 ,\gic0.gc0.count_reg[0]_i_1_n_5 ,\gic0.gc0.count_reg[0]_i_1_n_6 ,\gic0.gc0.count_reg[0]_i_1_n_7 }), + .S({\gic0.gc0.count[0]_i_2_n_0 ,\gic0.gc0.count[0]_i_3_n_0 ,\gic0.gc0.count[0]_i_4_n_0 ,\gic0.gc0.count[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[10] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[11] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[12] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[12]_i_1_n_7 ), + .Q(D[12]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[12]_i_1 + (.CI(\gic0.gc0.count_reg[8]_i_1_n_0 ), + .CO({\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:1],\gic0.gc0.count_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED [3:2],\gic0.gc0.count_reg[12]_i_1_n_6 ,\gic0.gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,\gic0.gc0.count[12]_i_2_n_0 ,\gic0.gc0.count[12]_i_3_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[13] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[12]_i_1_n_6 ), + .Q(D[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \gic0.gc0.count_reg[1] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[0]_i_1_n_6 ), + .Q(D[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[2] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[3] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[4] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[4]_i_1 + (.CI(\gic0.gc0.count_reg[0]_i_1_n_0 ), + .CO({\gic0.gc0.count_reg[4]_i_1_n_0 ,\gic0.gc0.count_reg[4]_i_1_n_1 ,\gic0.gc0.count_reg[4]_i_1_n_2 ,\gic0.gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[4]_i_1_n_4 ,\gic0.gc0.count_reg[4]_i_1_n_5 ,\gic0.gc0.count_reg[4]_i_1_n_6 ,\gic0.gc0.count_reg[4]_i_1_n_7 }), + .S({\gic0.gc0.count[4]_i_2_n_0 ,\gic0.gc0.count[4]_i_3_n_0 ,\gic0.gc0.count[4]_i_4_n_0 ,\gic0.gc0.count[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[5] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[6] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[7] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[8] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[8]_i_1 + (.CI(\gic0.gc0.count_reg[4]_i_1_n_0 ), + .CO({\gic0.gc0.count_reg[8]_i_1_n_0 ,\gic0.gc0.count_reg[8]_i_1_n_1 ,\gic0.gc0.count_reg[8]_i_1_n_2 ,\gic0.gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[8]_i_1_n_4 ,\gic0.gc0.count_reg[8]_i_1_n_5 ,\gic0.gc0.count_reg[8]_i_1_n_6 ,\gic0.gc0.count_reg[8]_i_1_n_7 }), + .S({\gic0.gc0.count[8]_i_2_n_0 ,\gic0.gc0.count[8]_i_3_n_0 ,\gic0.gc0.count[8]_i_4_n_0 ,\gic0.gc0.count[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[9] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9]), + .R(1'b0)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic + (full, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + Q, + WEA, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 , + wr_clk, + wr_en, + RD_PNTR_WR); + output full; + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [13:0]Q; + output [0:0]WEA; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + input wr_clk; + input wr_en; + input [13:0]RD_PNTR_WR; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; + wire [0:0]WEA; + wire full; + wire \gwas.wsts_n_2 ; + wire out; + wire [13:0]p_13_out; + wire wr_clk; + wire wr_en; + wire [13:0]wr_pntr_plus2; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as \gwas.wsts + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ), + .E(\gwas.wsts_n_2 ), + .Q(p_13_out), + .RD_PNTR_WR(RD_PNTR_WR), + .WEA(WEA), + .full(full), + .out(out), + .wr_clk(wr_clk), + .wr_en(wr_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .E(\gwas.wsts_n_2 ), + .Q(Q), + .\gic0.gc0.count_d2_reg[13]_0 (p_13_out), + .out(out), + .wr_clk(wr_clk), + .wr_en(wr_en)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as + (full, + out, + E, + WEA, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + wr_clk, + wr_en, + Q, + RD_PNTR_WR, + D); + output full; + output out; + output [0:0]E; + output [0:0]WEA; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input wr_clk; + input wr_en; + input [13:0]Q; + input [13:0]RD_PNTR_WR; + input [13:0]D; + + wire [13:0]D; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [0:0]E; + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; + wire [0:0]WEA; + wire c1_n_0; + wire comp2; + (* DONT_TOUCH *) wire ram_full_fb_i; + (* DONT_TOUCH *) wire ram_full_i; + wire wr_clk; + wire wr_en; + + assign full = ram_full_i; + assign out = ram_full_fb_i; + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(WEA)); + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3__0 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c1 + (.Q(Q), + .RD_PNTR_WR(RD_PNTR_WR), + .comp2(comp2), + .out(ram_full_fb_i), + .ram_full_i_reg(c1_n_0), + .wr_en(wr_en)); + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 c2 + (.D(D), + .RD_PNTR_WR(RD_PNTR_WR), + .comp2(comp2)); + LUT2 #( + .INIT(4'h2)) + \gic0.gc0.count_d1[13]_i_1 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(E)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_fb_i_reg + (.C(wr_clk), + .CE(1'b1), + .D(c1_n_0), + .Q(ram_full_fb_i), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_i_reg + (.C(wr_clk), + .CE(1'b1), + .D(c1_n_0), + .Q(ram_full_i), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/rx_packet_fifo_stub.v b/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/rx_packet_fifo_stub.v new file mode 100755 index 0000000..5ac84ee --- /dev/null +++ b/fpga/projects/rx_only/rx_only.cache/ip/848330eae6fd4c94/rx_packet_fifo_stub.v @@ -0,0 +1,29 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 +// Date : Sat Apr 15 09:39:28 2017 +// Host : david-desktop-arch running 64-bit unknown +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rx_packet_fifo_stub.v +// Design : rx_packet_fifo +// Purpose : Stub declaration of top-level module interface +// Device : xc7a50tftg256-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, + prog_empty) +/* synthesis syn_black_box black_box_pad_pin="wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,prog_empty" */; + input wr_clk; + input rd_clk; + input [31:0]din; + input wr_en; + input rd_en; + output [31:0]dout; + output full; + output empty; + output prog_empty; +endmodule diff --git a/fpga/projects/rx_only/rx_only.ip_user_files/ip/iq_sample_fifo/iq_sample_fifo_stub.v b/fpga/projects/rx_only/rx_only.ip_user_files/ip/iq_sample_fifo/iq_sample_fifo_stub.v index a5b0e5b..406efd5 100644 --- a/fpga/projects/rx_only/rx_only.ip_user_files/ip/iq_sample_fifo/iq_sample_fifo_stub.v +++ b/fpga/projects/rx_only/rx_only.ip_user_files/ip/iq_sample_fifo/iq_sample_fifo_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 -// Date : Mon Dec 12 12:44:58 2016 +// Date : Sat Apr 15 09:49:57 2017 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/misc-projects/rftool-fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_stub.v diff --git a/fpga/projects/rx_only/rx_only.ip_user_files/ip/rx_packet_fifo/rx_packet_fifo_stub.v b/fpga/projects/rx_only/rx_only.ip_user_files/ip/rx_packet_fifo/rx_packet_fifo_stub.v index 8492c36..d137824 100644 --- a/fpga/projects/rx_only/rx_only.ip_user_files/ip/rx_packet_fifo/rx_packet_fifo_stub.v +++ b/fpga/projects/rx_only/rx_only.ip_user_files/ip/rx_packet_fifo/rx_packet_fifo_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 -// Date : Mon Jan 16 15:31:50 2017 +// Date : Sat Apr 15 09:39:28 2017 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/misc-projects/rftool-fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_stub.v diff --git a/fpga/projects/rx_only/rx_only.runs/iq_sample_fifo_synth_1/iq_sample_fifo.tcl b/fpga/projects/rx_only/rx_only.runs/iq_sample_fifo_synth_1/iq_sample_fifo.tcl index af02bc2..7dfadb3 100644 --- a/fpga/projects/rx_only/rx_only.runs/iq_sample_fifo_synth_1/iq_sample_fifo.tcl +++ b/fpga/projects/rx_only/rx_only.runs/iq_sample_fifo_synth_1/iq_sample_fifo.tcl @@ -2,6 +2,7 @@ # Synthesis run script generated by Vivado # +set_param xicom.use_bs_reader 1 set_msg_config -id {HDL 9-1061} -limit 100000 set_msg_config -id {HDL 9-1654} -limit 100000 set_msg_config -msgmgr_mode ooc_run diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo.xci b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo.xci index af64aef..72e3385 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo.xci +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo.xci @@ -41,7 +41,7 @@ 1 0 0 - 10 + 13 BlankString 24 1 @@ -127,7 +127,7 @@ 0 1 0 - 1kx36 + 8kx4 1kx18 512x36 1kx36 @@ -149,14 +149,14 @@ 0 0 0 - 1021 + 8189 1023 1023 1023 1023 1023 1023 - 1020 + 8188 0 0 0 @@ -166,10 +166,10 @@ 0 0 0 - 10 - 1024 + 13 + 8192 1 - 10 + 13 0 0 0 @@ -199,8 +199,8 @@ 0 0 0 - 10 - 1024 + 13 + 8192 1024 16 1024 @@ -208,7 +208,7 @@ 1024 16 1 - 10 + 13 10 4 10 @@ -229,7 +229,7 @@ iq_sample_fifo 64 false - 10 + 13 false false 0 @@ -275,14 +275,14 @@ Common_Clock_Block_RAM Independent_Clocks_Block_RAM 0 - 1021 + 8189 1023 1023 1023 1023 1023 1023 - 1020 + 8188 false false false @@ -303,7 +303,7 @@ false false 24 - 1024 + 8192 1024 16 1024 @@ -312,7 +312,7 @@ 16 false 24 - 1024 + 8192 Embedded_Reg false false @@ -338,7 +338,7 @@ 0 1 false - 10 + 13 Fully_Registered Fully_Registered Fully_Registered @@ -369,7 +369,7 @@ Active_High 1 false - 10 + 13 false FIFO false @@ -407,15 +407,20 @@ + + + + + diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_ooc.xdc b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_ooc.xdc index 6aae615..f112b6e 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_ooc.xdc +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_ooc.xdc @@ -1,4 +1,4 @@ -# (c) Copyright 2012-2016 Xilinx, Inc. All rights reserved. +# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. # # This file contains confidential and proprietary information # of Xilinx, Inc. and is protected under U.S. and diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_sim_netlist.v b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_sim_netlist.v index 78d04bd..3c9b71b 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_sim_netlist.v +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_sim_netlist.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 -// Date : Mon Dec 12 12:44:58 2016 +// Date : Sat Apr 15 09:49:57 2017 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim // /home/dave/misc-projects/rftool-fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_sim_netlist.v @@ -121,7 +121,7 @@ module iq_sample_fifo wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; - wire [9:0]NLW_U0_data_count_UNCONNECTED; + wire [12:0]NLW_U0_data_count_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; @@ -154,7 +154,7 @@ module iq_sample_fifo wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; - wire [9:0]NLW_U0_rd_data_count_UNCONNECTED; + wire [12:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; @@ -162,7 +162,7 @@ module iq_sample_fifo wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; - wire [9:0]NLW_U0_wr_data_count_UNCONNECTED; + wire [12:0]NLW_U0_wr_data_count_UNCONNECTED; (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) @@ -191,7 +191,7 @@ module iq_sample_fifo (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) - (* C_DATA_COUNT_WIDTH = "10" *) + (* C_DATA_COUNT_WIDTH = "13" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "24" *) (* C_DIN_WIDTH_AXIS = "1" *) @@ -277,7 +277,7 @@ module iq_sample_fifo (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) - (* C_PRIM_FIFO_TYPE = "1kx36" *) + (* C_PRIM_FIFO_TYPE = "8kx4" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) @@ -299,14 +299,14 @@ module iq_sample_fifo (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL = "8189" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) - (* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *) + (* C_PROG_FULL_THRESH_NEGATE_VAL = "8188" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) @@ -316,10 +316,10 @@ module iq_sample_fifo (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) - (* C_RD_DATA_COUNT_WIDTH = "10" *) - (* C_RD_DEPTH = "1024" *) + (* C_RD_DATA_COUNT_WIDTH = "13" *) + (* C_RD_DEPTH = "8192" *) (* C_RD_FREQ = "1" *) - (* C_RD_PNTR_WIDTH = "10" *) + (* C_RD_PNTR_WIDTH = "13" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) @@ -349,8 +349,8 @@ module iq_sample_fifo (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) - (* C_WR_DATA_COUNT_WIDTH = "10" *) - (* C_WR_DEPTH = "1024" *) + (* C_WR_DATA_COUNT_WIDTH = "13" *) + (* C_WR_DEPTH = "8192" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) @@ -358,7 +358,7 @@ module iq_sample_fifo (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) - (* C_WR_PNTR_WIDTH = "10" *) + (* C_WR_PNTR_WIDTH = "13" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) @@ -450,7 +450,7 @@ module iq_sample_fifo .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), - .data_count(NLW_U0_data_count_UNCONNECTED[9:0]), + .data_count(NLW_U0_data_count_UNCONNECTED[12:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout(dout), @@ -517,15 +517,15 @@ module iq_sample_fifo .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(NLW_U0_overflow_UNCONNECTED), .prog_empty(NLW_U0_prog_empty_UNCONNECTED), - .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full(NLW_U0_prog_full_UNCONNECTED), - .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), - .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]), + .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[12:0]), .rd_en(rd_en), .rd_rst(1'b0), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), @@ -594,7 +594,7 @@ module iq_sample_fifo .valid(NLW_U0_valid_UNCONNECTED), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), - .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]), + .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[12:0]), .wr_en(wr_en), .wr_rst(1'b0), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); @@ -603,40 +603,359 @@ endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module iq_sample_fifo_blk_mem_gen_generic_cstr (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - WEA, - E, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[9] , - din); + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input [0:0]WEA; - input [0:0]E; - input [9:0]Q; - input [9:0]\gc0.count_d1_reg[9] ; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; - wire [0:0]E; - wire [9:0]Q; + wire [12:0]Q; wire [0:0]WEA; wire [23:0]din; wire [23:0]dout; - wire [9:0]\gc0.count_d1_reg[9] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; + wire \ramloop[2].ram.r_n_0 ; + wire \ramloop[2].ram.r_n_1 ; + wire \ramloop[2].ram.r_n_2 ; + wire \ramloop[2].ram.r_n_3 ; + wire \ramloop[2].ram.r_n_4 ; + wire \ramloop[2].ram.r_n_5 ; + wire \ramloop[2].ram.r_n_6 ; + wire \ramloop[2].ram.r_n_7 ; + wire \ramloop[2].ram.r_n_8 ; + wire \ramloop[3].ram.r_n_0 ; + wire \ramloop[3].ram.r_n_1 ; + wire \ramloop[3].ram.r_n_2 ; + wire \ramloop[3].ram.r_n_3 ; + wire \ramloop[3].ram.r_n_4 ; + wire \ramloop[3].ram.r_n_5 ; + wire \ramloop[3].ram.r_n_6 ; + wire \ramloop[3].ram.r_n_7 ; + wire \ramloop[3].ram.r_n_8 ; + wire \ramloop[4].ram.r_n_0 ; + wire \ramloop[4].ram.r_n_1 ; + wire \ramloop[4].ram.r_n_2 ; + wire \ramloop[4].ram.r_n_3 ; + wire \ramloop[4].ram.r_n_4 ; + wire \ramloop[4].ram.r_n_5 ; + wire \ramloop[4].ram.r_n_6 ; + wire \ramloop[4].ram.r_n_7 ; + wire \ramloop[4].ram.r_n_8 ; + wire \ramloop[5].ram.r_n_0 ; + wire \ramloop[5].ram.r_n_1 ; + wire \ramloop[5].ram.r_n_2 ; + wire \ramloop[5].ram.r_n_3 ; + wire \ramloop[5].ram.r_n_4 ; + wire \ramloop[5].ram.r_n_5 ; + wire \ramloop[5].ram.r_n_6 ; + wire \ramloop[5].ram.r_n_7 ; + wire \ramloop[5].ram.r_n_8 ; wire rd_clk; wire wr_clk; + iq_sample_fifo_blk_mem_gen_mux__parameterized0 \has_mux_b.B + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\ramloop[2].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\ramloop[5].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_8 ), + .DOBDO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .DOPBDOP(\ramloop[3].ram.r_n_8 ), + .dout(dout[23:6]), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .rd_clk(rd_clk)); iq_sample_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r - (.E(E), - .Q(Q), + (.Q(Q), .WEA(WEA), - .din(din), - .dout(dout), - .\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ), + .din(din[1:0]), + .dout(dout[1:0]), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .wr_clk(wr_clk)); + iq_sample_fifo_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r + (.Q(Q), + .WEA(WEA), + .din(din[5:2]), + .dout(dout[5:2]), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + iq_sample_fifo_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[14:6]), + .\dout[13] ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }), + .\dout[14] (\ramloop[2].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + iq_sample_fifo_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r + (.DOBDO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .DOPBDOP(\ramloop[3].ram.r_n_8 ), + .Q(Q[11:0]), + .WEA(WEA), + .din(din[14:6]), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + iq_sample_fifo_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[23:15]), + .\dout[22] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\dout[23] (\ramloop[4].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + iq_sample_fifo_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[23:15]), + .\dout[22] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\dout[23] (\ramloop[5].ram.r_n_8 ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_mux" *) +module iq_sample_fifo_blk_mem_gen_mux__parameterized0 + (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 , + dout, + \gc0.count_d1_reg[12] , + rd_clk, + DOBDO, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + DOPBDOP, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ); + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ; + output [17:0]dout; + input \gc0.count_d1_reg[12] ; + input rd_clk; + input [7:0]DOBDO; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + input [0:0]DOPBDOP; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; + + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [17:0]dout; + wire \gc0.count_d1_reg[12] ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ; + wire rd_clk; + + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hAC)) + \dout[10]_INST_0 + (.I0(DOBDO[4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[4])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hAC)) + \dout[11]_INST_0 + (.I0(DOBDO[5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[5])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hAC)) + \dout[12]_INST_0 + (.I0(DOBDO[6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[6])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hAC)) + \dout[13]_INST_0 + (.I0(DOBDO[7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[7])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hAC)) + \dout[14]_INST_0 + (.I0(DOPBDOP), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[8])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hAC)) + \dout[15]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [0]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[9])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \dout[16]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [1]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[10])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \dout[17]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [2]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[11])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \dout[18]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [3]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[12])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \dout[19]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [4]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[13])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \dout[20]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [5]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[14])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \dout[21]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [6]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[15])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \dout[22]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [7]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[16])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \dout[23]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[17])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hAC)) + \dout[6]_INST_0 + (.I0(DOBDO[0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[0])); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'hAC)) + \dout[7]_INST_0 + (.I0(DOBDO[1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[1])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hAC)) + \dout[8]_INST_0 + (.I0(DOBDO[2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[2])); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hAC)) + \dout[9]_INST_0 + (.I0(DOBDO[3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]), + .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .O(dout[3])); + FDRE #( + .INIT(1'b0)) + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(\gc0.count_d1_reg[12] ), + .Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .R(1'b0)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) @@ -644,36 +963,271 @@ module iq_sample_fifo_blk_mem_gen_prim_width (dout, wr_clk, rd_clk, - WEA, - E, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[9] , - din); - output [23:0]dout; + \gc0.count_d1_reg[12] , + din, + WEA); + output [1:0]dout; input wr_clk; input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [1:0]din; input [0:0]WEA; - input [0:0]E; - input [9:0]Q; - input [9:0]\gc0.count_d1_reg[9] ; - input [23:0]din; - wire [0:0]E; - wire [9:0]Q; + wire [12:0]Q; wire [0:0]WEA; - wire [23:0]din; - wire [23:0]dout; - wire [9:0]\gc0.count_d1_reg[9] ; + wire [1:0]din; + wire [1:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; wire rd_clk; wire wr_clk; iq_sample_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram - (.E(E), - .Q(Q), + (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module iq_sample_fifo_blk_mem_gen_prim_width__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA); + output [3:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [3:0]din; + input [0:0]WEA; + + wire [12:0]Q; + wire [0:0]WEA; + wire [3:0]din; + wire [3:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module iq_sample_fifo_blk_mem_gen_prim_width__parameterized1 + (\dout[13] , + \dout[14] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[13] ; + output [0:0]\dout[14] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[13] ; + wire [0:0]\dout[14] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[13] (\dout[13] ), + .\dout[14] (\dout[14] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module iq_sample_fifo_blk_mem_gen_prim_width__parameterized2 + (DOBDO, + DOPBDOP, + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]DOBDO; + output [0:0]DOPBDOP; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram + (.DOBDO(DOBDO), + .DOPBDOP(DOPBDOP), + .Q(Q), + .WEA(WEA), + .din(din), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module iq_sample_fifo_blk_mem_gen_prim_width__parameterized3 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[22] (\dout[22] ), + .\dout[23] (\dout[23] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module iq_sample_fifo_blk_mem_gen_prim_width__parameterized4 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[22] (\dout[22] ), + .\dout[23] (\dout[23] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule @@ -683,38 +1237,191 @@ module iq_sample_fifo_blk_mem_gen_prim_wrapper (dout, wr_clk, rd_clk, - WEA, - E, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[9] , - din); - output [23:0]dout; + \gc0.count_d1_reg[12] , + din, + WEA); + output [1:0]dout; input wr_clk; input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [1:0]din; input [0:0]WEA; - input [0:0]E; - input [9:0]Q; - input [9:0]\gc0.count_d1_reg[9] ; - input [23:0]din; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ; - wire [0:0]E; - wire [9:0]Q; + wire [12:0]Q; wire [0:0]WEA; - wire [23:0]din; - wire [23:0]dout; - wire [9:0]\gc0.count_d1_reg[9] ; + wire [1:0]din; + wire [1:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; + wire [15:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; + wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; + wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB18E1 #( + .DOA_REG(0), + .DOB_REG(0), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(18'h00000), + .INIT_B(18'h00000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(2), + .READ_WIDTH_B(2), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(18'h00000), + .SRVAL_B(18'h00000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(2), + .WRITE_WIDTH_B(2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram + (.ADDRARDADDR({Q,1'b0}), + .ADDRBWRADDR({\gc0.count_d1_reg[12] ,1'b0}), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:2],dout}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .WEA({WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[12] , + din, + WEA); + output [3:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; + input [3:0]din; + input [0:0]WEA; + + wire [12:0]Q; + wire [0:0]WEA; + wire [3:0]din; + wire [3:0]dout; + wire [12:0]\gc0.count_d1_reg[12] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; wire rd_clk; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; @@ -722,7 +1429,9 @@ module iq_sample_fifo_blk_mem_gen_prim_wrapper wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; @@ -892,8 +1601,8 @@ module iq_sample_fifo_blk_mem_gen_prim_wrapper .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(36), - .READ_WIDTH_B(36), + .READ_WIDTH_A(4), + .READ_WIDTH_B(4), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), @@ -902,11 +1611,11 @@ module iq_sample_fifo_blk_mem_gen_prim_wrapper .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(36), - .WRITE_WIDTH_B(36)) + .WRITE_WIDTH_A(4), + .WRITE_WIDTH_B(4)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}), + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[12] ,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), @@ -914,17 +1623,1045 @@ module iq_sample_fifo_blk_mem_gen_prim_wrapper .CLKARDCLK(wr_clk), .CLKBWRCLK(rd_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,din[23:18],1'b0,1'b0,din[17:12],1'b0,1'b0,din[11:6],1'b0,1'b0,din[5:0]}), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), - .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ,dout[23:18],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ,dout[17:12],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ,dout[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,dout[5:0]}), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:4],dout}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), - .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(WEA), - .ENBWREN(E), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized1 + (\dout[13] , + \dout[14] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[13] ; + output [0:0]\dout[14] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[13] ; + wire [0:0]\dout[14] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[13] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[14] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized2 + (DOBDO, + DOPBDOP, + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]DOBDO; + output [0:0]DOPBDOP; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],DOBDO}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized3 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[22] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[23] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module iq_sample_fifo_blk_mem_gen_prim_wrapper__parameterized4 + (\dout[22] , + \dout[23] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[22] ; + output [0:0]\dout[23] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[22] ; + wire [0:0]\dout[23] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[22] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[23] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), @@ -942,38 +2679,66 @@ endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module iq_sample_fifo_blk_mem_gen_top (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - WEA, - E, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[9] , - din); + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input [0:0]WEA; - input [0:0]E; - input [9:0]Q; - input [9:0]\gc0.count_d1_reg[9] ; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; - wire [0:0]E; - wire [9:0]Q; + wire [12:0]Q; wire [0:0]WEA; wire [23:0]din; wire [23:0]dout; - wire [9:0]\gc0.count_d1_reg[9] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; iq_sample_fifo_blk_mem_gen_generic_cstr \valid.cstr - (.E(E), - .Q(Q), + (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule @@ -981,38 +2746,66 @@ endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4" *) module iq_sample_fifo_blk_mem_gen_v8_3_4 (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - WEA, - E, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[9] , - din); + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input [0:0]WEA; - input [0:0]E; - input [9:0]Q; - input [9:0]\gc0.count_d1_reg[9] ; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; - wire [0:0]E; - wire [9:0]Q; + wire [12:0]Q; wire [0:0]WEA; wire [23:0]din; wire [23:0]dout; - wire [9:0]\gc0.count_d1_reg[9] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; iq_sample_fifo_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen - (.E(E), - .Q(Q), + (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule @@ -1020,67 +2813,106 @@ endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4_synth" *) module iq_sample_fifo_blk_mem_gen_v8_3_4_synth (dout, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - WEA, - E, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[9] , - din); + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); output [23:0]dout; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input [0:0]WEA; - input [0:0]E; - input [9:0]Q; - input [9:0]\gc0.count_d1_reg[9] ; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; - wire [0:0]E; - wire [9:0]Q; + wire [12:0]Q; wire [0:0]WEA; wire [23:0]din; wire [23:0]dout; - wire [9:0]\gc0.count_d1_reg[9] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; iq_sample_fifo_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen - (.E(E), - .Q(Q), + (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "clk_x_pntrs" *) module iq_sample_fifo_clk_x_pntrs - (v1_reg, - v1_reg_0, + (ram_full_i_reg, RD_PNTR_WR, + ram_full_i_reg_0, + WR_PNTR_RD, Q, - \gc0.count_reg[9] , - \gic0.gc0.count_d2_reg[9] , + D, rd_clk, - wr_clk); - output [4:0]v1_reg; - output [4:0]v1_reg_0; - output [9:0]RD_PNTR_WR; - input [9:0]Q; - input [9:0]\gc0.count_reg[9] ; - input [9:0]\gic0.gc0.count_d2_reg[9] ; + wr_clk, + \gic0.gc0.count_d2_reg[12] , + bin2gray, + I6); + output ram_full_i_reg; + output [11:0]RD_PNTR_WR; + output ram_full_i_reg_0; + output [12:0]WR_PNTR_RD; + input [0:0]Q; + input [0:0]D; input rd_clk; input wr_clk; + input [0:0]\gic0.gc0.count_d2_reg[12] ; + input [11:0]bin2gray; + input [12:0]I6; - wire [9:0]Q; - wire [9:0]RD_PNTR_WR; - wire [8:0]bin2gray; - wire [9:0]\gc0.count_reg[9] ; - wire [9:0]\gic0.gc0.count_d2_reg[9] ; + wire [0:0]D; + wire [12:0]I6; + wire [0:0]Q; + wire [11:0]RD_PNTR_WR; + wire [12:0]WR_PNTR_RD; + wire [11:0]bin2gray; + wire [0:0]\gic0.gc0.count_d2_reg[12] ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ; @@ -1089,109 +2921,32 @@ module iq_sample_fifo_clk_x_pntrs wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ; - wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ; - wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ; - wire [7:0]gray2bin; + wire [10:0]gray2bin; wire p_0_out; - wire [9:0]p_22_out; - wire [9:0]p_3_out; - wire [9:0]p_4_out; - wire [9:9]p_5_out; - wire [9:9]p_6_out; + wire [12:12]p_23_out; + wire [12:0]p_3_out; + wire [12:0]p_4_out; + wire [12:12]p_5_out; + wire [12:12]p_6_out; + wire ram_full_i_reg; + wire ram_full_i_reg_0; wire rd_clk; - wire [9:0]rd_pntr_gc; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; + wire [12:0]rd_pntr_gc; wire wr_clk; - wire [9:0]wr_pntr_gc; + wire [12:0]wr_pntr_gc; - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1 - (.I0(p_22_out[0]), - .I1(Q[0]), - .I2(p_22_out[1]), - .I3(Q[1]), - .O(v1_reg[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__0 - (.I0(p_22_out[0]), - .I1(\gc0.count_reg[9] [0]), - .I2(p_22_out[1]), - .I3(\gc0.count_reg[9] [1]), - .O(v1_reg_0[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1 - (.I0(p_22_out[2]), - .I1(Q[2]), - .I2(p_22_out[3]), - .I3(Q[3]), - .O(v1_reg[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__0 - (.I0(p_22_out[2]), - .I1(\gc0.count_reg[9] [2]), - .I2(p_22_out[3]), - .I3(\gc0.count_reg[9] [3]), - .O(v1_reg_0[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1 - (.I0(p_22_out[4]), - .I1(Q[4]), - .I2(p_22_out[5]), - .I3(Q[5]), - .O(v1_reg[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__0 - (.I0(p_22_out[4]), - .I1(\gc0.count_reg[9] [4]), - .I2(p_22_out[5]), - .I3(\gc0.count_reg[9] [5]), - .O(v1_reg_0[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1 - (.I0(p_22_out[6]), - .I1(Q[6]), - .I2(p_22_out[7]), - .I3(Q[7]), - .O(v1_reg[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__0 - (.I0(p_22_out[6]), - .I1(\gc0.count_reg[9] [6]), - .I2(p_22_out[7]), - .I3(\gc0.count_reg[9] [7]), - .O(v1_reg_0[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1 - (.I0(p_22_out[8]), - .I1(Q[8]), - .I2(p_22_out[9]), - .I3(Q[9]), - .O(v1_reg[4])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1__0 - (.I0(p_22_out[8]), - .I1(\gc0.count_reg[9] [8]), - .I2(p_22_out[9]), - .I3(\gc0.count_reg[9] [9]), - .O(v1_reg_0[4])); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1 + (.I0(p_23_out), + .I1(Q), + .O(ram_full_i_reg)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1__0 + (.I0(p_23_out), + .I1(D), + .O(ram_full_i_reg_0)); iq_sample_fifo_synchronizer_ff \gnxpm_cdc.gsync_stage[1].rd_stg_inst (.in0(wr_pntr_gc), .out(p_3_out), @@ -1202,12 +2957,12 @@ module iq_sample_fifo_clk_x_pntrs .wr_clk(wr_clk)); iq_sample_fifo_synchronizer_ff_4 \gnxpm_cdc.gsync_stage[2].rd_stg_inst (.D({p_0_out,gray2bin}), - .\gnxpm_cdc.wr_pntr_bin_reg[9] (p_5_out), + .\gnxpm_cdc.wr_pntr_bin_reg[12] (p_5_out), .out(p_3_out), .rd_clk(rd_clk)); iq_sample_fifo_synchronizer_ff_5 \gnxpm_cdc.gsync_stage[2].wr_stg_inst - (.D({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 }), - .\gnxpm_cdc.rd_pntr_bin_reg[9] (p_6_out), + (.D({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 }), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (p_6_out), .out(p_4_out), .wr_clk(wr_clk)); FDRE #( @@ -1215,15 +2970,39 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[0] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ), .Q(RD_PNTR_WR[0]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), + .Q(RD_PNTR_WR[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), + .Q(RD_PNTR_WR[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(p_6_out), + .Q(p_23_out), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[1] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ), .Q(RD_PNTR_WR[1]), .R(1'b0)); FDRE #( @@ -1231,7 +3010,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[2] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ), .Q(RD_PNTR_WR[2]), .R(1'b0)); FDRE #( @@ -1239,7 +3018,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[3] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ), .Q(RD_PNTR_WR[3]), .R(1'b0)); FDRE #( @@ -1247,7 +3026,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[4] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), .Q(RD_PNTR_WR[4]), .R(1'b0)); FDRE #( @@ -1255,7 +3034,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[5] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), .Q(RD_PNTR_WR[5]), .R(1'b0)); FDRE #( @@ -1263,7 +3042,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[6] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), .Q(RD_PNTR_WR[6]), .R(1'b0)); FDRE #( @@ -1271,7 +3050,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[7] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), .Q(RD_PNTR_WR[7]), .R(1'b0)); FDRE #( @@ -1279,7 +3058,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[8] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), .Q(RD_PNTR_WR[8]), .R(1'b0)); FDRE #( @@ -1287,85 +3066,47 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[9] (.C(wr_clk), .CE(1'b1), - .D(p_6_out), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), .Q(RD_PNTR_WR[9]), .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[0]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[1]_i_1 - (.I0(Q[1]), - .I1(Q[2]), - .O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[2]_i_1 - (.I0(Q[2]), - .I1(Q[3]), - .O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[3]_i_1 - (.I0(Q[3]), - .I1(Q[4]), - .O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[4]_i_1 - (.I0(Q[4]), - .I1(Q[5]), - .O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[5]_i_1 - (.I0(Q[5]), - .I1(Q[6]), - .O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[6]_i_1 - (.I0(Q[6]), - .I1(Q[7]), - .O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[7]_i_1 - (.I0(Q[7]), - .I1(Q[8]), - .O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 )); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[8]_i_1 - (.I0(Q[8]), - .I1(Q[9]), - .O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[0] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ), + .D(I6[0]), .Q(rd_pntr_gc[0]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(I6[10]), + .Q(rd_pntr_gc[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(I6[11]), + .Q(rd_pntr_gc[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(I6[12]), + .Q(rd_pntr_gc[12]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[1] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ), + .D(I6[1]), .Q(rd_pntr_gc[1]), .R(1'b0)); FDRE #( @@ -1373,7 +3114,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[2] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ), + .D(I6[2]), .Q(rd_pntr_gc[2]), .R(1'b0)); FDRE #( @@ -1381,7 +3122,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[3] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ), + .D(I6[3]), .Q(rd_pntr_gc[3]), .R(1'b0)); FDRE #( @@ -1389,7 +3130,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[4] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ), + .D(I6[4]), .Q(rd_pntr_gc[4]), .R(1'b0)); FDRE #( @@ -1397,7 +3138,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[5] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ), + .D(I6[5]), .Q(rd_pntr_gc[5]), .R(1'b0)); FDRE #( @@ -1405,7 +3146,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[6] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ), + .D(I6[6]), .Q(rd_pntr_gc[6]), .R(1'b0)); FDRE #( @@ -1413,7 +3154,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[7] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ), + .D(I6[7]), .Q(rd_pntr_gc[7]), .R(1'b0)); FDRE #( @@ -1421,7 +3162,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[8] (.C(rd_clk), .CE(1'b1), - .D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ), + .D(I6[8]), .Q(rd_pntr_gc[8]), .R(1'b0)); FDRE #( @@ -1429,7 +3170,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[9] (.C(rd_clk), .CE(1'b1), - .D(Q[9]), + .D(I6[9]), .Q(rd_pntr_gc[9]), .R(1'b0)); FDRE #( @@ -1438,7 +3179,31 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[0]), - .Q(p_22_out[0]), + .Q(WR_PNTR_RD[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(gray2bin[10]), + .Q(WR_PNTR_RD[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(p_0_out), + .Q(WR_PNTR_RD[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(p_5_out), + .Q(WR_PNTR_RD[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -1446,7 +3211,7 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[1]), - .Q(p_22_out[1]), + .Q(WR_PNTR_RD[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -1454,7 +3219,7 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[2]), - .Q(p_22_out[2]), + .Q(WR_PNTR_RD[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -1462,7 +3227,7 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[3]), - .Q(p_22_out[3]), + .Q(WR_PNTR_RD[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -1470,7 +3235,7 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[4]), - .Q(p_22_out[4]), + .Q(WR_PNTR_RD[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -1478,7 +3243,7 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[5]), - .Q(p_22_out[5]), + .Q(WR_PNTR_RD[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -1486,7 +3251,7 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[6]), - .Q(p_22_out[6]), + .Q(WR_PNTR_RD[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -1494,86 +3259,24 @@ module iq_sample_fifo_clk_x_pntrs (.C(rd_clk), .CE(1'b1), .D(gray2bin[7]), - .Q(p_22_out[7]), + .Q(WR_PNTR_RD[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[8] (.C(rd_clk), .CE(1'b1), - .D(p_0_out), - .Q(p_22_out[8]), + .D(gray2bin[8]), + .Q(WR_PNTR_RD[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[9] (.C(rd_clk), .CE(1'b1), - .D(p_5_out), - .Q(p_22_out[9]), + .D(gray2bin[9]), + .Q(WR_PNTR_RD[9]), .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[0]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [0]), - .I1(\gic0.gc0.count_d2_reg[9] [1]), - .O(bin2gray[0])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[1]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [1]), - .I1(\gic0.gc0.count_d2_reg[9] [2]), - .O(bin2gray[1])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[2]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [2]), - .I1(\gic0.gc0.count_d2_reg[9] [3]), - .O(bin2gray[2])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[3]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [3]), - .I1(\gic0.gc0.count_d2_reg[9] [4]), - .O(bin2gray[3])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[4]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [4]), - .I1(\gic0.gc0.count_d2_reg[9] [5]), - .O(bin2gray[4])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[5]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [5]), - .I1(\gic0.gc0.count_d2_reg[9] [6]), - .O(bin2gray[5])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[6]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [6]), - .I1(\gic0.gc0.count_d2_reg[9] [7]), - .O(bin2gray[6])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[7]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [7]), - .I1(\gic0.gc0.count_d2_reg[9] [8]), - .O(bin2gray[7])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[8]_i_1 - (.I0(\gic0.gc0.count_d2_reg[9] [8]), - .I1(\gic0.gc0.count_d2_reg[9] [9]), - .O(bin2gray[8])); FDRE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[0] @@ -1582,6 +3285,30 @@ module iq_sample_fifo_clk_x_pntrs .D(bin2gray[0]), .Q(wr_pntr_gc[0]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[10]), + .Q(wr_pntr_gc[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(bin2gray[11]), + .Q(wr_pntr_gc[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(\gic0.gc0.count_d2_reg[12] ), + .Q(wr_pntr_gc[12]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[1] @@ -1651,7 +3378,7 @@ module iq_sample_fifo_clk_x_pntrs \gnxpm_cdc.wr_pntr_gc_reg[9] (.C(wr_clk), .CE(1'b1), - .D(\gic0.gc0.count_d2_reg[9] [9]), + .D(bin2gray[9]), .Q(wr_pntr_gc[9]), .R(1'b0)); endmodule @@ -1659,31 +3386,40 @@ endmodule (* ORIG_REF_NAME = "compare" *) module iq_sample_fifo_compare (ram_full_i_reg, - v1_reg, + \gnxpm_cdc.rd_pntr_bin_reg[12] , wr_en, out, - comp2); + comp2, + \gic0.gc0.count_d1_reg[11] , + RD_PNTR_WR); output ram_full_i_reg; - input [4:0]v1_reg; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; input wr_en; input out; input comp2; + input [11:0]\gic0.gc0.count_d1_reg[11] ; + input [11:0]RD_PNTR_WR; + wire [11:0]RD_PNTR_WR; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; + wire carrynet_4; + wire carrynet_5; wire comp1; wire comp2; + wire [11:0]\gic0.gc0.count_d1_reg[11] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; wire out; wire ram_full_i_reg; - wire [4:0]v1_reg; + wire [5:0]v1_reg; wire wr_en; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) @@ -1694,15 +3430,63 @@ module iq_sample_fifo_compare .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [0]), + .I1(RD_PNTR_WR[0]), + .I2(\gic0.gc0.count_d1_reg[11] [1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [2]), + .I1(RD_PNTR_WR[2]), + .I2(\gic0.gc0.count_d1_reg[11] [3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [4]), + .I1(RD_PNTR_WR[4]), + .I2(\gic0.gc0.count_d1_reg[11] [5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [6]), + .I1(RD_PNTR_WR[6]), + .I2(\gic0.gc0.count_d1_reg[11] [7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp1,carrynet_5,carrynet_4}), .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]})); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gnxpm_cdc.rd_pntr_bin_reg[12] ,v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [8]), + .I1(RD_PNTR_WR[8]), + .I2(\gic0.gc0.count_d1_reg[11] [9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(\gic0.gc0.count_d1_reg[11] [10]), + .I1(RD_PNTR_WR[10]), + .I2(\gic0.gc0.count_d1_reg[11] [11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); LUT4 #( .INIT(16'hAEAA)) ram_full_i_i_1 @@ -1716,70 +3500,30 @@ endmodule (* ORIG_REF_NAME = "compare" *) module iq_sample_fifo_compare_0 (comp2, - v1_reg_0); + \gnxpm_cdc.rd_pntr_bin_reg[12] , + D, + RD_PNTR_WR); output comp2; - input [4:0]v1_reg_0; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; + input [11:0]D; + input [11:0]RD_PNTR_WR; + wire [11:0]D; + wire [11:0]RD_PNTR_WR; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; + wire carrynet_4; + wire carrynet_5; wire comp2; - wire [4:0]v1_reg_0; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; + wire [5:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; - - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[0].gm1.m1_CARRY4 - (.CI(1'b0), - .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), - .CYINIT(1'b1), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S(v1_reg_0[3:0])); - (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) - (* box_type = "PRIMITIVE" *) - CARRY4 \gmux.gm[4].gms.ms_CARRY4 - (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}), - .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), - .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]})); -endmodule - -(* ORIG_REF_NAME = "compare" *) -module iq_sample_fifo_compare_1 - (ram_empty_fb_i_reg, - v1_reg, - rd_en, - out, - comp1); - output ram_empty_fb_i_reg; - input [4:0]v1_reg; - input rd_en; - input out; - input comp1; - - wire carrynet_0; - wire carrynet_1; - wire carrynet_2; - wire carrynet_3; - wire comp0; - wire comp1; - wire out; - wire ram_empty_fb_i_reg; - wire rd_en; - wire [4:0]v1_reg; - wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; - wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) @@ -1790,43 +3534,92 @@ module iq_sample_fifo_compare_1 .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(D[0]), + .I1(RD_PNTR_WR[0]), + .I2(D[1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(D[2]), + .I1(RD_PNTR_WR[2]), + .I2(D[3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(D[4]), + .I1(RD_PNTR_WR[4]), + .I2(D[5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(D[6]), + .I1(RD_PNTR_WR[6]), + .I2(D[7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp2,carrynet_5,carrynet_4}), .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]})); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gnxpm_cdc.rd_pntr_bin_reg[12] ,v1_reg[5:4]})); LUT4 #( - .INIT(16'hAEAA)) - ram_empty_i_i_1 - (.I0(comp0), - .I1(rd_en), - .I2(out), - .I3(comp1), - .O(ram_empty_fb_i_reg)); + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(D[8]), + .I1(RD_PNTR_WR[8]), + .I2(D[9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(D[10]), + .I1(RD_PNTR_WR[10]), + .I2(D[11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); endmodule (* ORIG_REF_NAME = "compare" *) -module iq_sample_fifo_compare_2 - (comp1, - v1_reg_0); - output comp1; - input [4:0]v1_reg_0; +module iq_sample_fifo_compare_1 + (comp0, + \gc0.count_d1_reg[12] , + WR_PNTR_RD, + Q); + output comp0; + input \gc0.count_d1_reg[12] ; + input [11:0]WR_PNTR_RD; + input [11:0]Q; + wire [11:0]Q; + wire [11:0]WR_PNTR_RD; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; - wire comp1; - wire [4:0]v1_reg_0; + wire carrynet_4; + wire carrynet_5; + wire comp0; + wire \gc0.count_d1_reg[12] ; + wire [5:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; - wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) @@ -1836,16 +3629,160 @@ module iq_sample_fifo_compare_2 .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S(v1_reg_0[3:0])); + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(Q[0]), + .I2(WR_PNTR_RD[1]), + .I3(Q[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(Q[2]), + .I2(WR_PNTR_RD[3]), + .I3(Q[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(Q[4]), + .I2(WR_PNTR_RD[5]), + .I3(Q[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(Q[6]), + .I2(WR_PNTR_RD[7]), + .I3(Q[7]), + .O(v1_reg[3])); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 (.CI(carrynet_3), - .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp0,carrynet_5,carrynet_4}), .CYINIT(1'b0), - .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]})); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gc0.count_d1_reg[12] ,v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(Q[8]), + .I2(WR_PNTR_RD[9]), + .I3(Q[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(Q[10]), + .I2(WR_PNTR_RD[11]), + .I3(Q[11]), + .O(v1_reg[5])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module iq_sample_fifo_compare_2 + (comp1, + \gc0.count_reg[12] , + WR_PNTR_RD, + D); + output comp1; + input \gc0.count_reg[12] ; + input [11:0]WR_PNTR_RD; + input [11:0]D; + + wire [11:0]D; + wire [11:0]WR_PNTR_RD; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire carrynet_5; + wire comp1; + wire \gc0.count_reg[12] ; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(D[0]), + .I2(WR_PNTR_RD[1]), + .I3(D[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(D[2]), + .I2(WR_PNTR_RD[3]), + .I3(D[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(D[4]), + .I2(WR_PNTR_RD[5]), + .I3(D[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(D[6]), + .I2(WR_PNTR_RD[7]), + .I3(D[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3],comp1,carrynet_5,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gc0.count_reg[12] ,v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(D[8]), + .I2(WR_PNTR_RD[9]), + .I3(D[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(D[10]), + .I2(WR_PNTR_RD[11]), + .I3(D[11]), + .O(v1_reg[5])); endmodule (* ORIG_REF_NAME = "fifo_generator_ramfifo" *) @@ -1867,56 +3804,99 @@ module iq_sample_fifo_fifo_generator_ramfifo input rd_clk; input [23:0]din; + wire [11:0]bin2gray; wire [23:0]din; wire [23:0]dout; wire empty; wire full; + wire [1:1]\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; + wire [1:1]\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; + wire \gntv_or_sync_fifo.gcx.clkx_n_0 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_13 ; wire \gntv_or_sync_fifo.gl0.rd_n_1 ; + wire \gntv_or_sync_fifo.gl0.rd_n_15 ; + wire \gntv_or_sync_fifo.gl0.rd_n_16 ; + wire \gntv_or_sync_fifo.gl0.rd_n_17 ; + wire \gntv_or_sync_fifo.gl0.rd_n_18 ; + wire \gntv_or_sync_fifo.gl0.rd_n_19 ; + wire \gntv_or_sync_fifo.gl0.rd_n_20 ; + wire \gntv_or_sync_fifo.gl0.rd_n_21 ; + wire \gntv_or_sync_fifo.gl0.rd_n_22 ; + wire \gntv_or_sync_fifo.gl0.rd_n_23 ; + wire \gntv_or_sync_fifo.gl0.rd_n_24 ; + wire \gntv_or_sync_fifo.gl0.rd_n_25 ; + wire \gntv_or_sync_fifo.gl0.rd_n_26 ; + wire \gntv_or_sync_fifo.gl0.rd_n_27 ; + wire \gntv_or_sync_fifo.gl0.rd_n_29 ; wire \gntv_or_sync_fifo.gl0.wr_n_1 ; - wire [4:0]\gras.rsts/c0/v1_reg ; - wire [4:0]\gras.rsts/c1/v1_reg ; - wire [9:0]p_0_out; - wire [9:0]p_12_out; - wire [9:0]p_23_out; + wire \gntv_or_sync_fifo.gl0.wr_n_15 ; + wire \gntv_or_sync_fifo.gl0.wr_n_31 ; + wire [12:0]p_0_out; + wire [12:0]p_12_out; + wire [12:12]p_13_out; + wire [12:0]p_22_out; + wire [11:0]p_23_out; wire rd_clk; wire rd_en; - wire [9:0]rd_pntr_plus1; + wire sel_pipe; wire wr_clk; wire wr_en; + wire [12:12]wr_pntr_plus2; iq_sample_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx - (.Q(p_0_out), + (.D(wr_pntr_plus2), + .I6({p_0_out[12],\gntv_or_sync_fifo.gl0.rd_n_16 ,\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 ,\gntv_or_sync_fifo.gl0.rd_n_26 ,\gntv_or_sync_fifo.gl0.rd_n_27 }), + .Q(p_13_out), .RD_PNTR_WR(p_23_out), - .\gc0.count_reg[9] (rd_pntr_plus1), - .\gic0.gc0.count_d2_reg[9] (p_12_out), + .WR_PNTR_RD(p_22_out), + .bin2gray(bin2gray), + .\gic0.gc0.count_d2_reg[12] (p_12_out[12]), + .ram_full_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ), + .ram_full_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_13 ), .rd_clk(rd_clk), - .v1_reg(\gras.rsts/c0/v1_reg ), - .v1_reg_0(\gras.rsts/c1/v1_reg ), .wr_clk(wr_clk)); iq_sample_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_0_out), - .E(\gntv_or_sync_fifo.gl0.rd_n_1 ), - .Q(rd_pntr_plus1), + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.rd_n_1 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.rd_n_29 ), + .I6({\gntv_or_sync_fifo.gl0.rd_n_16 ,\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 ,\gntv_or_sync_fifo.gl0.rd_n_26 ,\gntv_or_sync_fifo.gl0.rd_n_27 }), + .Q(p_0_out), + .WR_PNTR_RD(p_22_out), .empty(empty), + .enb_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_15 ), .rd_clk(rd_clk), .rd_en(rd_en), - .v1_reg(\gras.rsts/c0/v1_reg ), - .v1_reg_0(\gras.rsts/c1/v1_reg )); + .sel_pipe(sel_pipe)); iq_sample_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr - (.Q(p_12_out), + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.wr_n_1 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.wr_n_31 ), + .Q(p_12_out), .RD_PNTR_WR(p_23_out), - .WEA(\gntv_or_sync_fifo.gl0.wr_n_1 ), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_15 ), + .bin2gray(bin2gray), + .ena_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ), .full(full), + .\gic0.gc0.count_d2_reg[12] (p_13_out), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gntv_or_sync_fifo.gcx.clkx_n_0 ), + .\gnxpm_cdc.rd_pntr_bin_reg[12]_0 (\gntv_or_sync_fifo.gcx.clkx_n_13 ), .wr_clk(wr_clk), .wr_en(wr_en)); iq_sample_fifo_memory \gntv_or_sync_fifo.mem - (.E(\gntv_or_sync_fifo.gl0.rd_n_1 ), - .Q(p_12_out), - .WEA(\gntv_or_sync_fifo.gl0.wr_n_1 ), + (.Q(p_12_out), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_15 ), .din(din), .dout(dout), - .\gc0.count_d1_reg[9] (p_0_out), + .ena_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ), + .enb_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ), + .\gc0.count_d1_reg[12] (p_0_out), + .\gc0.count_d1_reg[12]_0 (\gntv_or_sync_fifo.gl0.rd_n_15 ), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_29 ), + .ram_empty_fb_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_1 ), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_31 ), + .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_1 ), .rd_clk(rd_clk), + .sel_pipe(sel_pipe), .wr_clk(wr_clk)); endmodule @@ -1968,7 +3948,7 @@ endmodule (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) -(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "24" *) +(* C_DATA_COUNT_WIDTH = "13" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "24" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "24" *) (* C_ENABLE_RLOCS = "0" *) @@ -1996,7 +3976,7 @@ endmodule (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) -(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *) +(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "8kx4" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) @@ -2004,13 +3984,13 @@ endmodule (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) -(* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL = "8189" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) -(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *) (* C_PROG_FULL_TYPE = "0" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "8188" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) -(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *) -(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *) +(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "13" *) +(* C_RD_DEPTH = "8192" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "13" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) @@ -2020,10 +4000,10 @@ endmodule (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) -(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *) -(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) +(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "13" *) +(* C_WR_DEPTH = "8192" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) -(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *) +(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "13" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_2" *) @@ -2271,12 +4251,12 @@ module iq_sample_fifo_fifo_generator_v13_1_2 input [23:0]din; input wr_en; input rd_en; - input [9:0]prog_empty_thresh; - input [9:0]prog_empty_thresh_assert; - input [9:0]prog_empty_thresh_negate; - input [9:0]prog_full_thresh; - input [9:0]prog_full_thresh_assert; - input [9:0]prog_full_thresh_negate; + input [12:0]prog_empty_thresh; + input [12:0]prog_empty_thresh_assert; + input [12:0]prog_empty_thresh_negate; + input [12:0]prog_full_thresh; + input [12:0]prog_full_thresh_assert; + input [12:0]prog_full_thresh_negate; input int_clk; input injectdbiterr; input injectsbiterr; @@ -2290,9 +4270,9 @@ module iq_sample_fifo_fifo_generator_v13_1_2 output almost_empty; output valid; output underflow; - output [9:0]data_count; - output [9:0]rd_data_count; - output [9:0]wr_data_count; + output [12:0]data_count; + output [12:0]rd_data_count; + output [12:0]wr_data_count; output prog_full; output prog_empty; output sbiterr; @@ -2684,6 +4664,9 @@ module iq_sample_fifo_fifo_generator_v13_1_2 assign axis_wr_data_count[2] = \ ; assign axis_wr_data_count[1] = \ ; assign axis_wr_data_count[0] = \ ; + assign data_count[12] = \ ; + assign data_count[11] = \ ; + assign data_count[10] = \ ; assign data_count[9] = \ ; assign data_count[8] = \ ; assign data_count[7] = \ ; @@ -2922,6 +4905,9 @@ module iq_sample_fifo_fifo_generator_v13_1_2 assign overflow = \ ; assign prog_empty = \ ; assign prog_full = \ ; + assign rd_data_count[12] = \ ; + assign rd_data_count[11] = \ ; + assign rd_data_count[10] = \ ; assign rd_data_count[9] = \ ; assign rd_data_count[8] = \ ; assign rd_data_count[7] = \ ; @@ -3016,6 +5002,9 @@ module iq_sample_fifo_fifo_generator_v13_1_2 assign underflow = \ ; assign valid = \ ; assign wr_ack = \ ; + assign wr_data_count[12] = \ ; + assign wr_data_count[11] = \ ; + assign wr_data_count[10] = \ ; assign wr_data_count[9] = \ ; assign wr_data_count[8] = \ ; assign wr_data_count[7] = \ ; @@ -3084,398 +5073,713 @@ endmodule (* ORIG_REF_NAME = "memory" *) module iq_sample_fifo_memory (dout, + sel_pipe, wr_clk, rd_clk, - WEA, - E, + ram_full_fb_i_reg, + ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[9] , - din); + \gc0.count_d1_reg[12] , + din, + WEA, + ram_full_fb_i_reg_0, + ram_empty_fb_i_reg_0, + ena_array, + enb_array, + \gc0.count_d1_reg[12]_0 ); output [23:0]dout; + output sel_pipe; input wr_clk; input rd_clk; - input [0:0]WEA; - input [0:0]E; - input [9:0]Q; - input [9:0]\gc0.count_d1_reg[9] ; + input ram_full_fb_i_reg; + input ram_empty_fb_i_reg; + input [12:0]Q; + input [12:0]\gc0.count_d1_reg[12] ; input [23:0]din; + input [0:0]WEA; + input ram_full_fb_i_reg_0; + input ram_empty_fb_i_reg_0; + input [0:0]ena_array; + input [0:0]enb_array; + input \gc0.count_d1_reg[12]_0 ; - wire [0:0]E; - wire [9:0]Q; + wire [12:0]Q; wire [0:0]WEA; wire [23:0]din; wire [23:0]dout; - wire [9:0]\gc0.count_d1_reg[9] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [12:0]\gc0.count_d1_reg[12] ; + wire \gc0.count_d1_reg[12]_0 ; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; wire rd_clk; + wire sel_pipe; wire wr_clk; iq_sample_fifo_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg - (.E(E), - .Q(Q), + (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (sel_pipe), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module iq_sample_fifo_rd_bin_cntr - (Q, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + (D, + ram_empty_fb_i_reg, + Q, + ram_empty_fb_i_reg_0, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + enb_array, + I6, E, - rd_clk); - output [9:0]Q; - output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + rd_clk, + WR_PNTR_RD, + rd_en, + out, + sel_pipe); + output [11:0]D; + output ram_empty_fb_i_reg; + output [12:0]Q; + output ram_empty_fb_i_reg_0; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + output [0:0]enb_array; + output [11:0]I6; input [0:0]E; input rd_clk; + input [0:0]WR_PNTR_RD; + input rd_en; + input out; + input sel_pipe; - wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [11:0]D; wire [0:0]E; - wire [9:0]Q; - wire \gc0.count[9]_i_2_n_0 ; - wire [9:0]plusOp; + wire [11:0]I6; + wire [12:0]Q; + wire [0:0]WR_PNTR_RD; + wire [0:0]enb_array; + wire \gc0.count[0]_i_2_n_0 ; + wire \gc0.count[0]_i_3_n_0 ; + wire \gc0.count[0]_i_4_n_0 ; + wire \gc0.count[0]_i_5_n_0 ; + wire \gc0.count[12]_i_2_n_0 ; + wire \gc0.count[4]_i_2_n_0 ; + wire \gc0.count[4]_i_3_n_0 ; + wire \gc0.count[4]_i_4_n_0 ; + wire \gc0.count[4]_i_5_n_0 ; + wire \gc0.count[8]_i_2_n_0 ; + wire \gc0.count[8]_i_3_n_0 ; + wire \gc0.count[8]_i_4_n_0 ; + wire \gc0.count[8]_i_5_n_0 ; + wire \gc0.count_reg[0]_i_1_n_0 ; + wire \gc0.count_reg[0]_i_1_n_1 ; + wire \gc0.count_reg[0]_i_1_n_2 ; + wire \gc0.count_reg[0]_i_1_n_3 ; + wire \gc0.count_reg[0]_i_1_n_4 ; + wire \gc0.count_reg[0]_i_1_n_5 ; + wire \gc0.count_reg[0]_i_1_n_6 ; + wire \gc0.count_reg[0]_i_1_n_7 ; + wire \gc0.count_reg[12]_i_1_n_7 ; + wire \gc0.count_reg[4]_i_1_n_0 ; + wire \gc0.count_reg[4]_i_1_n_1 ; + wire \gc0.count_reg[4]_i_1_n_2 ; + wire \gc0.count_reg[4]_i_1_n_3 ; + wire \gc0.count_reg[4]_i_1_n_4 ; + wire \gc0.count_reg[4]_i_1_n_5 ; + wire \gc0.count_reg[4]_i_1_n_6 ; + wire \gc0.count_reg[4]_i_1_n_7 ; + wire \gc0.count_reg[8]_i_1_n_0 ; + wire \gc0.count_reg[8]_i_1_n_1 ; + wire \gc0.count_reg[8]_i_1_n_2 ; + wire \gc0.count_reg[8]_i_1_n_3 ; + wire \gc0.count_reg[8]_i_1_n_4 ; + wire \gc0.count_reg[8]_i_1_n_5 ; + wire \gc0.count_reg[8]_i_1_n_6 ; + wire \gc0.count_reg[8]_i_1_n_7 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire out; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; wire rd_clk; + wire rd_en; + wire [12:12]rd_pntr_plus1; + wire sel_pipe; + wire [3:0]\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED ; + LUT3 #( + .INIT(8'h20)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 + (.I0(Q[12]), + .I1(out), + .I2(rd_en), + .O(enb_array)); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gc0.count[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) - \gc0.count[0]_i_1 - (.I0(Q[0]), - .O(plusOp[0])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT2 #( - .INIT(4'h6)) - \gc0.count[1]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT3 #( - .INIT(8'h78)) - \gc0.count[2]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .I2(Q[2]), - .O(plusOp[2])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT4 #( - .INIT(16'h7F80)) - \gc0.count[3]_i_1 - (.I0(Q[1]), - .I1(Q[0]), - .I2(Q[2]), - .I3(Q[3]), - .O(plusOp[3])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gc0.count[4]_i_1 - (.I0(Q[2]), - .I1(Q[0]), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[4]), - .O(plusOp[4])); - LUT6 #( - .INIT(64'h7FFFFFFF80000000)) - \gc0.count[5]_i_1 - (.I0(Q[3]), - .I1(Q[1]), - .I2(Q[0]), - .I3(Q[2]), - .I4(Q[4]), - .I5(Q[5]), - .O(plusOp[5])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT2 #( - .INIT(4'h6)) - \gc0.count[6]_i_1 - (.I0(\gc0.count[9]_i_2_n_0 ), - .I1(Q[6]), - .O(plusOp[6])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'h78)) - \gc0.count[7]_i_1 - (.I0(\gc0.count[9]_i_2_n_0 ), - .I1(Q[6]), - .I2(Q[7]), - .O(plusOp[7])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT4 #( - .INIT(16'h7F80)) - \gc0.count[8]_i_1 - (.I0(Q[6]), - .I1(\gc0.count[9]_i_2_n_0 ), - .I2(Q[7]), - .I3(Q[8]), - .O(plusOp[8])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gc0.count[9]_i_1 - (.I0(Q[7]), - .I1(\gc0.count[9]_i_2_n_0 ), - .I2(Q[6]), - .I3(Q[8]), - .I4(Q[9]), - .O(plusOp[9])); - LUT6 #( - .INIT(64'h8000000000000000)) - \gc0.count[9]_i_2 - (.I0(Q[5]), - .I1(Q[3]), - .I2(Q[1]), - .I3(Q[0]), - .I4(Q[2]), - .I5(Q[4]), - .O(\gc0.count[9]_i_2_n_0 )); + \gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[12]_i_2 + (.I0(rd_pntr_plus1), + .O(\gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gc0.count[8]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[0] (.C(rd_clk), .CE(E), - .D(Q[0]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]), + .D(D[0]), + .Q(Q[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[10] + (.C(rd_clk), + .CE(E), + .D(D[10]), + .Q(Q[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[11] + (.C(rd_clk), + .CE(E), + .D(D[11]), + .Q(Q[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[12] + (.C(rd_clk), + .CE(E), + .D(rd_pntr_plus1), + .Q(Q[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(rd_clk), .CE(E), - .D(Q[1]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]), + .D(D[1]), + .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(rd_clk), .CE(E), - .D(Q[2]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]), + .D(D[2]), + .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(rd_clk), .CE(E), - .D(Q[3]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]), + .D(D[3]), + .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[4] (.C(rd_clk), .CE(E), - .D(Q[4]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), + .D(D[4]), + .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[5] (.C(rd_clk), .CE(E), - .D(Q[5]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]), + .D(D[5]), + .Q(Q[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[6] (.C(rd_clk), .CE(E), - .D(Q[6]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]), + .D(D[6]), + .Q(Q[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[7] (.C(rd_clk), .CE(E), - .D(Q[7]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]), + .D(D[7]), + .Q(Q[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[8] (.C(rd_clk), .CE(E), - .D(Q[8]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]), + .D(D[8]), + .Q(Q[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[9] (.C(rd_clk), .CE(E), - .D(Q[9]), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]), + .D(D[9]), + .Q(Q[9]), .R(1'b0)); FDRE #( .INIT(1'b1)) \gc0.count_reg[0] (.C(rd_clk), .CE(E), - .D(plusOp[0]), - .Q(Q[0]), + .D(\gc0.count_reg[0]_i_1_n_7 ), + .Q(D[0]), .R(1'b0)); + CARRY4 \gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gc0.count_reg[0]_i_1_n_0 ,\gc0.count_reg[0]_i_1_n_1 ,\gc0.count_reg[0]_i_1_n_2 ,\gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gc0.count_reg[0]_i_1_n_4 ,\gc0.count_reg[0]_i_1_n_5 ,\gc0.count_reg[0]_i_1_n_6 ,\gc0.count_reg[0]_i_1_n_7 }), + .S({\gc0.count[0]_i_2_n_0 ,\gc0.count[0]_i_3_n_0 ,\gc0.count[0]_i_4_n_0 ,\gc0.count[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[10] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[11] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[12] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[12]_i_1_n_7 ), + .Q(rd_pntr_plus1), + .R(1'b0)); + CARRY4 \gc0.count_reg[12]_i_1 + (.CI(\gc0.count_reg[8]_i_1_n_0 ), + .CO(\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED [3:1],\gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,\gc0.count[12]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \gc0.count_reg[1] (.C(rd_clk), .CE(E), - .D(plusOp[1]), - .Q(Q[1]), + .D(\gc0.count_reg[0]_i_1_n_6 ), + .Q(D[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_reg[2] (.C(rd_clk), .CE(E), - .D(plusOp[2]), - .Q(Q[2]), + .D(\gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_reg[3] (.C(rd_clk), .CE(E), - .D(plusOp[3]), - .Q(Q[3]), + .D(\gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_reg[4] (.C(rd_clk), .CE(E), - .D(plusOp[4]), - .Q(Q[4]), + .D(\gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4]), .R(1'b0)); + CARRY4 \gc0.count_reg[4]_i_1 + (.CI(\gc0.count_reg[0]_i_1_n_0 ), + .CO({\gc0.count_reg[4]_i_1_n_0 ,\gc0.count_reg[4]_i_1_n_1 ,\gc0.count_reg[4]_i_1_n_2 ,\gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[4]_i_1_n_4 ,\gc0.count_reg[4]_i_1_n_5 ,\gc0.count_reg[4]_i_1_n_6 ,\gc0.count_reg[4]_i_1_n_7 }), + .S({\gc0.count[4]_i_2_n_0 ,\gc0.count[4]_i_3_n_0 ,\gc0.count[4]_i_4_n_0 ,\gc0.count[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \gc0.count_reg[5] (.C(rd_clk), .CE(E), - .D(plusOp[5]), - .Q(Q[5]), + .D(\gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_reg[6] (.C(rd_clk), .CE(E), - .D(plusOp[6]), - .Q(Q[6]), + .D(\gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_reg[7] (.C(rd_clk), .CE(E), - .D(plusOp[7]), - .Q(Q[7]), + .D(\gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_reg[8] (.C(rd_clk), .CE(E), - .D(plusOp[8]), - .Q(Q[8]), + .D(\gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8]), .R(1'b0)); + CARRY4 \gc0.count_reg[8]_i_1 + (.CI(\gc0.count_reg[4]_i_1_n_0 ), + .CO({\gc0.count_reg[8]_i_1_n_0 ,\gc0.count_reg[8]_i_1_n_1 ,\gc0.count_reg[8]_i_1_n_2 ,\gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[8]_i_1_n_4 ,\gc0.count_reg[8]_i_1_n_5 ,\gc0.count_reg[8]_i_1_n_6 ,\gc0.count_reg[8]_i_1_n_7 }), + .S({\gc0.count[8]_i_2_n_0 ,\gc0.count[8]_i_3_n_0 ,\gc0.count[8]_i_4_n_0 ,\gc0.count[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \gc0.count_reg[9] (.C(rd_clk), .CE(E), - .D(plusOp[9]), - .Q(Q[9]), + .D(\gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9]), .R(1'b0)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1__1 + (.I0(Q[12]), + .I1(WR_PNTR_RD), + .O(ram_empty_fb_i_reg)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[6].gms.ms_i_1__2 + (.I0(rd_pntr_plus1), + .I1(WR_PNTR_RD), + .O(ram_empty_fb_i_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[0]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(I6[0])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[10]_i_1 + (.I0(Q[10]), + .I1(Q[11]), + .O(I6[10])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[11]_i_1 + (.I0(Q[11]), + .I1(Q[12]), + .O(I6[11])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[1]_i_1 + (.I0(Q[1]), + .I1(Q[2]), + .O(I6[1])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[2]_i_1 + (.I0(Q[2]), + .I1(Q[3]), + .O(I6[2])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[3]_i_1 + (.I0(Q[3]), + .I1(Q[4]), + .O(I6[3])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[4]_i_1 + (.I0(Q[4]), + .I1(Q[5]), + .O(I6[4])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[5]_i_1 + (.I0(Q[5]), + .I1(Q[6]), + .O(I6[5])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[6]_i_1 + (.I0(Q[6]), + .I1(Q[7]), + .O(I6[6])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[7]_i_1 + (.I0(Q[7]), + .I1(Q[8]), + .O(I6[7])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[8]_i_1 + (.I0(Q[8]), + .I1(Q[9]), + .O(I6[8])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[9]_i_1 + (.I0(Q[9]), + .I1(Q[10]), + .O(I6[9])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'hFB08)) + \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1 + (.I0(Q[12]), + .I1(rd_en), + .I2(out), + .I3(sel_pipe), + .O(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] )); endmodule (* ORIG_REF_NAME = "rd_logic" *) module iq_sample_fifo_rd_logic (empty, - E, - Q, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , - v1_reg, - v1_reg_0, + Q, + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , + I6, + enb_array, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , rd_clk, - rd_en); + rd_en, + WR_PNTR_RD, + sel_pipe); output empty; - output [0:0]E; - output [9:0]Q; - output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - input [4:0]v1_reg; - input [4:0]v1_reg_0; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [12:0]Q; + output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + output [11:0]I6; + output [0:0]enb_array; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; input rd_clk; input rd_en; + input [12:0]WR_PNTR_RD; + input sel_pipe; - wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - wire [0:0]E; - wire [9:0]Q; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [11:0]I6; + wire [12:0]Q; + wire [12:0]WR_PNTR_RD; wire empty; + wire [0:0]enb_array; + wire \gras.rsts_n_3 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire p_2_out; wire rd_clk; wire rd_en; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; + wire [11:0]rd_pntr_plus1; + wire rpntr_n_12; + wire rpntr_n_26; + wire sel_pipe; iq_sample_fifo_rd_status_flags_as \gras.rsts - (.E(E), + (.D(rd_pntr_plus1), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .E(\gras.rsts_n_3 ), + .Q(Q), + .WR_PNTR_RD(WR_PNTR_RD[11:0]), .empty(empty), + .\gc0.count_d1_reg[12] (rpntr_n_12), + .\gc0.count_reg[12] (rpntr_n_26), + .out(p_2_out), + .rd_clk(rd_clk), + .rd_en(rd_en)); + iq_sample_fifo_rd_bin_cntr rpntr + (.D(rd_pntr_plus1), + .E(\gras.rsts_n_3 ), + .I6(I6), + .Q(Q), + .WR_PNTR_RD(WR_PNTR_RD[12]), + .enb_array(enb_array), + .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .out(p_2_out), + .ram_empty_fb_i_reg(rpntr_n_12), + .ram_empty_fb_i_reg_0(rpntr_n_26), .rd_clk(rd_clk), .rd_en(rd_en), - .v1_reg(v1_reg), - .v1_reg_0(v1_reg_0)); - iq_sample_fifo_rd_bin_cntr rpntr - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), - .E(E), - .Q(Q), - .rd_clk(rd_clk)); + .sel_pipe(sel_pipe)); endmodule (* ORIG_REF_NAME = "rd_status_flags_as" *) module iq_sample_fifo_rd_status_flags_as (empty, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , E, - v1_reg, - v1_reg_0, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \gc0.count_d1_reg[12] , + \gc0.count_reg[12] , rd_clk, - rd_en); + rd_en, + Q, + WR_PNTR_RD, + D); output empty; + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; output [0:0]E; - input [4:0]v1_reg; - input [4:0]v1_reg_0; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input \gc0.count_d1_reg[12] ; + input \gc0.count_reg[12] ; input rd_clk; input rd_en; + input [12:0]Q; + input [11:0]WR_PNTR_RD; + input [11:0]D; + wire [11:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; wire [0:0]E; - wire c0_n_0; + wire [12:0]Q; + wire [11:0]WR_PNTR_RD; + wire comp0; wire comp1; + wire \gc0.count_d1_reg[12] ; + wire \gc0.count_reg[12] ; (* DONT_TOUCH *) wire ram_empty_fb_i; (* DONT_TOUCH *) wire ram_empty_i; + wire ram_empty_i_reg0_n_0; wire rd_clk; wire rd_en; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; assign empty = ram_empty_i; + assign out = ram_empty_fb_i; LUT2 #( .INIT(4'h2)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0 + (.I0(rd_en), + .I1(ram_empty_fb_i), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); + LUT3 #( + .INIT(8'h04)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1 + (.I0(ram_empty_fb_i), + .I1(rd_en), + .I2(Q[12]), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); + iq_sample_fifo_compare_1 c0 + (.Q(Q[11:0]), + .WR_PNTR_RD(WR_PNTR_RD), + .comp0(comp0), + .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] )); + iq_sample_fifo_compare_2 c1 + (.D(D), + .WR_PNTR_RD(WR_PNTR_RD), + .comp1(comp1), + .\gc0.count_reg[12] (\gc0.count_reg[12] )); + LUT2 #( + .INIT(4'h2)) + \gc0.count_d1[12]_i_1 (.I0(rd_en), .I1(ram_empty_fb_i), .O(E)); - iq_sample_fifo_compare_1 c0 - (.comp1(comp1), - .out(ram_empty_fb_i), - .ram_empty_fb_i_reg(c0_n_0), - .rd_en(rd_en), - .v1_reg(v1_reg)); - iq_sample_fifo_compare_2 c1 - (.comp1(comp1), - .v1_reg_0(v1_reg_0)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) @@ -3484,7 +5788,7 @@ module iq_sample_fifo_rd_status_flags_as ram_empty_fb_i_reg (.C(rd_clk), .CE(1'b1), - .D(c0_n_0), + .D(ram_empty_i_reg0_n_0), .Q(ram_empty_fb_i), .R(1'b0)); (* DONT_TOUCH *) @@ -3495,9 +5799,17 @@ module iq_sample_fifo_rd_status_flags_as ram_empty_i_reg (.C(rd_clk), .CE(1'b1), - .D(c0_n_0), + .D(ram_empty_i_reg0_n_0), .Q(ram_empty_i), .R(1'b0)); + LUT4 #( + .INIT(16'hAEAA)) + ram_empty_i_reg0 + (.I0(comp0), + .I1(rd_en), + .I2(ram_empty_fb_i), + .I3(comp1), + .O(ram_empty_i_reg0_n_0)); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) @@ -3505,15 +5817,15 @@ module iq_sample_fifo_synchronizer_ff (out, in0, rd_clk); - output [9:0]out; - input [9:0]in0; + output [12:0]out; + input [12:0]in0; input rd_clk; - (* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg; - wire [9:0]in0; + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire [12:0]in0; wire rd_clk; - assign out[9:0] = Q_reg; + assign out[12:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -3528,6 +5840,39 @@ module iq_sample_fifo_synchronizer_ff (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(in0[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(in0[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(in0[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -3631,15 +5976,15 @@ module iq_sample_fifo_synchronizer_ff_3 (out, Q, wr_clk); - output [9:0]out; - input [9:0]Q; + output [12:0]out; + input [12:0]Q; input wr_clk; - wire [9:0]Q; - (* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg; + wire [12:0]Q; + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; wire wr_clk; - assign out[9:0] = Q_reg; + assign out[12:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -3654,6 +5999,39 @@ module iq_sample_fifo_synchronizer_ff_3 (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(Q[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(Q[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(Q[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -3754,24 +6132,23 @@ endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module iq_sample_fifo_synchronizer_ff_4 - (\gnxpm_cdc.wr_pntr_bin_reg[9] , + (\gnxpm_cdc.wr_pntr_bin_reg[12] , D, out, rd_clk); - output [0:0]\gnxpm_cdc.wr_pntr_bin_reg[9] ; - output [8:0]D; - input [9:0]out; + output [0:0]\gnxpm_cdc.wr_pntr_bin_reg[12] ; + output [11:0]D; + input [12:0]out; input rd_clk; - wire [8:0]D; - (* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg; - wire \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ; + wire [11:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ; wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ; - wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ; - wire [9:0]out; + wire [12:0]out; wire rd_clk; - assign \gnxpm_cdc.wr_pntr_bin_reg[9] [0] = Q_reg[9]; + assign \gnxpm_cdc.wr_pntr_bin_reg[12] [0] = Q_reg[12]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -3786,6 +6163,39 @@ module iq_sample_fifo_synchronizer_ff_4 (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .D(out[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .D(out[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(rd_clk), + .CE(1'b1), + .D(out[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -3882,127 +6292,147 @@ module iq_sample_fifo_synchronizer_ff_4 .D(out[9]), .Q(Q_reg[9]), .R(1'b0)); - LUT5 #( - .INIT(32'h96696996)) + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[0]_i_1 - (.I0(Q_reg[1]), - .I1(Q_reg[0]), - .I2(Q_reg[2]), - .I3(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ), - .I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), + (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[1]), + .I2(Q_reg[0]), + .I3(Q_reg[3]), + .I4(Q_reg[2]), + .I5(D[7]), .O(D[0])); LUT3 #( .INIT(8'h96)) - \gnxpm_cdc.wr_pntr_bin[0]_i_2 - (.I0(Q_reg[4]), - .I1(Q_reg[3]), - .I2(Q_reg[9]), - .O(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 )); - LUT6 #( - .INIT(64'h6996966996696996)) - \gnxpm_cdc.wr_pntr_bin[1]_i_1 - (.I0(Q_reg[2]), - .I1(Q_reg[9]), - .I2(Q_reg[3]), - .I3(Q_reg[4]), - .I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), - .I5(Q_reg[1]), - .O(D[1])); + \gnxpm_cdc.wr_pntr_bin[10]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[10]), + .I2(Q_reg[12]), + .O(D[10])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[11]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[12]), + .O(D[11])); LUT5 #( .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[2]), + .I2(Q_reg[1]), + .I3(Q_reg[3]), + .I4(D[7]), + .O(D[1])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[1]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[4]), + .I2(Q_reg[6]), + .O(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[2]_i_1 (.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), - .I1(Q_reg[4]), - .I2(Q_reg[3]), - .I3(Q_reg[9]), - .I4(Q_reg[2]), - .O(D[2])); - LUT4 #( - .INIT(16'h6996)) - \gnxpm_cdc.wr_pntr_bin[2]_i_2 - (.I0(Q_reg[8]), .I1(Q_reg[7]), - .I2(Q_reg[6]), - .I3(Q_reg[5]), + .I2(Q_reg[3]), + .I3(Q_reg[2]), + .I4(Q_reg[4]), + .I5(D[8]), + .O(D[2])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[2]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[6]), .O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[3]_i_1 - (.I0(Q_reg[9]), - .I1(Q_reg[3]), + (.I0(Q_reg[6]), + .I1(Q_reg[7]), .I2(Q_reg[4]), - .I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ), - .I4(Q_reg[7]), - .I5(Q_reg[8]), + .I3(Q_reg[3]), + .I4(Q_reg[5]), + .I5(D[8]), .O(D[3])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_bin[3]_i_2 - (.I0(Q_reg[5]), - .I1(Q_reg[6]), - .O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[4]_i_1 - (.I0(Q_reg[6]), - .I1(Q_reg[4]), + (.I0(Q_reg[7]), + .I1(Q_reg[8]), .I2(Q_reg[5]), - .I3(Q_reg[9]), - .I4(Q_reg[7]), - .I5(Q_reg[8]), + .I3(Q_reg[4]), + .I4(Q_reg[6]), + .I5(D[9]), .O(D[4])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[5]_i_1 (.I0(Q_reg[7]), - .I1(Q_reg[5]), - .I2(Q_reg[6]), - .I3(Q_reg[9]), - .I4(Q_reg[8]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[6]), + .I4(D[9]), .O(D[5])); - LUT4 #( - .INIT(16'h6996)) + LUT5 #( + .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[6]_i_1 - (.I0(Q_reg[7]), - .I1(Q_reg[6]), - .I2(Q_reg[9]), - .I3(Q_reg[8]), - .O(D[6])); - LUT3 #( - .INIT(8'h96)) - \gnxpm_cdc.wr_pntr_bin[7]_i_1 - (.I0(Q_reg[8]), - .I1(Q_reg[7]), - .I2(Q_reg[9]), - .O(D[7])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_bin[8]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[9]), + .I2(Q_reg[6]), + .I3(Q_reg[7]), + .I4(D[10]), + .O(D[6])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[7]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[7]), + .I2(Q_reg[8]), + .I3(Q_reg[12]), + .I4(Q_reg[10]), + .I5(Q_reg[11]), + .O(D[7])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[8]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[12]), + .I4(Q_reg[11]), .O(D[8])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.wr_pntr_bin[9]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[12]), + .I3(Q_reg[11]), + .O(D[9])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) module iq_sample_fifo_synchronizer_ff_5 - (\gnxpm_cdc.rd_pntr_bin_reg[9] , + (\gnxpm_cdc.rd_pntr_bin_reg[12] , D, out, wr_clk); - output [0:0]\gnxpm_cdc.rd_pntr_bin_reg[9] ; - output [8:0]D; - input [9:0]out; + output [0:0]\gnxpm_cdc.rd_pntr_bin_reg[12] ; + output [11:0]D; + input [12:0]out; input wr_clk; - wire [8:0]D; - (* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg; - wire \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ; + wire [11:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ; wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ; - wire \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ; - wire [9:0]out; + wire [12:0]out; wire wr_clk; - assign \gnxpm_cdc.rd_pntr_bin_reg[9] [0] = Q_reg[9]; + assign \gnxpm_cdc.rd_pntr_bin_reg[12] [0] = Q_reg[12]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -4017,6 +6447,39 @@ module iq_sample_fifo_synchronizer_ff_5 (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .D(out[10]), + .Q(Q_reg[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .D(out[11]), + .Q(Q_reg[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(out[12]), + .Q(Q_reg[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -4113,629 +6576,851 @@ module iq_sample_fifo_synchronizer_ff_5 .D(out[9]), .Q(Q_reg[9]), .R(1'b0)); - LUT5 #( - .INIT(32'h96696996)) + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[0]_i_1 - (.I0(Q_reg[1]), - .I1(Q_reg[0]), - .I2(Q_reg[2]), - .I3(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ), - .I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ), + (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[1]), + .I2(Q_reg[0]), + .I3(Q_reg[3]), + .I4(Q_reg[2]), + .I5(D[7]), .O(D[0])); LUT3 #( .INIT(8'h96)) - \gnxpm_cdc.rd_pntr_bin[0]_i_2 - (.I0(Q_reg[4]), - .I1(Q_reg[3]), - .I2(Q_reg[9]), - .O(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 )); - LUT6 #( - .INIT(64'h6996966996696996)) - \gnxpm_cdc.rd_pntr_bin[1]_i_1 - (.I0(Q_reg[2]), - .I1(Q_reg[9]), - .I2(Q_reg[3]), - .I3(Q_reg[4]), - .I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ), - .I5(Q_reg[1]), - .O(D[1])); + \gnxpm_cdc.rd_pntr_bin[10]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[10]), + .I2(Q_reg[12]), + .O(D[10])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[11]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[12]), + .O(D[11])); LUT5 #( .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[2]), + .I2(Q_reg[1]), + .I3(Q_reg[3]), + .I4(D[7]), + .O(D[1])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.rd_pntr_bin[1]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[4]), + .I2(Q_reg[6]), + .O(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[2]_i_1 (.I0(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ), - .I1(Q_reg[4]), - .I2(Q_reg[3]), - .I3(Q_reg[9]), - .I4(Q_reg[2]), - .O(D[2])); - LUT4 #( - .INIT(16'h6996)) - \gnxpm_cdc.rd_pntr_bin[2]_i_2 - (.I0(Q_reg[8]), .I1(Q_reg[7]), - .I2(Q_reg[6]), - .I3(Q_reg[5]), + .I2(Q_reg[3]), + .I3(Q_reg[2]), + .I4(Q_reg[4]), + .I5(D[8]), + .O(D[2])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[2]_i_2 + (.I0(Q_reg[5]), + .I1(Q_reg[6]), .O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[3]_i_1 - (.I0(Q_reg[9]), - .I1(Q_reg[3]), + (.I0(Q_reg[6]), + .I1(Q_reg[7]), .I2(Q_reg[4]), - .I3(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ), - .I4(Q_reg[7]), - .I5(Q_reg[8]), + .I3(Q_reg[3]), + .I4(Q_reg[5]), + .I5(D[8]), .O(D[3])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_bin[3]_i_2 - (.I0(Q_reg[5]), - .I1(Q_reg[6]), - .O(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[4]_i_1 - (.I0(Q_reg[6]), - .I1(Q_reg[4]), + (.I0(Q_reg[7]), + .I1(Q_reg[8]), .I2(Q_reg[5]), - .I3(Q_reg[9]), - .I4(Q_reg[7]), - .I5(Q_reg[8]), + .I3(Q_reg[4]), + .I4(Q_reg[6]), + .I5(D[9]), .O(D[4])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[5]_i_1 (.I0(Q_reg[7]), - .I1(Q_reg[5]), - .I2(Q_reg[6]), - .I3(Q_reg[9]), - .I4(Q_reg[8]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[6]), + .I4(D[9]), .O(D[5])); - LUT4 #( - .INIT(16'h6996)) + LUT5 #( + .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[6]_i_1 - (.I0(Q_reg[7]), - .I1(Q_reg[6]), - .I2(Q_reg[9]), - .I3(Q_reg[8]), - .O(D[6])); - LUT3 #( - .INIT(8'h96)) - \gnxpm_cdc.rd_pntr_bin[7]_i_1 - (.I0(Q_reg[8]), - .I1(Q_reg[7]), - .I2(Q_reg[9]), - .O(D[7])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_bin[8]_i_1 (.I0(Q_reg[8]), .I1(Q_reg[9]), + .I2(Q_reg[6]), + .I3(Q_reg[7]), + .I4(D[10]), + .O(D[6])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[7]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[7]), + .I2(Q_reg[8]), + .I3(Q_reg[12]), + .I4(Q_reg[10]), + .I5(Q_reg[11]), + .O(D[7])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[8]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[12]), + .I4(Q_reg[11]), .O(D[8])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[9]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[12]), + .I3(Q_reg[11]), + .O(D[9])); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) module iq_sample_fifo_wr_bin_cntr - (Q, - v1_reg, - v1_reg_0, - E, + (D, + ena_array, + Q, + \gic0.gc0.count_d2_reg[12]_0 , + bin2gray, + ram_full_fb_i_reg, wr_clk, - RD_PNTR_WR); - output [9:0]Q; - output [4:0]v1_reg; - output [4:0]v1_reg_0; - input [0:0]E; + out, + wr_en); + output [12:0]D; + output [0:0]ena_array; + output [12:0]Q; + output [12:0]\gic0.gc0.count_d2_reg[12]_0 ; + output [11:0]bin2gray; + input ram_full_fb_i_reg; input wr_clk; - input [9:0]RD_PNTR_WR; + input out; + input wr_en; - wire [0:0]E; - wire [9:0]Q; - wire [9:0]RD_PNTR_WR; - wire \gic0.gc0.count[9]_i_2_n_0 ; - wire [9:0]p_13_out; - wire [9:0]plusOp__0; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; + wire [12:0]D; + wire [12:0]Q; + wire [11:0]bin2gray; + wire [0:0]ena_array; + wire \gic0.gc0.count[0]_i_2_n_0 ; + wire \gic0.gc0.count[0]_i_3_n_0 ; + wire \gic0.gc0.count[0]_i_4_n_0 ; + wire \gic0.gc0.count[0]_i_5_n_0 ; + wire \gic0.gc0.count[12]_i_2_n_0 ; + wire \gic0.gc0.count[4]_i_2_n_0 ; + wire \gic0.gc0.count[4]_i_3_n_0 ; + wire \gic0.gc0.count[4]_i_4_n_0 ; + wire \gic0.gc0.count[4]_i_5_n_0 ; + wire \gic0.gc0.count[8]_i_2_n_0 ; + wire \gic0.gc0.count[8]_i_3_n_0 ; + wire \gic0.gc0.count[8]_i_4_n_0 ; + wire \gic0.gc0.count[8]_i_5_n_0 ; + wire [12:0]\gic0.gc0.count_d2_reg[12]_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_1 ; + wire \gic0.gc0.count_reg[0]_i_1_n_2 ; + wire \gic0.gc0.count_reg[0]_i_1_n_3 ; + wire \gic0.gc0.count_reg[0]_i_1_n_4 ; + wire \gic0.gc0.count_reg[0]_i_1_n_5 ; + wire \gic0.gc0.count_reg[0]_i_1_n_6 ; + wire \gic0.gc0.count_reg[0]_i_1_n_7 ; + wire \gic0.gc0.count_reg[12]_i_1_n_7 ; + wire \gic0.gc0.count_reg[4]_i_1_n_0 ; + wire \gic0.gc0.count_reg[4]_i_1_n_1 ; + wire \gic0.gc0.count_reg[4]_i_1_n_2 ; + wire \gic0.gc0.count_reg[4]_i_1_n_3 ; + wire \gic0.gc0.count_reg[4]_i_1_n_4 ; + wire \gic0.gc0.count_reg[4]_i_1_n_5 ; + wire \gic0.gc0.count_reg[4]_i_1_n_6 ; + wire \gic0.gc0.count_reg[4]_i_1_n_7 ; + wire \gic0.gc0.count_reg[8]_i_1_n_0 ; + wire \gic0.gc0.count_reg[8]_i_1_n_1 ; + wire \gic0.gc0.count_reg[8]_i_1_n_2 ; + wire \gic0.gc0.count_reg[8]_i_1_n_3 ; + wire \gic0.gc0.count_reg[8]_i_1_n_4 ; + wire \gic0.gc0.count_reg[8]_i_1_n_5 ; + wire \gic0.gc0.count_reg[8]_i_1_n_6 ; + wire \gic0.gc0.count_reg[8]_i_1_n_7 ; + wire out; + wire ram_full_fb_i_reg; wire wr_clk; - wire [9:0]wr_pntr_plus2; + wire wr_en; + wire [3:0]\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED ; + LUT3 #( + .INIT(8'h20)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 + (.I0(Q[12]), + .I1(out), + .I2(wr_en), + .O(ena_array)); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gic0.gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gic0.gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gic0.gc0.count[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) - \gic0.gc0.count[0]_i_1 - (.I0(wr_pntr_plus2[0]), - .O(plusOp__0[0])); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT2 #( - .INIT(4'h6)) - \gic0.gc0.count[1]_i_1 - (.I0(wr_pntr_plus2[0]), - .I1(wr_pntr_plus2[1]), - .O(plusOp__0[1])); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'h78)) - \gic0.gc0.count[2]_i_1 - (.I0(wr_pntr_plus2[0]), - .I1(wr_pntr_plus2[1]), - .I2(wr_pntr_plus2[2]), - .O(plusOp__0[2])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT4 #( - .INIT(16'h7F80)) - \gic0.gc0.count[3]_i_1 - (.I0(wr_pntr_plus2[1]), - .I1(wr_pntr_plus2[0]), - .I2(wr_pntr_plus2[2]), - .I3(wr_pntr_plus2[3]), - .O(plusOp__0[3])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gic0.gc0.count[4]_i_1 - (.I0(wr_pntr_plus2[2]), - .I1(wr_pntr_plus2[0]), - .I2(wr_pntr_plus2[1]), - .I3(wr_pntr_plus2[3]), - .I4(wr_pntr_plus2[4]), - .O(plusOp__0[4])); - LUT6 #( - .INIT(64'h7FFFFFFF80000000)) - \gic0.gc0.count[5]_i_1 - (.I0(wr_pntr_plus2[3]), - .I1(wr_pntr_plus2[1]), - .I2(wr_pntr_plus2[0]), - .I3(wr_pntr_plus2[2]), - .I4(wr_pntr_plus2[4]), - .I5(wr_pntr_plus2[5]), - .O(plusOp__0[5])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT2 #( - .INIT(4'h6)) - \gic0.gc0.count[6]_i_1 - (.I0(\gic0.gc0.count[9]_i_2_n_0 ), - .I1(wr_pntr_plus2[6]), - .O(plusOp__0[6])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'h78)) - \gic0.gc0.count[7]_i_1 - (.I0(\gic0.gc0.count[9]_i_2_n_0 ), - .I1(wr_pntr_plus2[6]), - .I2(wr_pntr_plus2[7]), - .O(plusOp__0[7])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT4 #( - .INIT(16'h7F80)) - \gic0.gc0.count[8]_i_1 - (.I0(wr_pntr_plus2[6]), - .I1(\gic0.gc0.count[9]_i_2_n_0 ), - .I2(wr_pntr_plus2[7]), - .I3(wr_pntr_plus2[8]), - .O(plusOp__0[8])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT5 #( - .INIT(32'h7FFF8000)) - \gic0.gc0.count[9]_i_1 - (.I0(wr_pntr_plus2[7]), - .I1(\gic0.gc0.count[9]_i_2_n_0 ), - .I2(wr_pntr_plus2[6]), - .I3(wr_pntr_plus2[8]), - .I4(wr_pntr_plus2[9]), - .O(plusOp__0[9])); - LUT6 #( - .INIT(64'h8000000000000000)) - \gic0.gc0.count[9]_i_2 - (.I0(wr_pntr_plus2[5]), - .I1(wr_pntr_plus2[3]), - .I2(wr_pntr_plus2[1]), - .I3(wr_pntr_plus2[0]), - .I4(wr_pntr_plus2[2]), - .I5(wr_pntr_plus2[4]), - .O(\gic0.gc0.count[9]_i_2_n_0 )); + \gic0.gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gic0.gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[12]_i_2 + (.I0(D[12]), + .O(\gic0.gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gic0.gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gic0.gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gic0.gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gic0.gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gic0.gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gic0.gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gic0.gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gic0.gc0.count[8]_i_5_n_0 )); FDRE #( .INIT(1'b1)) \gic0.gc0.count_d1_reg[0] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[0]), - .Q(p_13_out[0]), + .CE(ram_full_fb_i_reg), + .D(D[0]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[10]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[11]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[12] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[12]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[1] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[1]), - .Q(p_13_out[1]), + .CE(ram_full_fb_i_reg), + .D(D[1]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[2] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[2]), - .Q(p_13_out[2]), + .CE(ram_full_fb_i_reg), + .D(D[2]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[3] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[3]), - .Q(p_13_out[3]), + .CE(ram_full_fb_i_reg), + .D(D[3]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[4] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[4]), - .Q(p_13_out[4]), + .CE(ram_full_fb_i_reg), + .D(D[4]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[5] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[5]), - .Q(p_13_out[5]), + .CE(ram_full_fb_i_reg), + .D(D[5]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[6] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[6]), - .Q(p_13_out[6]), + .CE(ram_full_fb_i_reg), + .D(D[6]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[7] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[7]), - .Q(p_13_out[7]), + .CE(ram_full_fb_i_reg), + .D(D[7]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[8] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[8]), - .Q(p_13_out[8]), + .CE(ram_full_fb_i_reg), + .D(D[8]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[9] (.C(wr_clk), - .CE(E), - .D(wr_pntr_plus2[9]), - .Q(p_13_out[9]), + .CE(ram_full_fb_i_reg), + .D(D[9]), + .Q(\gic0.gc0.count_d2_reg[12]_0 [9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[0] (.C(wr_clk), - .CE(E), - .D(p_13_out[0]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [0]), .Q(Q[0]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [10]), + .Q(Q[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [11]), + .Q(Q[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[12] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [12]), + .Q(Q[12]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[1] (.C(wr_clk), - .CE(E), - .D(p_13_out[1]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[2] (.C(wr_clk), - .CE(E), - .D(p_13_out[2]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [2]), .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[3] (.C(wr_clk), - .CE(E), - .D(p_13_out[3]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [3]), .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[4] (.C(wr_clk), - .CE(E), - .D(p_13_out[4]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [4]), .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[5] (.C(wr_clk), - .CE(E), - .D(p_13_out[5]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [5]), .Q(Q[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[6] (.C(wr_clk), - .CE(E), - .D(p_13_out[6]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [6]), .Q(Q[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[7] (.C(wr_clk), - .CE(E), - .D(p_13_out[7]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [7]), .Q(Q[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[8] (.C(wr_clk), - .CE(E), - .D(p_13_out[8]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [8]), .Q(Q[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[9] (.C(wr_clk), - .CE(E), - .D(p_13_out[9]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_d2_reg[12]_0 [9]), .Q(Q[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[0] (.C(wr_clk), - .CE(E), - .D(plusOp__0[0]), - .Q(wr_pntr_plus2[0]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_7 ), + .Q(D[0]), .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gic0.gc0.count_reg[0]_i_1_n_0 ,\gic0.gc0.count_reg[0]_i_1_n_1 ,\gic0.gc0.count_reg[0]_i_1_n_2 ,\gic0.gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gic0.gc0.count_reg[0]_i_1_n_4 ,\gic0.gc0.count_reg[0]_i_1_n_5 ,\gic0.gc0.count_reg[0]_i_1_n_6 ,\gic0.gc0.count_reg[0]_i_1_n_7 }), + .S({\gic0.gc0.count[0]_i_2_n_0 ,\gic0.gc0.count[0]_i_3_n_0 ,\gic0.gc0.count[0]_i_4_n_0 ,\gic0.gc0.count[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[12] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[12]_i_1_n_7 ), + .Q(D[12]), + .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[12]_i_1 + (.CI(\gic0.gc0.count_reg[8]_i_1_n_0 ), + .CO(\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED [3:1],\gic0.gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,\gic0.gc0.count[12]_i_2_n_0 })); FDRE #( .INIT(1'b1)) \gic0.gc0.count_reg[1] (.C(wr_clk), - .CE(E), - .D(plusOp__0[1]), - .Q(wr_pntr_plus2[1]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_6 ), + .Q(D[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[2] (.C(wr_clk), - .CE(E), - .D(plusOp__0[2]), - .Q(wr_pntr_plus2[2]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[3] (.C(wr_clk), - .CE(E), - .D(plusOp__0[3]), - .Q(wr_pntr_plus2[3]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[4] (.C(wr_clk), - .CE(E), - .D(plusOp__0[4]), - .Q(wr_pntr_plus2[4]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4]), .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[4]_i_1 + (.CI(\gic0.gc0.count_reg[0]_i_1_n_0 ), + .CO({\gic0.gc0.count_reg[4]_i_1_n_0 ,\gic0.gc0.count_reg[4]_i_1_n_1 ,\gic0.gc0.count_reg[4]_i_1_n_2 ,\gic0.gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[4]_i_1_n_4 ,\gic0.gc0.count_reg[4]_i_1_n_5 ,\gic0.gc0.count_reg[4]_i_1_n_6 ,\gic0.gc0.count_reg[4]_i_1_n_7 }), + .S({\gic0.gc0.count[4]_i_2_n_0 ,\gic0.gc0.count[4]_i_3_n_0 ,\gic0.gc0.count[4]_i_4_n_0 ,\gic0.gc0.count[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[5] (.C(wr_clk), - .CE(E), - .D(plusOp__0[5]), - .Q(wr_pntr_plus2[5]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[6] (.C(wr_clk), - .CE(E), - .D(plusOp__0[6]), - .Q(wr_pntr_plus2[6]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[7] (.C(wr_clk), - .CE(E), - .D(plusOp__0[7]), - .Q(wr_pntr_plus2[7]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[8] (.C(wr_clk), - .CE(E), - .D(plusOp__0[8]), - .Q(wr_pntr_plus2[8]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8]), .R(1'b0)); + CARRY4 \gic0.gc0.count_reg[8]_i_1 + (.CI(\gic0.gc0.count_reg[4]_i_1_n_0 ), + .CO({\gic0.gc0.count_reg[8]_i_1_n_0 ,\gic0.gc0.count_reg[8]_i_1_n_1 ,\gic0.gc0.count_reg[8]_i_1_n_2 ,\gic0.gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[8]_i_1_n_4 ,\gic0.gc0.count_reg[8]_i_1_n_5 ,\gic0.gc0.count_reg[8]_i_1_n_6 ,\gic0.gc0.count_reg[8]_i_1_n_7 }), + .S({\gic0.gc0.count[8]_i_2_n_0 ,\gic0.gc0.count[8]_i_3_n_0 ,\gic0.gc0.count[8]_i_4_n_0 ,\gic0.gc0.count[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[9] (.C(wr_clk), - .CE(E), - .D(plusOp__0[9]), - .Q(wr_pntr_plus2[9]), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9]), .R(1'b0)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__1 - (.I0(p_13_out[0]), - .I1(RD_PNTR_WR[0]), - .I2(p_13_out[1]), - .I3(RD_PNTR_WR[1]), - .O(v1_reg[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__2 - (.I0(wr_pntr_plus2[0]), - .I1(RD_PNTR_WR[0]), - .I2(wr_pntr_plus2[1]), - .I3(RD_PNTR_WR[1]), - .O(v1_reg_0[0])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__1 - (.I0(p_13_out[2]), - .I1(RD_PNTR_WR[2]), - .I2(p_13_out[3]), - .I3(RD_PNTR_WR[3]), - .O(v1_reg[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__2 - (.I0(wr_pntr_plus2[2]), - .I1(RD_PNTR_WR[2]), - .I2(wr_pntr_plus2[3]), - .I3(RD_PNTR_WR[3]), - .O(v1_reg_0[1])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__1 - (.I0(p_13_out[4]), - .I1(RD_PNTR_WR[4]), - .I2(p_13_out[5]), - .I3(RD_PNTR_WR[5]), - .O(v1_reg[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__2 - (.I0(wr_pntr_plus2[4]), - .I1(RD_PNTR_WR[4]), - .I2(wr_pntr_plus2[5]), - .I3(RD_PNTR_WR[5]), - .O(v1_reg_0[2])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__1 - (.I0(p_13_out[6]), - .I1(RD_PNTR_WR[6]), - .I2(p_13_out[7]), - .I3(RD_PNTR_WR[7]), - .O(v1_reg[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__2 - (.I0(wr_pntr_plus2[6]), - .I1(RD_PNTR_WR[6]), - .I2(wr_pntr_plus2[7]), - .I3(RD_PNTR_WR[7]), - .O(v1_reg_0[3])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1__1 - (.I0(p_13_out[8]), - .I1(RD_PNTR_WR[8]), - .I2(p_13_out[9]), - .I3(RD_PNTR_WR[9]), - .O(v1_reg[4])); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[4].gms.ms_i_1__2 - (.I0(wr_pntr_plus2[8]), - .I1(RD_PNTR_WR[8]), - .I2(wr_pntr_plus2[9]), - .I3(RD_PNTR_WR[9]), - .O(v1_reg_0[4])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[0]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(bin2gray[0])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[10]_i_1 + (.I0(Q[10]), + .I1(Q[11]), + .O(bin2gray[10])); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[11]_i_1 + (.I0(Q[11]), + .I1(Q[12]), + .O(bin2gray[11])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[1]_i_1 + (.I0(Q[1]), + .I1(Q[2]), + .O(bin2gray[1])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[2]_i_1 + (.I0(Q[2]), + .I1(Q[3]), + .O(bin2gray[2])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[3]_i_1 + (.I0(Q[3]), + .I1(Q[4]), + .O(bin2gray[3])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[4]_i_1 + (.I0(Q[4]), + .I1(Q[5]), + .O(bin2gray[4])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[5]_i_1 + (.I0(Q[5]), + .I1(Q[6]), + .O(bin2gray[5])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[6]_i_1 + (.I0(Q[6]), + .I1(Q[7]), + .O(bin2gray[6])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[7]_i_1 + (.I0(Q[7]), + .I1(Q[8]), + .O(bin2gray[7])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[8]_i_1 + (.I0(Q[8]), + .I1(Q[9]), + .O(bin2gray[8])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[9]_i_1 + (.I0(Q[9]), + .I1(Q[10]), + .O(bin2gray[9])); endmodule (* ORIG_REF_NAME = "wr_logic" *) module iq_sample_fifo_wr_logic (full, - WEA, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , Q, + WEA, + D, + \gic0.gc0.count_d2_reg[12] , + bin2gray, + ena_array, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \gnxpm_cdc.rd_pntr_bin_reg[12] , + \gnxpm_cdc.rd_pntr_bin_reg[12]_0 , wr_clk, wr_en, RD_PNTR_WR); output full; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [12:0]Q; output [0:0]WEA; - output [9:0]Q; + output [0:0]D; + output [0:0]\gic0.gc0.count_d2_reg[12] ; + output [11:0]bin2gray; + output [0:0]ena_array; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; + input \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; input wr_clk; input wr_en; - input [9:0]RD_PNTR_WR; + input [11:0]RD_PNTR_WR; - wire [9:0]Q; - wire [9:0]RD_PNTR_WR; + wire [0:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [12:0]Q; + wire [11:0]RD_PNTR_WR; wire [0:0]WEA; - wire [4:0]\c1/v1_reg ; - wire [4:0]\c2/v1_reg ; + wire [11:0]bin2gray; + wire [0:0]ena_array; wire full; + wire [0:0]\gic0.gc0.count_d2_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; + wire \gwas.wsts_n_1 ; + wire [11:0]p_13_out; wire wr_clk; wire wr_en; + wire [11:0]wr_pntr_plus2; iq_sample_fifo_wr_status_flags_as \gwas.wsts - (.E(WEA), + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .Q(Q[12]), + .RD_PNTR_WR(RD_PNTR_WR), .full(full), - .v1_reg(\c1/v1_reg ), - .v1_reg_0(\c2/v1_reg ), + .\gic0.gc0.count_d1_reg[11] (p_13_out), + .\gic0.gc0.count_d1_reg[12] (WEA), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12] ), + .\gnxpm_cdc.rd_pntr_bin_reg[12]_0 (\gnxpm_cdc.rd_pntr_bin_reg[12]_0 ), + .out(\gwas.wsts_n_1 ), .wr_clk(wr_clk), .wr_en(wr_en)); iq_sample_fifo_wr_bin_cntr wpntr - (.E(WEA), + (.D({D,wr_pntr_plus2}), .Q(Q), - .RD_PNTR_WR(RD_PNTR_WR), - .v1_reg(\c1/v1_reg ), - .v1_reg_0(\c2/v1_reg ), - .wr_clk(wr_clk)); + .bin2gray(bin2gray), + .ena_array(ena_array), + .\gic0.gc0.count_d2_reg[12]_0 ({\gic0.gc0.count_d2_reg[12] ,p_13_out}), + .out(\gwas.wsts_n_1 ), + .ram_full_fb_i_reg(WEA), + .wr_clk(wr_clk), + .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "wr_status_flags_as" *) module iq_sample_fifo_wr_status_flags_as (full, - E, - v1_reg, - v1_reg_0, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + \gic0.gc0.count_d1_reg[12] , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , + \gnxpm_cdc.rd_pntr_bin_reg[12] , + \gnxpm_cdc.rd_pntr_bin_reg[12]_0 , wr_clk, - wr_en); + wr_en, + Q, + \gic0.gc0.count_d1_reg[11] , + RD_PNTR_WR, + D); output full; - output [0:0]E; - input [4:0]v1_reg; - input [4:0]v1_reg_0; + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output \gic0.gc0.count_d1_reg[12] ; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input \gnxpm_cdc.rd_pntr_bin_reg[12] ; + input \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; input wr_clk; input wr_en; + input [0:0]Q; + input [11:0]\gic0.gc0.count_d1_reg[11] ; + input [11:0]RD_PNTR_WR; + input [11:0]D; - wire [0:0]E; + wire [11:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [0:0]Q; + wire [11:0]RD_PNTR_WR; wire c1_n_0; wire comp2; + wire [11:0]\gic0.gc0.count_d1_reg[11] ; + wire \gic0.gc0.count_d1_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; + wire \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; (* DONT_TOUCH *) wire ram_full_fb_i; (* DONT_TOUCH *) wire ram_full_i; - wire [4:0]v1_reg; - wire [4:0]v1_reg_0; wire wr_clk; wire wr_en; assign full = ram_full_i; + assign out = ram_full_fb_i; LUT2 #( .INIT(4'h2)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0 (.I0(wr_en), .I1(ram_full_fb_i), - .O(E)); + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); + LUT3 #( + .INIT(8'h04)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1 + (.I0(ram_full_fb_i), + .I1(wr_en), + .I2(Q), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(\gic0.gc0.count_d1_reg[12] )); iq_sample_fifo_compare c1 - (.comp2(comp2), + (.RD_PNTR_WR(RD_PNTR_WR), + .comp2(comp2), + .\gic0.gc0.count_d1_reg[11] (\gic0.gc0.count_d1_reg[11] ), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12] ), .out(ram_full_fb_i), .ram_full_i_reg(c1_n_0), - .v1_reg(v1_reg), .wr_en(wr_en)); iq_sample_fifo_compare_0 c2 - (.comp2(comp2), - .v1_reg_0(v1_reg_0)); + (.D(D), + .RD_PNTR_WR(RD_PNTR_WR), + .comp2(comp2), + .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12]_0 )); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_stub.v b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_stub.v index a5b0e5b..406efd5 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_stub.v +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 -// Date : Mon Dec 12 12:44:58 2016 +// Date : Sat Apr 15 09:49:57 2017 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/misc-projects/rftool-fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo_stub.v diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/sim/iq_sample_fifo.v b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/sim/iq_sample_fifo.v index 440d592..b0be118 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/sim/iq_sample_fifo.v +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/sim/iq_sample_fifo.v @@ -1,4 +1,4 @@ -// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and @@ -85,7 +85,7 @@ output wire empty; .C_COMMON_CLOCK(0), .C_SELECT_XPM(0), .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(10), + .C_DATA_COUNT_WIDTH(13), .C_DEFAULT_VALUE("BlankString"), .C_DIN_WIDTH(24), .C_DOUT_RST_VAL("0"), @@ -117,17 +117,17 @@ output wire empty; .C_OVERFLOW_LOW(0), .C_PRELOAD_LATENCY(1), .C_PRELOAD_REGS(0), - .C_PRIM_FIFO_TYPE("1kx36"), + .C_PRIM_FIFO_TYPE("8kx4"), .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(1021), - .C_PROG_FULL_THRESH_NEGATE_VAL(1020), + .C_PROG_FULL_THRESH_ASSERT_VAL(8189), + .C_PROG_FULL_THRESH_NEGATE_VAL(8188), .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(10), - .C_RD_DEPTH(1024), + .C_RD_DATA_COUNT_WIDTH(13), + .C_RD_DEPTH(8192), .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(10), + .C_RD_PNTR_WIDTH(13), .C_UNDERFLOW_LOW(0), .C_USE_DOUT_RST(0), .C_USE_ECC(0), @@ -138,10 +138,10 @@ output wire empty; .C_USE_FWFT_DATA_COUNT(0), .C_VALID_LOW(0), .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(10), - .C_WR_DEPTH(1024), + .C_WR_DATA_COUNT_WIDTH(13), + .C_WR_DEPTH(8192), .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(10), + .C_WR_PNTR_WIDTH(13), .C_WR_RESPONSE_LATENCY(1), .C_MSGON_VAL(1), .C_ENABLE_RST_SYNC(1), @@ -297,12 +297,12 @@ output wire empty; .din(din), .wr_en(wr_en), .rd_en(rd_en), - .prog_empty_thresh(10'B0), - .prog_empty_thresh_assert(10'B0), - .prog_empty_thresh_negate(10'B0), - .prog_full_thresh(10'B0), - .prog_full_thresh_assert(10'B0), - .prog_full_thresh_negate(10'B0), + .prog_empty_thresh(13'B0), + .prog_empty_thresh_assert(13'B0), + .prog_empty_thresh_negate(13'B0), + .prog_full_thresh(13'B0), + .prog_full_thresh_assert(13'B0), + .prog_full_thresh_negate(13'B0), .int_clk(1'D0), .injectdbiterr(1'D0), .injectsbiterr(1'D0), diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/synth/iq_sample_fifo.vhd b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/synth/iq_sample_fifo.vhd index 57f6d0a..5939b79 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/synth/iq_sample_fifo.vhd +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/synth/iq_sample_fifo.vhd @@ -1,4 +1,4 @@ --- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and @@ -290,12 +290,12 @@ ARCHITECTURE iq_sample_fifo_arch OF iq_sample_fifo IS din : IN STD_LOGIC_VECTOR(23 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; - prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); - prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0); - prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0); - prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); - prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0); - prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + prog_empty_thresh : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + prog_full_thresh : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + prog_full_thresh_assert : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + prog_full_thresh_negate : IN STD_LOGIC_VECTOR(12 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; @@ -309,9 +309,9 @@ ARCHITECTURE iq_sample_fifo_arch OF iq_sample_fifo IS almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; - data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); - rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); - wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + rd_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + wr_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; @@ -516,16 +516,16 @@ ARCHITECTURE iq_sample_fifo_arch OF iq_sample_fifo IS ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF iq_sample_fifo_arch : ARCHITECTURE IS "iq_sample_fifo,fifo_generator_v13_1_2,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; - ATTRIBUTE CORE_GENERATION_INFO OF iq_sample_fifo_arch: ARCHITECTURE IS "iq_sample_fifo,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=24,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=24,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" & -"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_T" & -"HRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTE" & -"RFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_W" & -"IDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_T" & -"YPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C" & -"_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=" & -"10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=" & -"1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_AS" & -"SERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; + ATTRIBUTE CORE_GENERATION_INFO OF iq_sample_fifo_arch: ARCHITECTURE IS "iq_sample_fifo,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=13,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=24,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=24,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" & +"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=8kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=8189,C_PROG_FULL_TH" & +"RESH_NEGATE_VAL=8188,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=13,C_RD_DEPTH=8192,C_RD_FREQ=1,C_RD_PNTR_WIDTH=13,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=13,C_WR_DEPTH=8192,C_WR_FREQ=1,C_WR_PNTR_WIDTH=13,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTER" & +"FACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WI" & +"DTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TY" & +"PE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_" & +"ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=1" & +"0,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1" & +"023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASS" & +"ERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK"; @@ -541,7 +541,7 @@ BEGIN C_COMMON_CLOCK => 0, C_SELECT_XPM => 0, C_COUNT_TYPE => 0, - C_DATA_COUNT_WIDTH => 10, + C_DATA_COUNT_WIDTH => 13, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 24, C_DOUT_RST_VAL => "0", @@ -573,17 +573,17 @@ BEGIN C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, - C_PRIM_FIFO_TYPE => "1kx36", + C_PRIM_FIFO_TYPE => "8kx4", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, - C_PROG_FULL_THRESH_ASSERT_VAL => 1021, - C_PROG_FULL_THRESH_NEGATE_VAL => 1020, + C_PROG_FULL_THRESH_ASSERT_VAL => 8189, + C_PROG_FULL_THRESH_NEGATE_VAL => 8188, C_PROG_FULL_TYPE => 0, - C_RD_DATA_COUNT_WIDTH => 10, - C_RD_DEPTH => 1024, + C_RD_DATA_COUNT_WIDTH => 13, + C_RD_DEPTH => 8192, C_RD_FREQ => 1, - C_RD_PNTR_WIDTH => 10, + C_RD_PNTR_WIDTH => 13, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 0, C_USE_ECC => 0, @@ -594,10 +594,10 @@ BEGIN C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, - C_WR_DATA_COUNT_WIDTH => 10, - C_WR_DEPTH => 1024, + C_WR_DATA_COUNT_WIDTH => 13, + C_WR_DEPTH => 8192, C_WR_FREQ => 1, - C_WR_PNTR_WIDTH => 10, + C_WR_PNTR_WIDTH => 13, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, @@ -754,12 +754,12 @@ BEGIN din => din, wr_en => wr_en, rd_en => rd_en, - prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), - prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), - prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), - prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), - prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), - prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), + prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), + prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), + prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), + prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), + prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), + prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo.xci b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo.xci index 8b1e47f..f9a5453 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo.xci +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo.xci @@ -46,7 +46,7 @@ 1 0 0 - 13 + 14 BlankString 32 1 @@ -154,14 +154,14 @@ 0 0 0 - 8189 + 16381 1023 1023 1023 1023 1023 1023 - 8188 + 16380 0 0 0 @@ -171,10 +171,10 @@ 0 0 0 - 13 - 8192 + 14 + 16384 1 - 13 + 14 0 0 0 @@ -204,8 +204,8 @@ 0 0 0 - 13 - 8192 + 14 + 16384 1024 16 1024 @@ -213,7 +213,7 @@ 1024 16 1 - 13 + 14 10 4 10 @@ -234,7 +234,7 @@ rx_packet_fifo 64 false - 13 + 14 false false 0 @@ -280,14 +280,14 @@ Common_Clock_Block_RAM Independent_Clocks_Block_RAM 0 - 8189 + 16381 1023 1023 1023 1023 1023 1023 - 8188 + 16380 false false false @@ -308,7 +308,7 @@ false false 32 - 8192 + 16384 1024 16 1024 @@ -317,7 +317,7 @@ 16 false 32 - 8192 + 16384 Embedded_Reg false false @@ -343,7 +343,7 @@ 0 1 false - 13 + 14 Fully_Registered Fully_Registered Fully_Registered @@ -374,7 +374,7 @@ Active_High 1 false - 13 + 14 false FIFO false diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_sim_netlist.v b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_sim_netlist.v index 6790993..4b0a757 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_sim_netlist.v +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_sim_netlist.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 -// Date : Mon Jan 16 15:31:50 2017 +// Date : Sat Apr 15 09:39:28 2017 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode funcsim // /home/dave/misc-projects/rftool-fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_sim_netlist.v @@ -123,7 +123,7 @@ module rx_packet_fifo wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; - wire [12:0]NLW_U0_data_count_UNCONNECTED; + wire [13:0]NLW_U0_data_count_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; @@ -156,7 +156,7 @@ module rx_packet_fifo wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; - wire [12:0]NLW_U0_rd_data_count_UNCONNECTED; + wire [13:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; @@ -164,7 +164,7 @@ module rx_packet_fifo wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; - wire [12:0]NLW_U0_wr_data_count_UNCONNECTED; + wire [13:0]NLW_U0_wr_data_count_UNCONNECTED; (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) @@ -193,7 +193,7 @@ module rx_packet_fifo (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) - (* C_DATA_COUNT_WIDTH = "13" *) + (* C_DATA_COUNT_WIDTH = "14" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *) (* C_DIN_WIDTH_AXIS = "1" *) @@ -301,14 +301,14 @@ module rx_packet_fifo (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) - (* C_PROG_FULL_THRESH_ASSERT_VAL = "8189" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL = "16381" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) - (* C_PROG_FULL_THRESH_NEGATE_VAL = "8188" *) + (* C_PROG_FULL_THRESH_NEGATE_VAL = "16380" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) @@ -318,10 +318,10 @@ module rx_packet_fifo (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) - (* C_RD_DATA_COUNT_WIDTH = "13" *) - (* C_RD_DEPTH = "8192" *) + (* C_RD_DATA_COUNT_WIDTH = "14" *) + (* C_RD_DEPTH = "16384" *) (* C_RD_FREQ = "1" *) - (* C_RD_PNTR_WIDTH = "13" *) + (* C_RD_PNTR_WIDTH = "14" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) @@ -351,8 +351,8 @@ module rx_packet_fifo (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) - (* C_WR_DATA_COUNT_WIDTH = "13" *) - (* C_WR_DEPTH = "8192" *) + (* C_WR_DATA_COUNT_WIDTH = "14" *) + (* C_WR_DEPTH = "16384" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) @@ -360,7 +360,7 @@ module rx_packet_fifo (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) - (* C_WR_PNTR_WIDTH = "13" *) + (* C_WR_PNTR_WIDTH = "14" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) @@ -452,7 +452,7 @@ module rx_packet_fifo .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), - .data_count(NLW_U0_data_count_UNCONNECTED[12:0]), + .data_count(NLW_U0_data_count_UNCONNECTED[13:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout(dout), @@ -519,15 +519,15 @@ module rx_packet_fifo .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(NLW_U0_overflow_UNCONNECTED), .prog_empty(prog_empty), - .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full(NLW_U0_prog_full_UNCONNECTED), - .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), - .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[12:0]), + .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[13:0]), .rd_en(rd_en), .rd_rst(1'b0), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), @@ -596,67 +596,189 @@ module rx_packet_fifo .valid(NLW_U0_valid_UNCONNECTED), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), - .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[12:0]), + .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[13:0]), .wr_en(wr_en), .wr_rst(1'b0), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); endmodule +(* ORIG_REF_NAME = "bindec" *) +module rx_packet_fifo_bindec + (ena_array, + out, + wr_en, + Q); + output [2:0]ena_array; + input out; + input wr_en; + input [1:0]Q; + + wire [1:0]Q; + wire [2:0]ena_array; + wire out; + wire wr_en; + + LUT4 #( + .INIT(16'h0004)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 + (.I0(out), + .I1(wr_en), + .I2(Q[0]), + .I3(Q[1]), + .O(ena_array[0])); + LUT4 #( + .INIT(16'h0040)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(wr_en), + .I3(out), + .O(ena_array[1])); + LUT4 #( + .INIT(16'h0400)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1 + (.I0(Q[0]), + .I1(wr_en), + .I2(out), + .I3(Q[1]), + .O(ena_array[2])); +endmodule + +(* ORIG_REF_NAME = "bindec" *) +module rx_packet_fifo_bindec_0 + (enb_array, + ram_empty_fb_i_reg, + rd_en, + \gc0.count_d1_reg[13] ); + output [2:0]enb_array; + input ram_empty_fb_i_reg; + input rd_en; + input [1:0]\gc0.count_d1_reg[13] ; + + wire [2:0]enb_array; + wire [1:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire rd_en; + + LUT4 #( + .INIT(16'h0004)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 + (.I0(ram_empty_fb_i_reg), + .I1(rd_en), + .I2(\gc0.count_d1_reg[13] [0]), + .I3(\gc0.count_d1_reg[13] [1]), + .O(enb_array[0])); + LUT4 #( + .INIT(16'h0040)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0 + (.I0(\gc0.count_d1_reg[13] [1]), + .I1(\gc0.count_d1_reg[13] [0]), + .I2(rd_en), + .I3(ram_empty_fb_i_reg), + .O(enb_array[1])); + LUT4 #( + .INIT(16'h0400)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1 + (.I0(\gc0.count_d1_reg[13] [0]), + .I1(rd_en), + .I2(ram_empty_fb_i_reg), + .I3(\gc0.count_d1_reg[13] [1]), + .O(enb_array[2])); +endmodule + (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module rx_packet_fifo_blk_mem_gen_generic_cstr (dout, - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, + ram_full_fb_i_reg, WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , ram_full_fb_i_reg_0, - ram_empty_fb_i_reg_0, - ena_array, - enb_array, - \gc0.count_d1_reg[12]_0 ); + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); output [31:0]dout; - output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; input [31:0]din; + input [0:0]ram_full_fb_i_reg; input [0:0]WEA; - input ram_full_fb_i_reg_0; - input ram_empty_fb_i_reg_0; - input [0:0]ena_array; - input [0:0]enb_array; - input \gc0.count_d1_reg[12]_0 ; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; - wire [12:0]Q; + wire [13:0]Q; wire [0:0]WEA; wire [31:0]din; wire [31:0]dout; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire [12:0]\gc0.count_d1_reg[12] ; - wire \gc0.count_d1_reg[12]_0 ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire [2:0]ena_array; + wire [2:0]enb_array; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; - wire \ramloop[2].ram.r_n_0 ; - wire \ramloop[2].ram.r_n_1 ; - wire \ramloop[2].ram.r_n_2 ; - wire \ramloop[2].ram.r_n_3 ; - wire \ramloop[2].ram.r_n_4 ; - wire \ramloop[2].ram.r_n_5 ; - wire \ramloop[2].ram.r_n_6 ; - wire \ramloop[2].ram.r_n_7 ; - wire \ramloop[2].ram.r_n_8 ; + wire ram_ena_n_0; + wire ram_enb_n_0; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire \ramloop[10].ram.r_n_0 ; + wire \ramloop[10].ram.r_n_1 ; + wire \ramloop[10].ram.r_n_2 ; + wire \ramloop[10].ram.r_n_3 ; + wire \ramloop[10].ram.r_n_4 ; + wire \ramloop[10].ram.r_n_5 ; + wire \ramloop[10].ram.r_n_6 ; + wire \ramloop[10].ram.r_n_7 ; + wire \ramloop[10].ram.r_n_8 ; + wire \ramloop[11].ram.r_n_0 ; + wire \ramloop[11].ram.r_n_1 ; + wire \ramloop[11].ram.r_n_2 ; + wire \ramloop[11].ram.r_n_3 ; + wire \ramloop[11].ram.r_n_4 ; + wire \ramloop[11].ram.r_n_5 ; + wire \ramloop[11].ram.r_n_6 ; + wire \ramloop[11].ram.r_n_7 ; + wire \ramloop[11].ram.r_n_8 ; + wire \ramloop[12].ram.r_n_0 ; + wire \ramloop[12].ram.r_n_1 ; + wire \ramloop[12].ram.r_n_2 ; + wire \ramloop[12].ram.r_n_3 ; + wire \ramloop[12].ram.r_n_4 ; + wire \ramloop[12].ram.r_n_5 ; + wire \ramloop[12].ram.r_n_6 ; + wire \ramloop[12].ram.r_n_7 ; + wire \ramloop[12].ram.r_n_8 ; + wire \ramloop[13].ram.r_n_0 ; + wire \ramloop[13].ram.r_n_1 ; + wire \ramloop[13].ram.r_n_2 ; + wire \ramloop[13].ram.r_n_3 ; + wire \ramloop[13].ram.r_n_4 ; + wire \ramloop[13].ram.r_n_5 ; + wire \ramloop[13].ram.r_n_6 ; + wire \ramloop[13].ram.r_n_7 ; + wire \ramloop[13].ram.r_n_8 ; + wire \ramloop[14].ram.r_n_0 ; + wire \ramloop[14].ram.r_n_1 ; + wire \ramloop[14].ram.r_n_2 ; + wire \ramloop[14].ram.r_n_3 ; + wire \ramloop[14].ram.r_n_4 ; + wire \ramloop[14].ram.r_n_5 ; + wire \ramloop[14].ram.r_n_6 ; + wire \ramloop[14].ram.r_n_7 ; + wire \ramloop[14].ram.r_n_8 ; wire \ramloop[3].ram.r_n_0 ; wire \ramloop[3].ram.r_n_1 ; wire \ramloop[3].ram.r_n_2 ; @@ -692,6 +814,7 @@ module rx_packet_fifo_blk_mem_gen_generic_cstr wire \ramloop[6].ram.r_n_5 ; wire \ramloop[6].ram.r_n_6 ; wire \ramloop[6].ram.r_n_7 ; + wire \ramloop[6].ram.r_n_8 ; wire \ramloop[7].ram.r_n_0 ; wire \ramloop[7].ram.r_n_1 ; wire \ramloop[7].ram.r_n_2 ; @@ -700,371 +823,641 @@ module rx_packet_fifo_blk_mem_gen_generic_cstr wire \ramloop[7].ram.r_n_5 ; wire \ramloop[7].ram.r_n_6 ; wire \ramloop[7].ram.r_n_7 ; + wire \ramloop[7].ram.r_n_8 ; + wire \ramloop[8].ram.r_n_0 ; + wire \ramloop[8].ram.r_n_1 ; + wire \ramloop[8].ram.r_n_2 ; + wire \ramloop[8].ram.r_n_3 ; + wire \ramloop[8].ram.r_n_4 ; + wire \ramloop[8].ram.r_n_5 ; + wire \ramloop[8].ram.r_n_6 ; + wire \ramloop[8].ram.r_n_7 ; + wire \ramloop[8].ram.r_n_8 ; + wire \ramloop[9].ram.r_n_0 ; + wire \ramloop[9].ram.r_n_1 ; + wire \ramloop[9].ram.r_n_2 ; + wire \ramloop[9].ram.r_n_3 ; + wire \ramloop[9].ram.r_n_4 ; + wire \ramloop[9].ram.r_n_5 ; + wire \ramloop[9].ram.r_n_6 ; + wire \ramloop[9].ram.r_n_7 ; + wire \ramloop[9].ram.r_n_8 ; wire rd_clk; + wire rd_en; wire wr_clk; + wire wr_en; + rx_packet_fifo_bindec \bindec_a.bindec_inst_a + (.Q(Q[13:12]), + .ena_array(ena_array), + .out(out), + .wr_en(wr_en)); + rx_packet_fifo_bindec_0 \bindec_b.bindec_inst_b + (.enb_array(enb_array), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] [13:12]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .rd_en(rd_en)); rx_packet_fifo_blk_mem_gen_mux__parameterized0 \has_mux_b.B - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\ramloop[2].ram.r_n_8 ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 (\ramloop[8].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 (\ramloop[9].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 (\ramloop[7].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ({\ramloop[14].ram.r_n_0 ,\ramloop[14].ram.r_n_1 ,\ramloop[14].ram.r_n_2 ,\ramloop[14].ram.r_n_3 ,\ramloop[14].ram.r_n_4 ,\ramloop[14].ram.r_n_5 ,\ramloop[14].ram.r_n_6 ,\ramloop[14].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ({\ramloop[12].ram.r_n_0 ,\ramloop[12].ram.r_n_1 ,\ramloop[12].ram.r_n_2 ,\ramloop[12].ram.r_n_3 ,\ramloop[12].ram.r_n_4 ,\ramloop[12].ram.r_n_5 ,\ramloop[12].ram.r_n_6 ,\ramloop[12].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ({\ramloop[13].ram.r_n_0 ,\ramloop[13].ram.r_n_1 ,\ramloop[13].ram.r_n_2 ,\ramloop[13].ram.r_n_3 ,\ramloop[13].ram.r_n_4 ,\ramloop[13].ram.r_n_5 ,\ramloop[13].ram.r_n_6 ,\ramloop[13].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ({\ramloop[11].ram.r_n_0 ,\ramloop[11].ram.r_n_1 ,\ramloop[11].ram.r_n_2 ,\ramloop[11].ram.r_n_3 ,\ramloop[11].ram.r_n_4 ,\ramloop[11].ram.r_n_5 ,\ramloop[11].ram.r_n_6 ,\ramloop[11].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 (\ramloop[14].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 (\ramloop[12].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 (\ramloop[13].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\ramloop[4].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 (\ramloop[11].ram.r_n_8 ), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\ramloop[5].ram.r_n_8 ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_8 ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }), - .DOBDO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), - .DOPBDOP(\ramloop[3].ram.r_n_8 ), - .dout(dout[31:6]), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12]_0 ), - .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), - .rd_clk(rd_clk)); + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 (\ramloop[3].ram.r_n_8 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ({\ramloop[10].ram.r_n_0 ,\ramloop[10].ram.r_n_1 ,\ramloop[10].ram.r_n_2 ,\ramloop[10].ram.r_n_3 ,\ramloop[10].ram.r_n_4 ,\ramloop[10].ram.r_n_5 ,\ramloop[10].ram.r_n_6 ,\ramloop[10].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 (\ramloop[10].ram.r_n_8 ), + .DOBDO({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }), + .DOPBDOP(\ramloop[6].ram.r_n_8 ), + .dout(dout[31:5]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] [13:12]), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .rd_clk(rd_clk), + .rd_en(rd_en)); + LUT2 #( + .INIT(4'h2)) + ram_ena + (.I0(wr_en), + .I1(out), + .O(ram_ena_n_0)); + LUT2 #( + .INIT(4'h2)) + ram_enb + (.I0(rd_en), + .I1(ram_empty_fb_i_reg), + .O(ram_enb_n_0)); rx_packet_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r (.Q(Q), + .din(din[0]), + .dout(dout[0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_enb_n_0), + .ram_full_fb_i_reg(ram_ena_n_0), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + rx_packet_fifo_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r + (.Q(Q[11:0]), + .din(din[22:14]), + .\dout[21] ({\ramloop[10].ram.r_n_0 ,\ramloop[10].ram.r_n_1 ,\ramloop[10].ram.r_n_2 ,\ramloop[10].ram.r_n_3 ,\ramloop[10].ram.r_n_4 ,\ramloop[10].ram.r_n_5 ,\ramloop[10].ram.r_n_6 ,\ramloop[10].ram.r_n_7 }), + .\dout[22] (\ramloop[10].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + rx_packet_fifo_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r + (.Q(Q[11:0]), .WEA(WEA), - .din(din[1:0]), - .dout(dout[1:0]), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_fb_i_reg(ram_full_fb_i_reg), + .din(din[31:23]), + .\dout[30] ({\ramloop[11].ram.r_n_0 ,\ramloop[11].ram.r_n_1 ,\ramloop[11].ram.r_n_2 ,\ramloop[11].ram.r_n_3 ,\ramloop[11].ram.r_n_4 ,\ramloop[11].ram.r_n_5 ,\ramloop[11].ram.r_n_6 ,\ramloop[11].ram.r_n_7 }), + .\dout[31] (\ramloop[11].ram.r_n_8 ), + .ena_array(ena_array[0]), + .enb_array(enb_array[0]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + rx_packet_fifo_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r + (.Q(Q[11:0]), + .din(din[31:23]), + .\dout[30] ({\ramloop[12].ram.r_n_0 ,\ramloop[12].ram.r_n_1 ,\ramloop[12].ram.r_n_2 ,\ramloop[12].ram.r_n_3 ,\ramloop[12].ram.r_n_4 ,\ramloop[12].ram.r_n_5 ,\ramloop[12].ram.r_n_6 ,\ramloop[12].ram.r_n_7 }), + .\dout[31] (\ramloop[12].ram.r_n_8 ), + .ena_array(ena_array[1]), + .enb_array(enb_array[1]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + rx_packet_fifo_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[31:23]), + .\dout[30] ({\ramloop[13].ram.r_n_0 ,\ramloop[13].ram.r_n_1 ,\ramloop[13].ram.r_n_2 ,\ramloop[13].ram.r_n_3 ,\ramloop[13].ram.r_n_4 ,\ramloop[13].ram.r_n_5 ,\ramloop[13].ram.r_n_6 ,\ramloop[13].ram.r_n_7 }), + .\dout[31] (\ramloop[13].ram.r_n_8 ), + .ena_array(ena_array[2]), + .enb_array(enb_array[2]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + rx_packet_fifo_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r + (.Q(Q[11:0]), + .din(din[31:23]), + .\dout[30] ({\ramloop[14].ram.r_n_0 ,\ramloop[14].ram.r_n_1 ,\ramloop[14].ram.r_n_2 ,\ramloop[14].ram.r_n_3 ,\ramloop[14].ram.r_n_4 ,\ramloop[14].ram.r_n_5 ,\ramloop[14].ram.r_n_6 ,\ramloop[14].ram.r_n_7 }), + .\dout[31] (\ramloop[14].ram.r_n_8 ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r (.Q(Q), - .WEA(WEA), - .din(din[5:2]), - .dout(dout[5:2]), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_fb_i_reg(ram_full_fb_i_reg), + .din(din[2:1]), + .dout(dout[2:1]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_enb_n_0), + .ram_full_fb_i_reg(ram_ena_n_0), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r - (.Q(Q[11:0]), - .WEA(WEA), - .din(din[14:6]), - .\dout[13] ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }), - .\dout[14] (\ramloop[2].ram.r_n_8 ), - .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), - .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + (.Q(Q), + .din(din[4:3]), + .dout(dout[4:3]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .ram_empty_fb_i_reg(ram_enb_n_0), + .ram_full_fb_i_reg(ram_ena_n_0), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r - (.DOBDO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), - .DOPBDOP(\ramloop[3].ram.r_n_8 ), - .Q(Q[11:0]), - .WEA(WEA), - .din(din[14:6]), - .ena_array(ena_array), - .enb_array(enb_array), - .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + (.Q(Q[11:0]), + .din(din[13:5]), + .\dout[12] ({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }), + .\dout[13] (\ramloop[3].ram.r_n_8 ), + .ena_array(ena_array[0]), + .enb_array(enb_array[0]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r (.Q(Q[11:0]), - .WEA(WEA), - .din(din[23:15]), - .\dout[22] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), - .\dout[23] (\ramloop[4].ram.r_n_8 ), - .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), - .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .din(din[13:5]), + .\dout[12] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }), + .\dout[13] (\ramloop[4].ram.r_n_8 ), + .ena_array(ena_array[1]), + .enb_array(enb_array[1]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r (.Q(Q[11:0]), .WEA(WEA), - .din(din[23:15]), - .\dout[22] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), - .\dout[23] (\ramloop[5].ram.r_n_8 ), - .ena_array(ena_array), - .enb_array(enb_array), - .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .din(din[13:5]), + .\dout[12] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }), + .\dout[13] (\ramloop[5].ram.r_n_8 ), + .ena_array(ena_array[2]), + .enb_array(enb_array[2]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r - (.Q(Q[11:0]), - .WEA(WEA), - .din(din[31:24]), - .\dout[31] ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }), - .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), + (.DOBDO({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }), + .DOPBDOP(\ramloop[6].ram.r_n_8 ), + .Q(Q[11:0]), + .din(din[13:5]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), .ram_full_fb_i_reg(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r (.Q(Q[11:0]), .WEA(WEA), - .din(din[31:24]), - .\dout[31] ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }), - .ena_array(ena_array), - .enb_array(enb_array), - .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[12] [11:0]), + .din(din[22:14]), + .\dout[21] ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }), + .\dout[22] (\ramloop[7].ram.r_n_8 ), + .ena_array(ena_array[0]), + .enb_array(enb_array[0]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + rx_packet_fifo_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r + (.Q(Q[11:0]), + .din(din[22:14]), + .\dout[21] ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }), + .\dout[22] (\ramloop[8].ram.r_n_8 ), + .ena_array(ena_array[1]), + .enb_array(enb_array[1]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + rx_packet_fifo_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r + (.Q(Q[11:0]), + .WEA(WEA), + .din(din[22:14]), + .\dout[21] ({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }), + .\dout[22] (\ramloop[9].ram.r_n_8 ), + .ena_array(ena_array[2]), + .enb_array(enb_array[2]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[13] [11:0]), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_mux" *) module rx_packet_fifo_blk_mem_gen_mux__parameterized0 - (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 , - dout, - \gc0.count_d1_reg[12] , + (dout, + \gc0.count_d1_reg[13] , + rd_en, + ram_empty_fb_i_reg, rd_clk, DOBDO, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , - DOPBDOP, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 , + DOPBDOP, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 , \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 , \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 , \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 , - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ); - output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ; - output [25:0]dout; - input \gc0.count_d1_reg[12] ; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ); + output [26:0]dout; + input [1:0]\gc0.count_d1_reg[13] ; + input rd_en; + input ram_empty_fb_i_reg; input rd_clk; input [7:0]DOBDO; input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - input [0:0]DOPBDOP; - input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; - input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + input [0:0]DOPBDOP; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ; input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ; + input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ; + input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ; wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; - wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ; wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ; wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ; wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 ; wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ; wire [7:0]DOBDO; wire [0:0]DOPBDOP; - wire [25:0]dout; - wire \gc0.count_d1_reg[12] ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ; + wire [26:0]dout; + wire [1:0]\gc0.count_d1_reg[13] ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 ; + wire \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 ; + wire ram_empty_fb_i_reg; wire rd_clk; + wire rd_en; + wire [1:0]sel_pipe; - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hAC)) + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) \dout[10]_INST_0 - (.I0(DOBDO[4]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[4])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT3 #( - .INIT(8'hAC)) - \dout[11]_INST_0 (.I0(DOBDO[5]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [5]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [5]), + .I5(sel_pipe[0]), .O(dout[5])); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'hAC)) - \dout[12]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[11]_INST_0 (.I0(DOBDO[6]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [6]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [6]), + .I5(sel_pipe[0]), .O(dout[6])); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'hAC)) - \dout[13]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[12]_INST_0 (.I0(DOBDO[7]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [7]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [7]), + .I5(sel_pipe[0]), .O(dout[7])); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT3 #( - .INIT(8'hAC)) - \dout[14]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[13]_INST_0 (.I0(DOPBDOP), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ), + .I5(sel_pipe[0]), .O(dout[8])); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT3 #( - .INIT(8'hAC)) - \dout[15]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [0]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [0]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[9])); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT3 #( - .INIT(8'hAC)) - \dout[16]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [1]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [1]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[10])); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT3 #( - .INIT(8'hAC)) - \dout[17]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [2]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [2]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[11])); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT3 #( - .INIT(8'hAC)) - \dout[18]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [3]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [3]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[12])); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT3 #( - .INIT(8'hAC)) - \dout[19]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [4]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [4]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[13])); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'hAC)) - \dout[20]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [5]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [5]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[14])); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'hAC)) - \dout[21]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [6]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [6]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[15])); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT3 #( - .INIT(8'hAC)) - \dout[22]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [7]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 [7]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[16])); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT3 #( - .INIT(8'hAC)) - \dout[23]_INST_0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[17])); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT3 #( - .INIT(8'hAC)) - \dout[24]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[14]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [0]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [0]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[18])); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT3 #( - .INIT(8'hAC)) - \dout[25]_INST_0 + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [0]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [0]), + .I5(sel_pipe[0]), + .O(dout[9])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[15]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [1]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [1]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[19])); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT3 #( - .INIT(8'hAC)) - \dout[26]_INST_0 + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [1]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [1]), + .I5(sel_pipe[0]), + .O(dout[10])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[16]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [2]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [2]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[20])); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT3 #( - .INIT(8'hAC)) - \dout[27]_INST_0 + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [2]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [2]), + .I5(sel_pipe[0]), + .O(dout[11])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[17]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [3]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [3]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[21])); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT3 #( - .INIT(8'hAC)) - \dout[28]_INST_0 + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [3]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [3]), + .I5(sel_pipe[0]), + .O(dout[12])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[18]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [4]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [4]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[22])); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT3 #( - .INIT(8'hAC)) - \dout[29]_INST_0 + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [4]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [4]), + .I5(sel_pipe[0]), + .O(dout[13])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[19]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [5]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [5]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[23])); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT3 #( - .INIT(8'hAC)) - \dout[30]_INST_0 + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [5]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [5]), + .I5(sel_pipe[0]), + .O(dout[14])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[20]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [6]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [6]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), - .O(dout[24])); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT3 #( - .INIT(8'hAC)) - \dout[31]_INST_0 + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [6]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [6]), + .I5(sel_pipe[0]), + .O(dout[15])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[21]_INST_0 (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5 [7]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6 [7]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7 [7]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8 [7]), + .I5(sel_pipe[0]), + .O(dout[16])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[22]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9 ), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11 ), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12 ), + .I5(sel_pipe[0]), + .O(dout[17])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[23]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [0]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [0]), + .I5(sel_pipe[0]), + .O(dout[18])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[24]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [1]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [1]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [1]), + .I5(sel_pipe[0]), + .O(dout[19])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[25]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [2]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [2]), + .I5(sel_pipe[0]), + .O(dout[20])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[26]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [3]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [3]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [3]), + .I5(sel_pipe[0]), + .O(dout[21])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[27]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [4]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [4]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [4]), + .I5(sel_pipe[0]), + .O(dout[22])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[28]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [5]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [5]), + .I5(sel_pipe[0]), + .O(dout[23])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[29]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [6]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [6]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [6]), + .I5(sel_pipe[0]), + .O(dout[24])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[30]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13 [7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14 [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15 [7]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16 [7]), + .I5(sel_pipe[0]), .O(dout[25])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hAC)) - \dout[6]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[31]_INST_0 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17 ), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19 ), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20 ), + .I5(sel_pipe[0]), + .O(dout[26])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[5]_INST_0 (.I0(DOBDO[0]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [0]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [0]), + .I5(sel_pipe[0]), .O(dout[0])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT3 #( - .INIT(8'hAC)) - \dout[7]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[6]_INST_0 (.I0(DOBDO[1]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [1]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [1]), + .I5(sel_pipe[0]), .O(dout[1])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hAC)) - \dout[8]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[7]_INST_0 (.I0(DOBDO[2]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [2]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [2]), + .I5(sel_pipe[0]), .O(dout[2])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT3 #( - .INIT(8'hAC)) - \dout[9]_INST_0 + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[8]_INST_0 (.I0(DOBDO[3]), .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]), - .I2(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [3]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [3]), + .I5(sel_pipe[0]), .O(dout[3])); + LUT6 #( + .INIT(64'hAACCAACCF0FFF000)) + \dout[9]_INST_0 + (.I0(DOBDO[4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 [4]), + .I3(sel_pipe[1]), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 [4]), + .I5(sel_pipe[0]), + .O(dout[4])); + LUT4 #( + .INIT(16'hFB08)) + \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1 + (.I0(\gc0.count_d1_reg[13] [0]), + .I1(rd_en), + .I2(ram_empty_fb_i_reg), + .I3(sel_pipe[0]), + .O(\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1 + (.I0(\gc0.count_d1_reg[13] [1]), + .I1(rd_en), + .I2(ram_empty_fb_i_reg), + .I3(sel_pipe[1]), + .O(\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (.C(rd_clk), .CE(1'b1), - .D(\gc0.count_d1_reg[12] ), - .Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]_0 ), + .D(\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0 ), + .Q(sel_pipe[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0 ), + .Q(sel_pipe[1]), .R(1'b0)); endmodule @@ -1076,37 +1469,37 @@ module rx_packet_fifo_blk_mem_gen_prim_width ram_full_fb_i_reg, ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, - WEA); - output [1:0]dout; + ram_full_fb_i_reg_0); + output [0:0]dout; input wr_clk; input rd_clk; input ram_full_fb_i_reg; input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; - input [1:0]din; - input [0:0]WEA; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [0:0]din; + input [0:0]ram_full_fb_i_reg_0; - wire [12:0]Q; - wire [0:0]WEA; - wire [1:0]din; - wire [1:0]dout; - wire [12:0]\gc0.count_d1_reg[12] ; + wire [13:0]Q; + wire [0:0]din; + wire [0:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; wire ram_empty_fb_i_reg; wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; rx_packet_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram (.Q(Q), - .WEA(WEA), .din(din), .dout(dout), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule @@ -1119,92 +1512,88 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized0 ram_full_fb_i_reg, ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, - WEA); - output [3:0]dout; + ram_full_fb_i_reg_0); + output [1:0]dout; input wr_clk; input rd_clk; input ram_full_fb_i_reg; input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; - input [3:0]din; - input [0:0]WEA; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; - wire [12:0]Q; - wire [0:0]WEA; - wire [3:0]din; - wire [3:0]dout; - wire [12:0]\gc0.count_d1_reg[12] ; + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; wire ram_empty_fb_i_reg; wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram (.Q(Q), - .WEA(WEA), .din(din), .dout(dout), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module rx_packet_fifo_blk_mem_gen_prim_width__parameterized1 - (\dout[13] , - \dout[14] , + (dout, wr_clk, rd_clk, ram_full_fb_i_reg, ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[11] , + \gc0.count_d1_reg[13] , din, - WEA); - output [7:0]\dout[13] ; - output [0:0]\dout[14] ; + ram_full_fb_i_reg_0); + output [1:0]dout; input wr_clk; input rd_clk; input ram_full_fb_i_reg; input ram_empty_fb_i_reg; - input [11:0]Q; - input [11:0]\gc0.count_d1_reg[11] ; - input [8:0]din; - input [0:0]WEA; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; - wire [11:0]Q; - wire [0:0]WEA; - wire [8:0]din; - wire [7:0]\dout[13] ; - wire [0:0]\dout[14] ; - wire [11:0]\gc0.count_d1_reg[11] ; + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; wire ram_empty_fb_i_reg; wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram (.Q(Q), - .WEA(WEA), .din(din), - .\dout[13] (\dout[13] ), - .\dout[14] (\dout[14] ), - .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .dout(dout), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module rx_packet_fifo_blk_mem_gen_prim_width__parameterized2 - (DOBDO, - DOPBDOP, +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized10 + (\dout[30] , + \dout[31] , wr_clk, rd_clk, ena_array, @@ -1213,8 +1602,8 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized2 \gc0.count_d1_reg[11] , din, WEA); - output [7:0]DOBDO; - output [0:0]DOPBDOP; + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; input wr_clk; input rd_clk; input [0:0]ena_array; @@ -1224,23 +1613,23 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized2 input [8:0]din; input [0:0]WEA; - wire [7:0]DOBDO; - wire [0:0]DOPBDOP; wire [11:0]Q; wire [0:0]WEA; wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; wire [0:0]ena_array; wire [0:0]enb_array; wire [11:0]\gc0.count_d1_reg[11] ; wire rd_clk; wire wr_clk; - rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram - (.DOBDO(DOBDO), - .DOPBDOP(DOPBDOP), - .Q(Q), + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized10 \prim_noinit.ram + (.Q(Q), .WEA(WEA), .din(din), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), .ena_array(ena_array), .enb_array(enb_array), .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), @@ -1249,56 +1638,56 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized2 endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module rx_packet_fifo_blk_mem_gen_prim_width__parameterized3 - (\dout[22] , - \dout[23] , +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized11 + (\dout[30] , + \dout[31] , wr_clk, rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, + ena_array, + enb_array, Q, \gc0.count_d1_reg[11] , din, - WEA); - output [7:0]\dout[22] ; - output [0:0]\dout[23] ; + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; input wr_clk; input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; + input [0:0]ena_array; + input [0:0]enb_array; input [11:0]Q; input [11:0]\gc0.count_d1_reg[11] ; input [8:0]din; - input [0:0]WEA; + input [0:0]ram_full_fb_i_reg; wire [11:0]Q; - wire [0:0]WEA; wire [8:0]din; - wire [7:0]\dout[22] ; - wire [0:0]\dout[23] ; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; wire [11:0]\gc0.count_d1_reg[11] ; - wire ram_empty_fb_i_reg; - wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg; wire rd_clk; wire wr_clk; - rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized11 \prim_noinit.ram (.Q(Q), - .WEA(WEA), .din(din), - .\dout[22] (\dout[22] ), - .\dout[23] (\dout[23] ), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), + .ena_array(ena_array), + .enb_array(enb_array), .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .wr_clk(wr_clk)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module rx_packet_fifo_blk_mem_gen_prim_width__parameterized4 - (\dout[22] , - \dout[23] , +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized12 + (\dout[30] , + \dout[31] , wr_clk, rd_clk, ena_array, @@ -1307,8 +1696,8 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized4 \gc0.count_d1_reg[11] , din, WEA); - output [7:0]\dout[22] ; - output [0:0]\dout[23] ; + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; input wr_clk; input rd_clk; input [0:0]ena_array; @@ -1321,8 +1710,196 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized4 wire [11:0]Q; wire [0:0]WEA; wire [8:0]din; - wire [7:0]\dout[22] ; - wire [0:0]\dout[23] ; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized12 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized13 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized13 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[30] (\dout[30] ), + .\dout[31] (\dout[31] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized2 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[12] (\dout[12] ), + .\dout[13] (\dout[13] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized3 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[12] (\dout[12] ), + .\dout[13] (\dout[13] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized4 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; wire [0:0]ena_array; wire [0:0]enb_array; wire [11:0]\gc0.count_d1_reg[11] ; @@ -1333,8 +1910,8 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized4 (.Q(Q), .WEA(WEA), .din(din), - .\dout[22] (\dout[22] ), - .\dout[23] (\dout[23] ), + .\dout[12] (\dout[12] ), + .\dout[13] (\dout[13] ), .ena_array(ena_array), .enb_array(enb_array), .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), @@ -1344,42 +1921,46 @@ endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module rx_packet_fifo_blk_mem_gen_prim_width__parameterized5 - (\dout[31] , + (DOBDO, + DOPBDOP, wr_clk, rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , Q, \gc0.count_d1_reg[11] , din, - WEA); - output [7:0]\dout[31] ; + ram_full_fb_i_reg); + output [7:0]DOBDO; + output [0:0]DOPBDOP; input wr_clk; input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; input [11:0]Q; input [11:0]\gc0.count_d1_reg[11] ; - input [7:0]din; - input [0:0]WEA; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; wire [11:0]Q; - wire [0:0]WEA; - wire [7:0]din; - wire [7:0]\dout[31] ; + wire [8:0]din; wire [11:0]\gc0.count_d1_reg[11] ; - wire ram_empty_fb_i_reg; - wire ram_full_fb_i_reg; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; wire rd_clk; wire wr_clk; rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram - (.Q(Q), - .WEA(WEA), + (.DOBDO(DOBDO), + .DOPBDOP(DOPBDOP), + .Q(Q), .din(din), - .\dout[31] (\dout[31] ), .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_clk(rd_clk), .wr_clk(wr_clk)); @@ -1387,7 +1968,8 @@ endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module rx_packet_fifo_blk_mem_gen_prim_width__parameterized6 - (\dout[31] , + (\dout[21] , + \dout[22] , wr_clk, rd_clk, ena_array, @@ -1396,20 +1978,22 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized6 \gc0.count_d1_reg[11] , din, WEA); - output [7:0]\dout[31] ; + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; input wr_clk; input rd_clk; input [0:0]ena_array; input [0:0]enb_array; input [11:0]Q; input [11:0]\gc0.count_d1_reg[11] ; - input [7:0]din; + input [8:0]din; input [0:0]WEA; wire [11:0]Q; wire [0:0]WEA; - wire [7:0]din; - wire [7:0]\dout[31] ; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; wire [0:0]ena_array; wire [0:0]enb_array; wire [11:0]\gc0.count_d1_reg[11] ; @@ -1420,7 +2004,8 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized6 (.Q(Q), .WEA(WEA), .din(din), - .\dout[31] (\dout[31] ), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), .ena_array(ena_array), .enb_array(enb_array), .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), @@ -1428,6 +2013,147 @@ module rx_packet_fifo_blk_mem_gen_prim_width__parameterized6 .wr_clk(wr_clk)); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized7 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized7 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized8 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized8 \prim_noinit.ram + (.Q(Q), + .WEA(WEA), + .din(din), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), + .ena_array(ena_array), + .enb_array(enb_array), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module rx_packet_fifo_blk_mem_gen_prim_width__parameterized9 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + + rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized9 \prim_noinit.ram + (.Q(Q), + .din(din), + .\dout[21] (\dout[21] ), + .\dout[22] (\dout[22] ), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); +endmodule + (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module rx_packet_fifo_blk_mem_gen_prim_wrapper (dout, @@ -1436,30 +2162,30 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper ram_full_fb_i_reg, ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, - WEA); - output [1:0]dout; + ram_full_fb_i_reg_0); + output [0:0]dout; input wr_clk; input rd_clk; input ram_full_fb_i_reg; input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; - input [1:0]din; - input [0:0]WEA; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [0:0]din; + input [0:0]ram_full_fb_i_reg_0; - wire [12:0]Q; - wire [0:0]WEA; - wire [1:0]din; - wire [1:0]dout; - wire [12:0]\gc0.count_d1_reg[12] ; + wire [13:0]Q; + wire [0:0]din; + wire [0:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; wire ram_empty_fb_i_reg; wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ; - wire [15:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; + wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ; @@ -1553,8 +2279,8 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper .IS_RSTREGB_INVERTED(1'b0), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(2), - .READ_WIDTH_B(2), + .READ_WIDTH_A(1), + .READ_WIDTH_B(1), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), @@ -1563,19 +2289,19 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper .SRVAL_B(18'h00000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(2), - .WRITE_WIDTH_B(2)) + .WRITE_WIDTH_A(1), + .WRITE_WIDTH_B(1)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram - (.ADDRARDADDR({Q,1'b0}), - .ADDRBWRADDR({\gc0.count_d1_reg[12] ,1'b0}), + (.ADDRARDADDR(Q), + .ADDRBWRADDR(\gc0.count_d1_reg[13] ), .CLKARDCLK(wr_clk), .CLKBWRCLK(rd_clk), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0}), .DIPBDIP({1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:2],dout}), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:1],dout}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(ram_full_fb_i_reg), @@ -1586,7 +2312,7 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), - .WEA({WEA,WEA}), + .WEA({ram_full_fb_i_reg_0,ram_full_fb_i_reg_0}), .WEBWE({1'b0,1'b0,1'b0,1'b0})); endmodule @@ -1598,26 +2324,26 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized0 ram_full_fb_i_reg, ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, - WEA); - output [3:0]dout; + ram_full_fb_i_reg_0); + output [1:0]dout; input wr_clk; input rd_clk; input ram_full_fb_i_reg; input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; - input [3:0]din; - input [0:0]WEA; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; - wire [12:0]Q; - wire [0:0]WEA; - wire [3:0]din; - wire [3:0]dout; - wire [12:0]\gc0.count_d1_reg[12] ; + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; wire ram_empty_fb_i_reg; wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; @@ -1625,7 +2351,7 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized0 wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; @@ -1797,8 +2523,8 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized0 .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(4), - .READ_WIDTH_B(4), + .READ_WIDTH_A(2), + .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .SIM_COLLISION_CHECK("ALL"), @@ -1807,11 +2533,11 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized0 .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(4), - .WRITE_WIDTH_B(4)) + .WRITE_WIDTH_A(2), + .WRITE_WIDTH_B(2)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,Q,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[12] ,1'b1,1'b1}), + (.ADDRARDADDR({1'b1,Q,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[13] ,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), @@ -1819,12 +2545,12 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized0 .CLKARDCLK(wr_clk), .CLKBWRCLK(rd_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DIPADIP({1'b0,1'b0,1'b0,1'b0}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:4],dout}), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],dout}), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), @@ -1840,28 +2566,282 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized0 .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({WEA,WEA,WEA,WEA}), + .WEA({ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized1 - (\dout[13] , - \dout[14] , + (dout, wr_clk, rd_clk, ram_full_fb_i_reg, ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[11] , + \gc0.count_d1_reg[13] , din, - WEA); - output [7:0]\dout[13] ; - output [0:0]\dout[14] ; + ram_full_fb_i_reg_0); + output [1:0]dout; input wr_clk; input rd_clk; input ram_full_fb_i_reg; input ram_empty_fb_i_reg; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; + input [1:0]din; + input [0:0]ram_full_fb_i_reg_0; + + wire [13:0]Q; + wire [1:0]din; + wire [1:0]dout; + wire [13:0]\gc0.count_d1_reg[13] ; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(2), + .READ_WIDTH_B(2), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(2), + .WRITE_WIDTH_B(2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[13] ,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],dout}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(ram_empty_fb_i_reg), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0,ram_full_fb_i_reg_0}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized10 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; input [11:0]Q; input [11:0]\gc0.count_d1_reg[11] ; input [8:0]din; @@ -1870,11 +2850,11 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized1 wire [11:0]Q; wire [0:0]WEA; wire [8:0]din; - wire [7:0]\dout[13] ; - wire [0:0]\dout[14] ; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; wire [11:0]\gc0.count_d1_reg[11] ; - wire ram_empty_fb_i_reg; - wire ram_full_fb_i_reg; wire rd_clk; wire wr_clk; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; @@ -2081,12 +3061,12 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized1 .DIPADIP({1'b0,1'b0,1'b0,din[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[13] }), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[14] }), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ram_full_fb_i_reg), - .ENBWREN(ram_empty_fb_i_reg), + .ENARDEN(ena_array), + .ENBWREN(enb_array), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), @@ -2102,9 +3082,266 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized1 endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) -module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 - (DOBDO, - DOPBDOP, +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized11 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized12 + (\dout[30] , + \dout[31] , wr_clk, rd_clk, ena_array, @@ -2113,8 +3350,8 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 \gc0.count_d1_reg[11] , din, WEA); - output [7:0]DOBDO; - output [0:0]DOPBDOP; + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; input wr_clk; input rd_clk; input [0:0]ena_array; @@ -2124,11 +3361,11 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 input [8:0]din; input [0:0]WEA; - wire [7:0]DOBDO; - wire [0:0]DOPBDOP; wire [11:0]Q; wire [0:0]WEA; wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; wire [0:0]ena_array; wire [0:0]enb_array; wire [11:0]\gc0.count_d1_reg[11] ; @@ -2323,6 +3560,1291 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized13 + (\dout[30] , + \dout[31] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[30] ; + output [0:0]\dout[31] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[30] ; + wire [0:0]\dout[31] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[30] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[31] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(\gic0.gc0.count_d2_reg[13] ), + .ENBWREN(\gc0.count_d1_reg[13] ), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[12] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[13] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized3 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[12] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[13] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized4 + (\dout[12] , + \dout[13] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[12] ; + output [0:0]\dout[13] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[12] ; + wire [0:0]\dout[13] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[12] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[13] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized5 + (DOBDO, + DOPBDOP, + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]DOBDO; + output [0:0]DOPBDOP; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [7:0]DOBDO; + wire [0:0]DOPBDOP; + wire [11:0]Q; + wire [8:0]din; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), @@ -2342,8 +4864,8 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena_array), - .ENBWREN(enb_array), + .ENARDEN(\gic0.gc0.count_d2_reg[13] ), + .ENBWREN(\gc0.count_d1_reg[13] ), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), @@ -2354,782 +4876,14 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized2 .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({WEA,WEA,WEA,WEA}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) -module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized3 - (\dout[22] , - \dout[23] , - wr_clk, - rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, - Q, - \gc0.count_d1_reg[11] , - din, - WEA); - output [7:0]\dout[22] ; - output [0:0]\dout[23] ; - input wr_clk; - input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; - input [11:0]Q; - input [11:0]\gc0.count_d1_reg[11] ; - input [8:0]din; - input [0:0]WEA; - - wire [11:0]Q; - wire [0:0]WEA; - wire [8:0]din; - wire [7:0]\dout[22] ; - wire [0:0]\dout[23] ; - wire [11:0]\gc0.count_d1_reg[11] ; - wire ram_empty_fb_i_reg; - wire ram_full_fb_i_reg; - wire rd_clk; - wire wr_clk; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* CLOCK_DOMAINS = "INDEPENDENT" *) - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(0), - .DOB_REG(0), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(wr_clk), - .CLKBWRCLK(rd_clk), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,din[8]}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[22] }), - .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[23] }), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ram_full_fb_i_reg), - .ENBWREN(ram_empty_fb_i_reg), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({WEA,WEA,WEA,WEA}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) -module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized4 - (\dout[22] , - \dout[23] , - wr_clk, - rd_clk, - ena_array, - enb_array, - Q, - \gc0.count_d1_reg[11] , - din, - WEA); - output [7:0]\dout[22] ; - output [0:0]\dout[23] ; - input wr_clk; - input rd_clk; - input [0:0]ena_array; - input [0:0]enb_array; - input [11:0]Q; - input [11:0]\gc0.count_d1_reg[11] ; - input [8:0]din; - input [0:0]WEA; - - wire [11:0]Q; - wire [0:0]WEA; - wire [8:0]din; - wire [7:0]\dout[22] ; - wire [0:0]\dout[23] ; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire [11:0]\gc0.count_d1_reg[11] ; - wire rd_clk; - wire wr_clk; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* CLOCK_DOMAINS = "INDEPENDENT" *) - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(0), - .DOB_REG(0), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(wr_clk), - .CLKBWRCLK(rd_clk), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,din[8]}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[22] }), - .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[23] }), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ena_array), - .ENBWREN(enb_array), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({WEA,WEA,WEA,WEA}), - .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); -endmodule - -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) -module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized5 - (\dout[31] , - wr_clk, - rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, - Q, - \gc0.count_d1_reg[11] , - din, - WEA); - output [7:0]\dout[31] ; - input wr_clk; - input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; - input [11:0]Q; - input [11:0]\gc0.count_d1_reg[11] ; - input [7:0]din; - input [0:0]WEA; - - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ; - wire [11:0]Q; - wire [0:0]WEA; - wire [7:0]din; - wire [7:0]\dout[31] ; - wire [11:0]\gc0.count_d1_reg[11] ; - wire ram_empty_fb_i_reg; - wire ram_full_fb_i_reg; - wire rd_clk; - wire wr_clk; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; - wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; - wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; - wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; - wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; - wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; - wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; - wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; - - (* CLOCK_DOMAINS = "INDEPENDENT" *) - (* box_type = "PRIMITIVE" *) - RAMB36E1 #( - .DOA_REG(0), - .DOB_REG(0), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_A(36'h000000000), - .INIT_B(36'h000000000), - .INIT_FILE("NONE"), - .IS_CLKARDCLK_INVERTED(1'b0), - .IS_CLKBWRCLK_INVERTED(1'b0), - .IS_ENARDEN_INVERTED(1'b0), - .IS_ENBWREN_INVERTED(1'b0), - .IS_RSTRAMARSTRAM_INVERTED(1'b0), - .IS_RSTRAMB_INVERTED(1'b0), - .IS_RSTREGARSTREG_INVERTED(1'b0), - .IS_RSTREGB_INVERTED(1'b0), - .RAM_EXTENSION_A("NONE"), - .RAM_EXTENSION_B("NONE"), - .RAM_MODE("TDP"), - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - .READ_WIDTH_A(9), - .READ_WIDTH_B(9), - .RSTREG_PRIORITY_A("REGCE"), - .RSTREG_PRIORITY_B("REGCE"), - .SIM_COLLISION_CHECK("ALL"), - .SIM_DEVICE("7SERIES"), - .SRVAL_A(36'h000000000), - .SRVAL_B(36'h000000000), - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST"), - .WRITE_WIDTH_A(9), - .WRITE_WIDTH_B(9)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram - (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), - .CASCADEINA(1'b0), - .CASCADEINB(1'b0), - .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), - .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(wr_clk), - .CLKBWRCLK(rd_clk), - .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), - .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), - .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), - .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[31] }), - .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }), - .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), - .ENARDEN(ram_full_fb_i_reg), - .ENBWREN(ram_empty_fb_i_reg), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(1'b0), - .REGCEB(1'b0), - .RSTRAMARSTRAM(1'b0), - .RSTRAMB(1'b0), - .RSTREGARSTREG(1'b0), - .RSTREGB(1'b0), - .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), - .WEA({WEA,WEA,WEA,WEA}), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized6 - (\dout[31] , + (\dout[21] , + \dout[22] , wr_clk, rd_clk, ena_array, @@ -3138,21 +4892,22 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized6 \gc0.count_d1_reg[11] , din, WEA); - output [7:0]\dout[31] ; + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; input wr_clk; input rd_clk; input [0:0]ena_array; input [0:0]enb_array; input [11:0]Q; input [11:0]\gc0.count_d1_reg[11] ; - input [7:0]din; + input [8:0]din; input [0:0]WEA; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ; wire [11:0]Q; wire [0:0]WEA; - wire [7:0]din; - wire [7:0]\dout[31] ; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; wire [0:0]ena_array; wire [0:0]enb_array; wire [11:0]\gc0.count_d1_reg[11] ; @@ -3357,14 +5112,14 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized6 .CLKARDCLK(wr_clk), .CLKBWRCLK(rd_clk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), - .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DIPADIP({1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), - .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[31] }), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), - .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ena_array), .ENBWREN(enb_array), @@ -3382,205 +5137,976 @@ module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized6 .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized7 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized8 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + ena_array, + enb_array, + Q, + \gc0.count_d1_reg[11] , + din, + WEA); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input [0:0]ena_array; + input [0:0]enb_array; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]WEA; + + wire [11:0]Q; + wire [0:0]WEA; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [0:0]ena_array; + wire [0:0]enb_array; + wire [11:0]\gc0.count_d1_reg[11] ; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ena_array), + .ENBWREN(enb_array), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({WEA,WEA,WEA,WEA}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module rx_packet_fifo_blk_mem_gen_prim_wrapper__parameterized9 + (\dout[21] , + \dout[22] , + wr_clk, + rd_clk, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13] , + Q, + \gc0.count_d1_reg[11] , + din, + ram_full_fb_i_reg); + output [7:0]\dout[21] ; + output [0:0]\dout[22] ; + input wr_clk; + input rd_clk; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13] ; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + input [0:0]ram_full_fb_i_reg; + + wire [11:0]Q; + wire [8:0]din; + wire [7:0]\dout[21] ; + wire [0:0]\dout[22] ; + wire [11:0]\gc0.count_d1_reg[11] ; + wire \gc0.count_d1_reg[13] ; + wire \gic0.gc0.count_d2_reg[13] ; + wire [0:0]ram_full_fb_i_reg; + wire rd_clk; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(0), + .DOB_REG(0), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\dout[21] }), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\dout[22] }), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(\gic0.gc0.count_d2_reg[13] ), + .ENBWREN(\gc0.count_d1_reg[13] ), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + (* ORIG_REF_NAME = "blk_mem_gen_top" *) module rx_packet_fifo_blk_mem_gen_top (dout, - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, + ram_full_fb_i_reg, WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , ram_full_fb_i_reg_0, - ram_empty_fb_i_reg_0, - ena_array, - enb_array, - \gc0.count_d1_reg[12]_0 ); + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); output [31:0]dout; - output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; input [31:0]din; + input [0:0]ram_full_fb_i_reg; input [0:0]WEA; - input ram_full_fb_i_reg_0; - input ram_empty_fb_i_reg_0; - input [0:0]ena_array; - input [0:0]enb_array; - input \gc0.count_d1_reg[12]_0 ; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; - wire [12:0]Q; + wire [13:0]Q; wire [0:0]WEA; wire [31:0]din; wire [31:0]dout; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire [12:0]\gc0.count_d1_reg[12] ; - wire \gc0.count_d1_reg[12]_0 ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; + wire rd_en; wire wr_clk; + wire wr_en; rx_packet_fifo_blk_mem_gen_generic_cstr \valid.cstr (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .ena_array(ena_array), - .enb_array(enb_array), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), - .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), - .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), .ram_full_fb_i_reg(ram_full_fb_i_reg), .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), - .wr_clk(wr_clk)); + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4" *) module rx_packet_fifo_blk_mem_gen_v8_3_4 (dout, - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, + ram_full_fb_i_reg, WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , ram_full_fb_i_reg_0, - ram_empty_fb_i_reg_0, - ena_array, - enb_array, - \gc0.count_d1_reg[12]_0 ); + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); output [31:0]dout; - output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; input [31:0]din; + input [0:0]ram_full_fb_i_reg; input [0:0]WEA; - input ram_full_fb_i_reg_0; - input ram_empty_fb_i_reg_0; - input [0:0]ena_array; - input [0:0]enb_array; - input \gc0.count_d1_reg[12]_0 ; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; - wire [12:0]Q; + wire [13:0]Q; wire [0:0]WEA; wire [31:0]din; wire [31:0]dout; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire [12:0]\gc0.count_d1_reg[12] ; - wire \gc0.count_d1_reg[12]_0 ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; + wire rd_en; wire wr_clk; + wire wr_en; rx_packet_fifo_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .ena_array(ena_array), - .enb_array(enb_array), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), - .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), - .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), .ram_full_fb_i_reg(ram_full_fb_i_reg), .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), - .wr_clk(wr_clk)); + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_4_synth" *) module rx_packet_fifo_blk_mem_gen_v8_3_4_synth (dout, - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , wr_clk, rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, + ram_full_fb_i_reg, WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , ram_full_fb_i_reg_0, - ram_empty_fb_i_reg_0, - ena_array, - enb_array, - \gc0.count_d1_reg[12]_0 ); + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); output [31:0]dout; - output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; input wr_clk; input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; input [31:0]din; + input [0:0]ram_full_fb_i_reg; input [0:0]WEA; - input ram_full_fb_i_reg_0; - input ram_empty_fb_i_reg_0; - input [0:0]ena_array; - input [0:0]enb_array; - input \gc0.count_d1_reg[12]_0 ; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; - wire [12:0]Q; + wire [13:0]Q; wire [0:0]WEA; wire [31:0]din; wire [31:0]dout; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire [12:0]\gc0.count_d1_reg[12] ; - wire \gc0.count_d1_reg[12]_0 ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; + wire rd_en; wire wr_clk; + wire wr_en; rx_packet_fifo_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .ena_array(ena_array), - .enb_array(enb_array), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), - .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), - .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), .ram_full_fb_i_reg(ram_full_fb_i_reg), .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), - .wr_clk(wr_clk)); + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "clk_x_pntrs" *) @@ -3589,51 +6115,37 @@ module rx_packet_fifo_clk_x_pntrs WR_PNTR_RD, \gdiff.diff_pntr_pad_reg[12] , \gdiff.diff_pntr_pad_reg[12]_0 , - ram_full_i_reg, + \gdiff.diff_pntr_pad_reg[14] , RD_PNTR_WR, - ram_full_i_reg_0, - \gdiff.diff_pntr_pad_reg[13] , Q, - \gic0.gc0.count_d1_reg[12] , - D, + \gic0.gc0.count_d2_reg[13] , rd_clk, - wr_clk, - \gic0.gc0.count_d2_reg[12] , - bin2gray, - I6); + wr_clk); output [3:0]S; - output [12:0]WR_PNTR_RD; + output [13:0]WR_PNTR_RD; output [3:0]\gdiff.diff_pntr_pad_reg[12] ; output [3:0]\gdiff.diff_pntr_pad_reg[12]_0 ; - output ram_full_i_reg; - output [11:0]RD_PNTR_WR; - output ram_full_i_reg_0; - output [0:0]\gdiff.diff_pntr_pad_reg[13] ; - input [12:0]Q; - input [0:0]\gic0.gc0.count_d1_reg[12] ; - input [0:0]D; + output [1:0]\gdiff.diff_pntr_pad_reg[14] ; + output [13:0]RD_PNTR_WR; + input [13:0]Q; + input [13:0]\gic0.gc0.count_d2_reg[13] ; input rd_clk; input wr_clk; - input [0:0]\gic0.gc0.count_d2_reg[12] ; - input [11:0]bin2gray; - input [11:0]I6; - wire [0:0]D; - wire [11:0]I6; - wire [12:0]Q; - wire [11:0]RD_PNTR_WR; + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; wire [3:0]S; - wire [12:0]WR_PNTR_RD; - wire [11:0]bin2gray; + wire [13:0]WR_PNTR_RD; + wire [12:0]bin2gray; wire [3:0]\gdiff.diff_pntr_pad_reg[12] ; wire [3:0]\gdiff.diff_pntr_pad_reg[12]_0 ; - wire [0:0]\gdiff.diff_pntr_pad_reg[13] ; - wire [0:0]\gic0.gc0.count_d1_reg[12] ; - wire [0:0]\gic0.gc0.count_d2_reg[12] ; + wire [1:0]\gdiff.diff_pntr_pad_reg[14] ; + wire [13:0]\gic0.gc0.count_d2_reg[13] ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_13 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ; @@ -3642,48 +6154,46 @@ module rx_packet_fifo_clk_x_pntrs wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ; wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ; - wire [10:0]gray2bin; + wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[10]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[11]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[12]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ; + wire \gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ; + wire [11:0]gray2bin; wire p_0_out; - wire [12:12]p_23_out; - wire [12:0]p_3_out; - wire [12:0]p_4_out; - wire [12:12]p_5_out; - wire [12:12]p_6_out; - wire ram_full_i_reg; - wire ram_full_i_reg_0; + wire [13:0]p_3_out; + wire [13:0]p_4_out; + wire [13:13]p_5_out; + wire [13:13]p_6_out; wire rd_clk; - wire [12:0]rd_pntr_gc; + wire [13:0]rd_pntr_gc; wire wr_clk; - wire [12:0]wr_pntr_gc; + wire [13:0]wr_pntr_gc; - LUT2 #( - .INIT(4'h9)) - \gmux.gm[6].gms.ms_i_1 - (.I0(p_23_out), - .I1(\gic0.gc0.count_d1_reg[12] ), - .O(ram_full_i_reg)); - LUT2 #( - .INIT(4'h9)) - \gmux.gm[6].gms.ms_i_1__0 - (.I0(p_23_out), - .I1(D), - .O(ram_full_i_reg_0)); rx_packet_fifo_synchronizer_ff \gnxpm_cdc.gsync_stage[1].rd_stg_inst (.in0(wr_pntr_gc), .out(p_3_out), .rd_clk(rd_clk)); - rx_packet_fifo_synchronizer_ff_3 \gnxpm_cdc.gsync_stage[1].wr_stg_inst + rx_packet_fifo_synchronizer_ff_4 \gnxpm_cdc.gsync_stage[1].wr_stg_inst (.Q(rd_pntr_gc), .out(p_4_out), .wr_clk(wr_clk)); - rx_packet_fifo_synchronizer_ff_4 \gnxpm_cdc.gsync_stage[2].rd_stg_inst + rx_packet_fifo_synchronizer_ff_5 \gnxpm_cdc.gsync_stage[2].rd_stg_inst (.D({p_0_out,gray2bin}), - .\gnxpm_cdc.wr_pntr_bin_reg[12] (p_5_out), + .\gnxpm_cdc.wr_pntr_bin_reg[13] (p_5_out), .out(p_3_out), .rd_clk(rd_clk)); - rx_packet_fifo_synchronizer_ff_5 \gnxpm_cdc.gsync_stage[2].wr_stg_inst - (.D({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 }), - .\gnxpm_cdc.rd_pntr_bin_reg[12] (p_6_out), + rx_packet_fifo_synchronizer_ff_6 \gnxpm_cdc.gsync_stage[2].wr_stg_inst + (.D({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_13 }), + .\gnxpm_cdc.rd_pntr_bin_reg[13] (p_6_out), .out(p_4_out), .wr_clk(wr_clk)); FDRE #( @@ -3691,7 +6201,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[0] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_13 ), .Q(RD_PNTR_WR[0]), .R(1'b0)); FDRE #( @@ -3699,7 +6209,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[10] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), .Q(RD_PNTR_WR[10]), .R(1'b0)); FDRE #( @@ -3707,23 +6217,31 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[11] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), .Q(RD_PNTR_WR[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[12] + (.C(wr_clk), + .CE(1'b1), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), + .Q(RD_PNTR_WR[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[13] (.C(wr_clk), .CE(1'b1), .D(p_6_out), - .Q(p_23_out), + .Q(RD_PNTR_WR[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_bin_reg[1] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_12 ), .Q(RD_PNTR_WR[1]), .R(1'b0)); FDRE #( @@ -3731,7 +6249,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[2] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ), .Q(RD_PNTR_WR[2]), .R(1'b0)); FDRE #( @@ -3739,7 +6257,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[3] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ), .Q(RD_PNTR_WR[3]), .R(1'b0)); FDRE #( @@ -3747,7 +6265,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[4] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ), .Q(RD_PNTR_WR[4]), .R(1'b0)); FDRE #( @@ -3755,7 +6273,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[5] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), .Q(RD_PNTR_WR[5]), .R(1'b0)); FDRE #( @@ -3763,7 +6281,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[6] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), .Q(RD_PNTR_WR[6]), .R(1'b0)); FDRE #( @@ -3771,7 +6289,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[7] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), .Q(RD_PNTR_WR[7]), .R(1'b0)); FDRE #( @@ -3779,7 +6297,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[8] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), .Q(RD_PNTR_WR[8]), .R(1'b0)); FDRE #( @@ -3787,15 +6305,105 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_bin_reg[9] (.C(wr_clk), .CE(1'b1), - .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), .Q(RD_PNTR_WR[9]), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[0]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[10]_i_1 + (.I0(Q[10]), + .I1(Q[11]), + .O(\gnxpm_cdc.rd_pntr_gc[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[11]_i_1 + (.I0(Q[11]), + .I1(Q[12]), + .O(\gnxpm_cdc.rd_pntr_gc[11]_i_1_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[12]_i_1 + (.I0(Q[12]), + .I1(Q[13]), + .O(\gnxpm_cdc.rd_pntr_gc[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[1]_i_1 + (.I0(Q[1]), + .I1(Q[2]), + .O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[2]_i_1 + (.I0(Q[2]), + .I1(Q[3]), + .O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[3]_i_1 + (.I0(Q[3]), + .I1(Q[4]), + .O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[4]_i_1 + (.I0(Q[4]), + .I1(Q[5]), + .O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[5]_i_1 + (.I0(Q[5]), + .I1(Q[6]), + .O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[6]_i_1 + (.I0(Q[6]), + .I1(Q[7]), + .O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[7]_i_1 + (.I0(Q[7]), + .I1(Q[8]), + .O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[8]_i_1 + (.I0(Q[8]), + .I1(Q[9]), + .O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[9]_i_1 + (.I0(Q[9]), + .I1(Q[10]), + .O(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[0] (.C(rd_clk), .CE(1'b1), - .D(I6[0]), + .D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ), .Q(rd_pntr_gc[0]), .R(1'b0)); FDRE #( @@ -3803,7 +6411,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[10] (.C(rd_clk), .CE(1'b1), - .D(I6[10]), + .D(\gnxpm_cdc.rd_pntr_gc[10]_i_1_n_0 ), .Q(rd_pntr_gc[10]), .R(1'b0)); FDRE #( @@ -3811,7 +6419,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[11] (.C(rd_clk), .CE(1'b1), - .D(I6[11]), + .D(\gnxpm_cdc.rd_pntr_gc[11]_i_1_n_0 ), .Q(rd_pntr_gc[11]), .R(1'b0)); FDRE #( @@ -3819,15 +6427,23 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[12] (.C(rd_clk), .CE(1'b1), - .D(Q[12]), + .D(\gnxpm_cdc.rd_pntr_gc[12]_i_1_n_0 ), .Q(rd_pntr_gc[12]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(Q[13]), + .Q(rd_pntr_gc[13]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.rd_pntr_gc_reg[1] (.C(rd_clk), .CE(1'b1), - .D(I6[1]), + .D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ), .Q(rd_pntr_gc[1]), .R(1'b0)); FDRE #( @@ -3835,7 +6451,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[2] (.C(rd_clk), .CE(1'b1), - .D(I6[2]), + .D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ), .Q(rd_pntr_gc[2]), .R(1'b0)); FDRE #( @@ -3843,7 +6459,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[3] (.C(rd_clk), .CE(1'b1), - .D(I6[3]), + .D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ), .Q(rd_pntr_gc[3]), .R(1'b0)); FDRE #( @@ -3851,7 +6467,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[4] (.C(rd_clk), .CE(1'b1), - .D(I6[4]), + .D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ), .Q(rd_pntr_gc[4]), .R(1'b0)); FDRE #( @@ -3859,7 +6475,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[5] (.C(rd_clk), .CE(1'b1), - .D(I6[5]), + .D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ), .Q(rd_pntr_gc[5]), .R(1'b0)); FDRE #( @@ -3867,7 +6483,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[6] (.C(rd_clk), .CE(1'b1), - .D(I6[6]), + .D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ), .Q(rd_pntr_gc[6]), .R(1'b0)); FDRE #( @@ -3875,7 +6491,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[7] (.C(rd_clk), .CE(1'b1), - .D(I6[7]), + .D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ), .Q(rd_pntr_gc[7]), .R(1'b0)); FDRE #( @@ -3883,7 +6499,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[8] (.C(rd_clk), .CE(1'b1), - .D(I6[8]), + .D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ), .Q(rd_pntr_gc[8]), .R(1'b0)); FDRE #( @@ -3891,7 +6507,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.rd_pntr_gc_reg[9] (.C(rd_clk), .CE(1'b1), - .D(I6[9]), + .D(\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ), .Q(rd_pntr_gc[9]), .R(1'b0)); FDRE #( @@ -3915,7 +6531,7 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.wr_pntr_bin_reg[11] (.C(rd_clk), .CE(1'b1), - .D(p_0_out), + .D(gray2bin[11]), .Q(WR_PNTR_RD[11]), .R(1'b0)); FDRE #( @@ -3923,9 +6539,17 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.wr_pntr_bin_reg[12] (.C(rd_clk), .CE(1'b1), - .D(p_5_out), + .D(p_0_out), .Q(WR_PNTR_RD[12]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(p_5_out), + .Q(WR_PNTR_RD[13]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_bin_reg[1] @@ -3998,6 +6622,96 @@ module rx_packet_fifo_clk_x_pntrs .D(gray2bin[9]), .Q(WR_PNTR_RD[9]), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[0]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [0]), + .I1(\gic0.gc0.count_d2_reg[13] [1]), + .O(bin2gray[0])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[10]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [10]), + .I1(\gic0.gc0.count_d2_reg[13] [11]), + .O(bin2gray[10])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[11]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [11]), + .I1(\gic0.gc0.count_d2_reg[13] [12]), + .O(bin2gray[11])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[12]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [12]), + .I1(\gic0.gc0.count_d2_reg[13] [13]), + .O(bin2gray[12])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[1]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [1]), + .I1(\gic0.gc0.count_d2_reg[13] [2]), + .O(bin2gray[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[2]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [2]), + .I1(\gic0.gc0.count_d2_reg[13] [3]), + .O(bin2gray[2])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[3]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [3]), + .I1(\gic0.gc0.count_d2_reg[13] [4]), + .O(bin2gray[3])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[4]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [4]), + .I1(\gic0.gc0.count_d2_reg[13] [5]), + .O(bin2gray[4])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[5]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [5]), + .I1(\gic0.gc0.count_d2_reg[13] [6]), + .O(bin2gray[5])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[6]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [6]), + .I1(\gic0.gc0.count_d2_reg[13] [7]), + .O(bin2gray[6])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[7]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [7]), + .I1(\gic0.gc0.count_d2_reg[13] [8]), + .O(bin2gray[7])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[8]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [8]), + .I1(\gic0.gc0.count_d2_reg[13] [9]), + .O(bin2gray[8])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[9]_i_1 + (.I0(\gic0.gc0.count_d2_reg[13] [9]), + .I1(\gic0.gc0.count_d2_reg[13] [10]), + .O(bin2gray[9])); FDRE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[0] @@ -4027,9 +6741,17 @@ module rx_packet_fifo_clk_x_pntrs \gnxpm_cdc.wr_pntr_gc_reg[12] (.C(wr_clk), .CE(1'b1), - .D(\gic0.gc0.count_d2_reg[12] ), + .D(bin2gray[12]), .Q(wr_pntr_gc[12]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[13] + (.C(wr_clk), + .CE(1'b1), + .D(\gic0.gc0.count_d2_reg[13] [13]), + .Q(wr_pntr_gc[13]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gnxpm_cdc.wr_pntr_gc_reg[1] @@ -4153,9 +6875,15 @@ module rx_packet_fifo_clk_x_pntrs LUT2 #( .INIT(4'h9)) plusOp_carry__2_i_1 + (.I0(WR_PNTR_RD[13]), + .I1(Q[13]), + .O(\gdiff.diff_pntr_pad_reg[14] [1])); + LUT2 #( + .INIT(4'h9)) + plusOp_carry__2_i_2 (.I0(WR_PNTR_RD[12]), .I1(Q[12]), - .O(\gdiff.diff_pntr_pad_reg[13] )); + .O(\gdiff.diff_pntr_pad_reg[14] [0])); LUT2 #( .INIT(4'h9)) plusOp_carry_i_2 @@ -4185,21 +6913,20 @@ endmodule (* ORIG_REF_NAME = "compare" *) module rx_packet_fifo_compare (ram_full_i_reg, - \gnxpm_cdc.rd_pntr_bin_reg[12] , wr_en, out, comp2, - \gic0.gc0.count_d1_reg[11] , + Q, RD_PNTR_WR); output ram_full_i_reg; - input \gnxpm_cdc.rd_pntr_bin_reg[12] ; input wr_en; input out; input comp2; - input [11:0]\gic0.gc0.count_d1_reg[11] ; - input [11:0]RD_PNTR_WR; + input [13:0]Q; + input [13:0]RD_PNTR_WR; - wire [11:0]RD_PNTR_WR; + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; wire carrynet_0; wire carrynet_1; wire carrynet_2; @@ -4208,11 +6935,9 @@ module rx_packet_fifo_compare wire carrynet_5; wire comp1; wire comp2; - wire [11:0]\gic0.gc0.count_d1_reg[11] ; - wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; wire out; wire ram_full_i_reg; - wire [5:0]v1_reg; + wire [6:0]v1_reg; wire wr_en; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; @@ -4232,33 +6957,33 @@ module rx_packet_fifo_compare LUT4 #( .INIT(16'h9009)) \gmux.gm[0].gm1.m1_i_1 - (.I0(\gic0.gc0.count_d1_reg[11] [0]), + (.I0(Q[0]), .I1(RD_PNTR_WR[0]), - .I2(\gic0.gc0.count_d1_reg[11] [1]), + .I2(Q[1]), .I3(RD_PNTR_WR[1]), .O(v1_reg[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1 - (.I0(\gic0.gc0.count_d1_reg[11] [2]), + (.I0(Q[2]), .I1(RD_PNTR_WR[2]), - .I2(\gic0.gc0.count_d1_reg[11] [3]), + .I2(Q[3]), .I3(RD_PNTR_WR[3]), .O(v1_reg[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1 - (.I0(\gic0.gc0.count_d1_reg[11] [4]), + (.I0(Q[4]), .I1(RD_PNTR_WR[4]), - .I2(\gic0.gc0.count_d1_reg[11] [5]), + .I2(Q[5]), .I3(RD_PNTR_WR[5]), .O(v1_reg[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1 - (.I0(\gic0.gc0.count_d1_reg[11] [6]), + (.I0(Q[6]), .I1(RD_PNTR_WR[6]), - .I2(\gic0.gc0.count_d1_reg[11] [7]), + .I2(Q[7]), .I3(RD_PNTR_WR[7]), .O(v1_reg[3])); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) @@ -4269,23 +6994,31 @@ module rx_packet_fifo_compare .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gnxpm_cdc.rd_pntr_bin_reg[12] ,v1_reg[5:4]})); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1 - (.I0(\gic0.gc0.count_d1_reg[11] [8]), + (.I0(Q[8]), .I1(RD_PNTR_WR[8]), - .I2(\gic0.gc0.count_d1_reg[11] [9]), + .I2(Q[9]), .I3(RD_PNTR_WR[9]), .O(v1_reg[4])); LUT4 #( .INIT(16'h9009)) \gmux.gm[5].gms.ms_i_1 - (.I0(\gic0.gc0.count_d1_reg[11] [10]), + (.I0(Q[10]), .I1(RD_PNTR_WR[10]), - .I2(\gic0.gc0.count_d1_reg[11] [11]), + .I2(Q[11]), .I3(RD_PNTR_WR[11]), .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(Q[12]), + .I1(RD_PNTR_WR[12]), + .I2(Q[13]), + .I3(RD_PNTR_WR[13]), + .O(v1_reg[6])); LUT4 #( .INIT(16'hAEAA)) ram_full_i_i_1 @@ -4297,18 +7030,16 @@ module rx_packet_fifo_compare endmodule (* ORIG_REF_NAME = "compare" *) -module rx_packet_fifo_compare_0 +module rx_packet_fifo_compare_1 (comp2, - \gnxpm_cdc.rd_pntr_bin_reg[12] , D, RD_PNTR_WR); output comp2; - input \gnxpm_cdc.rd_pntr_bin_reg[12] ; - input [11:0]D; - input [11:0]RD_PNTR_WR; + input [13:0]D; + input [13:0]RD_PNTR_WR; - wire [11:0]D; - wire [11:0]RD_PNTR_WR; + wire [13:0]D; + wire [13:0]RD_PNTR_WR; wire carrynet_0; wire carrynet_1; wire carrynet_2; @@ -4316,8 +7047,7 @@ module rx_packet_fifo_compare_0 wire carrynet_4; wire carrynet_5; wire comp2; - wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; - wire [5:0]v1_reg; + wire [6:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; @@ -4373,7 +7103,7 @@ module rx_packet_fifo_compare_0 .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gnxpm_cdc.rd_pntr_bin_reg[12] ,v1_reg[5:4]})); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1 @@ -4390,21 +7120,27 @@ module rx_packet_fifo_compare_0 .I2(D[11]), .I3(RD_PNTR_WR[11]), .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(D[12]), + .I1(RD_PNTR_WR[12]), + .I2(D[13]), + .I3(RD_PNTR_WR[13]), + .O(v1_reg[6])); endmodule (* ORIG_REF_NAME = "compare" *) -module rx_packet_fifo_compare_1 +module rx_packet_fifo_compare_2 (comp0, - \gc0.count_d1_reg[12] , WR_PNTR_RD, Q); output comp0; - input \gc0.count_d1_reg[12] ; - input [11:0]WR_PNTR_RD; - input [11:0]Q; + input [13:0]WR_PNTR_RD; + input [13:0]Q; - wire [11:0]Q; - wire [11:0]WR_PNTR_RD; + wire [13:0]Q; + wire [13:0]WR_PNTR_RD; wire carrynet_0; wire carrynet_1; wire carrynet_2; @@ -4412,8 +7148,7 @@ module rx_packet_fifo_compare_1 wire carrynet_4; wire carrynet_5; wire comp0; - wire \gc0.count_d1_reg[12] ; - wire [5:0]v1_reg; + wire [6:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; @@ -4469,7 +7204,7 @@ module rx_packet_fifo_compare_1 .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gc0.count_d1_reg[12] ,v1_reg[5:4]})); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1 @@ -4486,21 +7221,27 @@ module rx_packet_fifo_compare_1 .I2(WR_PNTR_RD[11]), .I3(Q[11]), .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(WR_PNTR_RD[12]), + .I1(Q[12]), + .I2(WR_PNTR_RD[13]), + .I3(Q[13]), + .O(v1_reg[6])); endmodule (* ORIG_REF_NAME = "compare" *) -module rx_packet_fifo_compare_2 +module rx_packet_fifo_compare_3 (comp1, - \gc0.count_reg[12] , WR_PNTR_RD, D); output comp1; - input \gc0.count_reg[12] ; - input [11:0]WR_PNTR_RD; - input [11:0]D; + input [13:0]WR_PNTR_RD; + input [13:0]D; - wire [11:0]D; - wire [11:0]WR_PNTR_RD; + wire [13:0]D; + wire [13:0]WR_PNTR_RD; wire carrynet_0; wire carrynet_1; wire carrynet_2; @@ -4508,8 +7249,7 @@ module rx_packet_fifo_compare_2 wire carrynet_4; wire carrynet_5; wire comp1; - wire \gc0.count_reg[12] ; - wire [5:0]v1_reg; + wire [6:0]v1_reg; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:3]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; @@ -4565,7 +7305,7 @@ module rx_packet_fifo_compare_2 .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],\gc0.count_reg[12] ,v1_reg[5:4]})); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3],v1_reg[6:4]})); LUT4 #( .INIT(16'h9009)) \gmux.gm[4].gms.ms_i_1 @@ -4582,6 +7322,14 @@ module rx_packet_fifo_compare_2 .I2(WR_PNTR_RD[11]), .I3(D[11]), .O(v1_reg[5])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[6].gms.ms_i_1 + (.I0(WR_PNTR_RD[12]), + .I1(D[12]), + .I2(WR_PNTR_RD[13]), + .I3(D[13]), + .O(v1_reg[6])); endmodule (* ORIG_REF_NAME = "fifo_generator_ramfifo" *) @@ -4605,16 +7353,12 @@ module rx_packet_fifo_fifo_generator_ramfifo input rd_clk; input [31:0]din; - wire [11:0]bin2gray; wire [31:0]din; wire [31:0]dout; wire empty; wire full; - wire [1:1]\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ; - wire [1:1]\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ; wire \gntv_or_sync_fifo.gcx.clkx_n_0 ; wire \gntv_or_sync_fifo.gcx.clkx_n_1 ; - wire \gntv_or_sync_fifo.gcx.clkx_n_17 ; wire \gntv_or_sync_fifo.gcx.clkx_n_18 ; wire \gntv_or_sync_fifo.gcx.clkx_n_19 ; wire \gntv_or_sync_fifo.gcx.clkx_n_2 ; @@ -4624,105 +7368,77 @@ module rx_packet_fifo_fifo_generator_ramfifo wire \gntv_or_sync_fifo.gcx.clkx_n_23 ; wire \gntv_or_sync_fifo.gcx.clkx_n_24 ; wire \gntv_or_sync_fifo.gcx.clkx_n_25 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_26 ; + wire \gntv_or_sync_fifo.gcx.clkx_n_27 ; wire \gntv_or_sync_fifo.gcx.clkx_n_3 ; - wire \gntv_or_sync_fifo.gcx.clkx_n_38 ; - wire \gntv_or_sync_fifo.gcx.clkx_n_39 ; - wire \gntv_or_sync_fifo.gl0.rd_n_16 ; - wire \gntv_or_sync_fifo.gl0.rd_n_17 ; - wire \gntv_or_sync_fifo.gl0.rd_n_18 ; - wire \gntv_or_sync_fifo.gl0.rd_n_19 ; - wire \gntv_or_sync_fifo.gl0.rd_n_2 ; - wire \gntv_or_sync_fifo.gl0.rd_n_20 ; - wire \gntv_or_sync_fifo.gl0.rd_n_21 ; - wire \gntv_or_sync_fifo.gl0.rd_n_22 ; - wire \gntv_or_sync_fifo.gl0.rd_n_23 ; - wire \gntv_or_sync_fifo.gl0.rd_n_24 ; - wire \gntv_or_sync_fifo.gl0.rd_n_25 ; - wire \gntv_or_sync_fifo.gl0.rd_n_26 ; - wire \gntv_or_sync_fifo.gl0.rd_n_27 ; - wire \gntv_or_sync_fifo.gl0.rd_n_28 ; - wire \gntv_or_sync_fifo.gl0.rd_n_30 ; + wire \gntv_or_sync_fifo.gl0.rd_n_3 ; wire \gntv_or_sync_fifo.gl0.wr_n_1 ; - wire \gntv_or_sync_fifo.gl0.wr_n_15 ; - wire \gntv_or_sync_fifo.gl0.wr_n_31 ; - wire [12:0]p_0_out_0; - wire [12:0]p_12_out; - wire [12:12]p_13_out; - wire [12:0]p_22_out; - wire [11:0]p_23_out; + wire \gntv_or_sync_fifo.gl0.wr_n_17 ; + wire \gntv_or_sync_fifo.gl0.wr_n_18 ; + wire \gntv_or_sync_fifo.gl0.wr_n_19 ; + wire \gntv_or_sync_fifo.gl0.wr_n_2 ; + wire [13:0]p_0_out_0; + wire [13:0]p_12_out; + wire [13:0]p_22_out; + wire [13:0]p_23_out; + wire p_2_out; wire prog_empty; wire rd_clk; wire rd_en; - wire sel_pipe; wire wr_clk; wire wr_en; - wire [12:12]wr_pntr_plus2; rx_packet_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx - (.D(wr_pntr_plus2), - .I6({\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 ,\gntv_or_sync_fifo.gl0.rd_n_26 ,\gntv_or_sync_fifo.gl0.rd_n_27 ,\gntv_or_sync_fifo.gl0.rd_n_28 }), - .Q(p_0_out_0), + (.Q(p_0_out_0), .RD_PNTR_WR(p_23_out), .S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 ,\gntv_or_sync_fifo.gcx.clkx_n_2 ,\gntv_or_sync_fifo.gcx.clkx_n_3 }), .WR_PNTR_RD(p_22_out), - .bin2gray(bin2gray), - .\gdiff.diff_pntr_pad_reg[12] ({\gntv_or_sync_fifo.gcx.clkx_n_17 ,\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 ,\gntv_or_sync_fifo.gcx.clkx_n_20 }), - .\gdiff.diff_pntr_pad_reg[12]_0 ({\gntv_or_sync_fifo.gcx.clkx_n_21 ,\gntv_or_sync_fifo.gcx.clkx_n_22 ,\gntv_or_sync_fifo.gcx.clkx_n_23 ,\gntv_or_sync_fifo.gcx.clkx_n_24 }), - .\gdiff.diff_pntr_pad_reg[13] (\gntv_or_sync_fifo.gcx.clkx_n_39 ), - .\gic0.gc0.count_d1_reg[12] (p_13_out), - .\gic0.gc0.count_d2_reg[12] (p_12_out[12]), - .ram_full_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_25 ), - .ram_full_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_38 ), + .\gdiff.diff_pntr_pad_reg[12] ({\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 ,\gntv_or_sync_fifo.gcx.clkx_n_20 ,\gntv_or_sync_fifo.gcx.clkx_n_21 }), + .\gdiff.diff_pntr_pad_reg[12]_0 ({\gntv_or_sync_fifo.gcx.clkx_n_22 ,\gntv_or_sync_fifo.gcx.clkx_n_23 ,\gntv_or_sync_fifo.gcx.clkx_n_24 ,\gntv_or_sync_fifo.gcx.clkx_n_25 }), + .\gdiff.diff_pntr_pad_reg[14] ({\gntv_or_sync_fifo.gcx.clkx_n_26 ,\gntv_or_sync_fifo.gcx.clkx_n_27 }), + .\gic0.gc0.count_d2_reg[13] (p_12_out), .rd_clk(rd_clk), .wr_clk(wr_clk)); rx_packet_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.rd_n_2 ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.rd_n_30 ), - .I6({\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 ,\gntv_or_sync_fifo.gl0.rd_n_26 ,\gntv_or_sync_fifo.gl0.rd_n_27 ,\gntv_or_sync_fifo.gl0.rd_n_28 }), + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.rd_n_3 ), .Q(p_0_out_0), .S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 ,\gntv_or_sync_fifo.gcx.clkx_n_2 ,\gntv_or_sync_fifo.gcx.clkx_n_3 }), .WR_PNTR_RD(p_22_out), .empty(empty), - .enb_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ), - .\gnxpm_cdc.wr_pntr_bin_reg[11] ({\gntv_or_sync_fifo.gcx.clkx_n_21 ,\gntv_or_sync_fifo.gcx.clkx_n_22 ,\gntv_or_sync_fifo.gcx.clkx_n_23 ,\gntv_or_sync_fifo.gcx.clkx_n_24 }), - .\gnxpm_cdc.wr_pntr_bin_reg[12] (\gntv_or_sync_fifo.gcx.clkx_n_39 ), - .\gnxpm_cdc.wr_pntr_bin_reg[7] ({\gntv_or_sync_fifo.gcx.clkx_n_17 ,\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 ,\gntv_or_sync_fifo.gcx.clkx_n_20 }), - .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_16 ), + .\gnxpm_cdc.wr_pntr_bin_reg[11] ({\gntv_or_sync_fifo.gcx.clkx_n_22 ,\gntv_or_sync_fifo.gcx.clkx_n_23 ,\gntv_or_sync_fifo.gcx.clkx_n_24 ,\gntv_or_sync_fifo.gcx.clkx_n_25 }), + .\gnxpm_cdc.wr_pntr_bin_reg[13] ({\gntv_or_sync_fifo.gcx.clkx_n_26 ,\gntv_or_sync_fifo.gcx.clkx_n_27 }), + .\gnxpm_cdc.wr_pntr_bin_reg[7] ({\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 ,\gntv_or_sync_fifo.gcx.clkx_n_20 ,\gntv_or_sync_fifo.gcx.clkx_n_21 }), + .out(p_2_out), .prog_empty(prog_empty), .rd_clk(rd_clk), - .rd_en(rd_en), - .sel_pipe(sel_pipe)); + .rd_en(rd_en)); rx_packet_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr - (.D(wr_pntr_plus2), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.wr_n_1 ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.wr_n_31 ), + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\gntv_or_sync_fifo.gl0.wr_n_2 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\gntv_or_sync_fifo.gl0.wr_n_18 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\gntv_or_sync_fifo.gl0.wr_n_19 ), .Q(p_12_out), .RD_PNTR_WR(p_23_out), - .WEA(\gntv_or_sync_fifo.gl0.wr_n_15 ), - .bin2gray(bin2gray), - .ena_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_17 ), .full(full), - .\gic0.gc0.count_d2_reg[12] (p_13_out), - .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gntv_or_sync_fifo.gcx.clkx_n_25 ), - .\gnxpm_cdc.rd_pntr_bin_reg[12]_0 (\gntv_or_sync_fifo.gcx.clkx_n_38 ), + .out(\gntv_or_sync_fifo.gl0.wr_n_1 ), .wr_clk(wr_clk), .wr_en(wr_en)); rx_packet_fifo_memory \gntv_or_sync_fifo.mem (.Q(p_12_out), - .WEA(\gntv_or_sync_fifo.gl0.wr_n_15 ), + .WEA(\gntv_or_sync_fifo.gl0.wr_n_17 ), .din(din), .dout(dout), - .ena_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ena_array ), - .enb_array(\gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ), - .\gc0.count_d1_reg[12] (p_0_out_0), - .\gc0.count_d1_reg[12]_0 (\gntv_or_sync_fifo.gl0.rd_n_16 ), - .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_30 ), - .ram_empty_fb_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_2 ), - .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_31 ), - .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_1 ), + .\gc0.count_d1_reg[13] (p_0_out_0), + .\gc0.count_d1_reg[13]_0 (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .\gic0.gc0.count_d2_reg[13] (\gntv_or_sync_fifo.gl0.wr_n_2 ), + .out(\gntv_or_sync_fifo.gl0.wr_n_1 ), + .ram_empty_fb_i_reg(p_2_out), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_18 ), + .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_19 ), .rd_clk(rd_clk), - .sel_pipe(sel_pipe), - .wr_clk(wr_clk)); + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "fifo_generator_top" *) @@ -4777,7 +7493,7 @@ endmodule (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) -(* C_DATA_COUNT_WIDTH = "13" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *) +(* C_DATA_COUNT_WIDTH = "14" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *) @@ -4813,13 +7529,13 @@ endmodule (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "1024" *) (* C_PROG_EMPTY_TYPE = "1" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) -(* C_PROG_FULL_THRESH_ASSERT_VAL = "8189" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL = "16381" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) -(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "8188" *) (* C_PROG_FULL_TYPE = "0" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "16380" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) -(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "13" *) -(* C_RD_DEPTH = "8192" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "13" *) +(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "14" *) +(* C_RD_DEPTH = "16384" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "14" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) @@ -4829,10 +7545,10 @@ endmodule (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) -(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "13" *) -(* C_WR_DEPTH = "8192" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) +(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "14" *) +(* C_WR_DEPTH = "16384" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) -(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "13" *) +(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "14" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_2" *) @@ -5080,12 +7796,12 @@ module rx_packet_fifo_fifo_generator_v13_1_2 input [31:0]din; input wr_en; input rd_en; - input [12:0]prog_empty_thresh; - input [12:0]prog_empty_thresh_assert; - input [12:0]prog_empty_thresh_negate; - input [12:0]prog_full_thresh; - input [12:0]prog_full_thresh_assert; - input [12:0]prog_full_thresh_negate; + input [13:0]prog_empty_thresh; + input [13:0]prog_empty_thresh_assert; + input [13:0]prog_empty_thresh_negate; + input [13:0]prog_full_thresh; + input [13:0]prog_full_thresh_assert; + input [13:0]prog_full_thresh_negate; input int_clk; input injectdbiterr; input injectsbiterr; @@ -5099,9 +7815,9 @@ module rx_packet_fifo_fifo_generator_v13_1_2 output almost_empty; output valid; output underflow; - output [12:0]data_count; - output [12:0]rd_data_count; - output [12:0]wr_data_count; + output [13:0]data_count; + output [13:0]rd_data_count; + output [13:0]wr_data_count; output prog_full; output prog_empty; output sbiterr; @@ -5494,6 +8210,7 @@ module rx_packet_fifo_fifo_generator_v13_1_2 assign axis_wr_data_count[2] = \ ; assign axis_wr_data_count[1] = \ ; assign axis_wr_data_count[0] = \ ; + assign data_count[13] = \ ; assign data_count[12] = \ ; assign data_count[11] = \ ; assign data_count[10] = \ ; @@ -5734,6 +8451,7 @@ module rx_packet_fifo_fifo_generator_v13_1_2 assign m_axis_tvalid = \ ; assign overflow = \ ; assign prog_full = \ ; + assign rd_data_count[13] = \ ; assign rd_data_count[12] = \ ; assign rd_data_count[11] = \ ; assign rd_data_count[10] = \ ; @@ -5831,6 +8549,7 @@ module rx_packet_fifo_fifo_generator_v13_1_2 assign underflow = \ ; assign valid = \ ; assign wr_ack = \ ; + assign wr_data_count[13] = \ ; assign wr_data_count[12] = \ ; assign wr_data_count[11] = \ ; assign wr_data_count[10] = \ ; @@ -5907,110 +8626,97 @@ endmodule (* ORIG_REF_NAME = "memory" *) module rx_packet_fifo_memory (dout, - sel_pipe, wr_clk, rd_clk, - ram_full_fb_i_reg, - ram_empty_fb_i_reg, Q, - \gc0.count_d1_reg[12] , + \gc0.count_d1_reg[13] , din, + ram_full_fb_i_reg, WEA, + \gic0.gc0.count_d2_reg[13] , + \gc0.count_d1_reg[13]_0 , ram_full_fb_i_reg_0, - ram_empty_fb_i_reg_0, - ena_array, - enb_array, - \gc0.count_d1_reg[12]_0 ); + wr_en, + out, + rd_en, + ram_empty_fb_i_reg); output [31:0]dout; - output sel_pipe; input wr_clk; input rd_clk; - input ram_full_fb_i_reg; - input ram_empty_fb_i_reg; - input [12:0]Q; - input [12:0]\gc0.count_d1_reg[12] ; + input [13:0]Q; + input [13:0]\gc0.count_d1_reg[13] ; input [31:0]din; + input [0:0]ram_full_fb_i_reg; input [0:0]WEA; - input ram_full_fb_i_reg_0; - input ram_empty_fb_i_reg_0; - input [0:0]ena_array; - input [0:0]enb_array; - input \gc0.count_d1_reg[12]_0 ; + input \gic0.gc0.count_d2_reg[13] ; + input \gc0.count_d1_reg[13]_0 ; + input [0:0]ram_full_fb_i_reg_0; + input wr_en; + input out; + input rd_en; + input ram_empty_fb_i_reg; - wire [12:0]Q; + wire [13:0]Q; wire [0:0]WEA; wire [31:0]din; wire [31:0]dout; - wire [0:0]ena_array; - wire [0:0]enb_array; - wire [12:0]\gc0.count_d1_reg[12] ; - wire \gc0.count_d1_reg[12]_0 ; + wire [13:0]\gc0.count_d1_reg[13] ; + wire \gc0.count_d1_reg[13]_0 ; + wire \gic0.gc0.count_d2_reg[13] ; + wire out; wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; - wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; + wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_full_fb_i_reg_0; wire rd_clk; - wire sel_pipe; + wire rd_en; wire wr_clk; + wire wr_en; rx_packet_fifo_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg (.Q(Q), .WEA(WEA), .din(din), .dout(dout), - .ena_array(ena_array), - .enb_array(enb_array), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] ), - .\gc0.count_d1_reg[12]_0 (\gc0.count_d1_reg[12]_0 ), - .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (sel_pipe), + .\gc0.count_d1_reg[13] (\gc0.count_d1_reg[13] ), + .\gc0.count_d1_reg[13]_0 (\gc0.count_d1_reg[13]_0 ), + .\gic0.gc0.count_d2_reg[13] (\gic0.gc0.count_d2_reg[13] ), + .out(out), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg_0), .ram_full_fb_i_reg(ram_full_fb_i_reg), .ram_full_fb_i_reg_0(ram_full_fb_i_reg_0), .rd_clk(rd_clk), - .wr_clk(wr_clk)); + .rd_en(rd_en), + .wr_clk(wr_clk), + .wr_en(wr_en)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module rx_packet_fifo_rd_bin_cntr (D, - ram_empty_fb_i_reg, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , Q, - ram_empty_fb_i_reg_0, - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , - enb_array, - I6, E, rd_clk, - WR_PNTR_RD, rd_en, - out, - sel_pipe); - output [11:0]D; - output ram_empty_fb_i_reg; - output [12:0]Q; - output ram_empty_fb_i_reg_0; - output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; - output [0:0]enb_array; - output [11:0]I6; + out); + output [13:0]D; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [13:0]Q; input [0:0]E; input rd_clk; - input [0:0]WR_PNTR_RD; input rd_en; input out; - input sel_pipe; - wire [11:0]D; + wire [13:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; wire [0:0]E; - wire [11:0]I6; - wire [12:0]Q; - wire [0:0]WR_PNTR_RD; - wire [0:0]enb_array; + wire [13:0]Q; wire \gc0.count[0]_i_2_n_0 ; wire \gc0.count[0]_i_3_n_0 ; wire \gc0.count[0]_i_4_n_0 ; wire \gc0.count[0]_i_5_n_0 ; wire \gc0.count[12]_i_2_n_0 ; + wire \gc0.count[12]_i_3_n_0 ; wire \gc0.count[4]_i_2_n_0 ; wire \gc0.count[4]_i_3_n_0 ; wire \gc0.count[4]_i_4_n_0 ; @@ -6027,6 +8733,8 @@ module rx_packet_fifo_rd_bin_cntr wire \gc0.count_reg[0]_i_1_n_5 ; wire \gc0.count_reg[0]_i_1_n_6 ; wire \gc0.count_reg[0]_i_1_n_7 ; + wire \gc0.count_reg[12]_i_1_n_3 ; + wire \gc0.count_reg[12]_i_1_n_6 ; wire \gc0.count_reg[12]_i_1_n_7 ; wire \gc0.count_reg[4]_i_1_n_0 ; wire \gc0.count_reg[4]_i_1_n_1 ; @@ -6044,24 +8752,20 @@ module rx_packet_fifo_rd_bin_cntr wire \gc0.count_reg[8]_i_1_n_5 ; wire \gc0.count_reg[8]_i_1_n_6 ; wire \gc0.count_reg[8]_i_1_n_7 ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; wire out; - wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; wire rd_clk; wire rd_en; - wire [12:12]rd_pntr_plus1; - wire sel_pipe; - wire [3:0]\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED ; - wire [3:1]\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED ; + wire [3:1]\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:2]\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED ; - LUT3 #( - .INIT(8'h20)) + LUT4 #( + .INIT(16'h0080)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 - (.I0(Q[12]), - .I1(out), + (.I0(Q[13]), + .I1(Q[12]), .I2(rd_en), - .O(enb_array)); + .I3(out), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); LUT1 #( .INIT(2'h2)) \gc0.count[0]_i_2 @@ -6085,8 +8789,13 @@ module rx_packet_fifo_rd_bin_cntr LUT1 #( .INIT(2'h2)) \gc0.count[12]_i_2 - (.I0(rd_pntr_plus1), + (.I0(D[13]), .O(\gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[12]_i_3 + (.I0(D[12]), + .O(\gc0.count[12]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \gc0.count[4]_i_2 @@ -6156,9 +8865,17 @@ module rx_packet_fifo_rd_bin_cntr \gc0.count_d1_reg[12] (.C(rd_clk), .CE(E), - .D(rd_pntr_plus1), + .D(D[12]), .Q(Q[12]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gc0.count_d1_reg[13] + (.C(rd_clk), + .CE(E), + .D(D[13]), + .Q(Q[13]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[1] @@ -6268,15 +8985,23 @@ module rx_packet_fifo_rd_bin_cntr (.C(rd_clk), .CE(E), .D(\gc0.count_reg[12]_i_1_n_7 ), - .Q(rd_pntr_plus1), + .Q(D[12]), .R(1'b0)); CARRY4 \gc0.count_reg[12]_i_1 (.CI(\gc0.count_reg[8]_i_1_n_0 ), - .CO(\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CO({\NLW_gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:1],\gc0.count_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED [3:1],\gc0.count_reg[12]_i_1_n_7 }), - .S({1'b0,1'b0,1'b0,\gc0.count[12]_i_2_n_0 })); + .O({\NLW_gc0.count_reg[12]_i_1_O_UNCONNECTED [3:2],\gc0.count_reg[12]_i_1_n_6 ,\gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,\gc0.count[12]_i_2_n_0 ,\gc0.count[12]_i_3_n_0 })); + FDRE #( + .INIT(1'b0)) + \gc0.count_reg[13] + (.C(rd_clk), + .CE(E), + .D(\gc0.count_reg[12]_i_1_n_6 ), + .Q(D[13]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gc0.count_reg[1] @@ -6363,241 +9088,112 @@ module rx_packet_fifo_rd_bin_cntr .D(\gc0.count_reg[8]_i_1_n_6 ), .Q(D[9]), .R(1'b0)); - LUT2 #( - .INIT(4'h9)) - \gmux.gm[6].gms.ms_i_1__1 - (.I0(Q[12]), - .I1(WR_PNTR_RD), - .O(ram_empty_fb_i_reg)); - LUT2 #( - .INIT(4'h9)) - \gmux.gm[6].gms.ms_i_1__2 - (.I0(rd_pntr_plus1), - .I1(WR_PNTR_RD), - .O(ram_empty_fb_i_reg_0)); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[0]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .O(I6[0])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[10]_i_1 - (.I0(Q[10]), - .I1(Q[11]), - .O(I6[10])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[11]_i_1 - (.I0(Q[11]), - .I1(Q[12]), - .O(I6[11])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[1]_i_1 - (.I0(Q[1]), - .I1(Q[2]), - .O(I6[1])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[2]_i_1 - (.I0(Q[2]), - .I1(Q[3]), - .O(I6[2])); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[3]_i_1 - (.I0(Q[3]), - .I1(Q[4]), - .O(I6[3])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[4]_i_1 - (.I0(Q[4]), - .I1(Q[5]), - .O(I6[4])); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[5]_i_1 - (.I0(Q[5]), - .I1(Q[6]), - .O(I6[5])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[6]_i_1 - (.I0(Q[6]), - .I1(Q[7]), - .O(I6[6])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[7]_i_1 - (.I0(Q[7]), - .I1(Q[8]), - .O(I6[7])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[8]_i_1 - (.I0(Q[8]), - .I1(Q[9]), - .O(I6[8])); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_gc[9]_i_1 - (.I0(Q[9]), - .I1(Q[10]), - .O(I6[9])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT4 #( - .INIT(16'hFB08)) - \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1 - (.I0(Q[12]), - .I1(rd_en), - .I2(out), - .I3(sel_pipe), - .O(\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] )); endmodule (* ORIG_REF_NAME = "rd_logic" *) module rx_packet_fifo_rd_logic (empty, + out, prog_empty, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , Q, - \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] , - I6, - enb_array, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , rd_clk, rd_en, WR_PNTR_RD, - sel_pipe, S, \gnxpm_cdc.wr_pntr_bin_reg[7] , \gnxpm_cdc.wr_pntr_bin_reg[11] , - \gnxpm_cdc.wr_pntr_bin_reg[12] ); + \gnxpm_cdc.wr_pntr_bin_reg[13] ); output empty; + output out; output prog_empty; output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - output [12:0]Q; - output \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; - output [11:0]I6; - output [0:0]enb_array; - output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + output [13:0]Q; input rd_clk; input rd_en; - input [12:0]WR_PNTR_RD; - input sel_pipe; + input [13:0]WR_PNTR_RD; input [3:0]S; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; - input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[12] ; + input [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; - wire [11:0]I6; - wire [12:0]Q; + wire [13:0]Q; wire [3:0]S; - wire [12:0]WR_PNTR_RD; + wire [13:0]WR_PNTR_RD; wire empty; - wire [0:0]enb_array; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; - wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[12] ; + wire [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; - wire \gras.rsts_n_3 ; - wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ; + wire \gras.rsts_n_2 ; + wire out; wire p_0_out; - wire p_2_out; wire prog_empty; wire rd_clk; wire rd_en; - wire [11:0]rd_pntr_plus1; - wire rpntr_n_12; - wire rpntr_n_26; - wire sel_pipe; + wire [13:0]rd_pntr_plus1; rx_packet_fifo_rd_pe_as \gras.gpe.rdpe (.S(S), - .WR_PNTR_RD(WR_PNTR_RD[11:0]), + .WR_PNTR_RD(WR_PNTR_RD[12:0]), .\gnxpm_cdc.wr_pntr_bin_reg[11] (\gnxpm_cdc.wr_pntr_bin_reg[11] ), - .\gnxpm_cdc.wr_pntr_bin_reg[12] (\gnxpm_cdc.wr_pntr_bin_reg[12] ), + .\gnxpm_cdc.wr_pntr_bin_reg[13] (\gnxpm_cdc.wr_pntr_bin_reg[13] ), .\gnxpm_cdc.wr_pntr_bin_reg[7] (\gnxpm_cdc.wr_pntr_bin_reg[7] ), - .out(p_2_out), + .out(out), .p_0_out(p_0_out), .prog_empty(prog_empty), .rd_clk(rd_clk)); rx_packet_fifo_rd_status_flags_as \gras.rsts (.D(rd_pntr_plus1), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), - .E(\gras.rsts_n_3 ), + .E(\gras.rsts_n_2 ), .Q(Q), - .WR_PNTR_RD(WR_PNTR_RD[11:0]), + .WR_PNTR_RD(WR_PNTR_RD), .empty(empty), - .\gc0.count_d1_reg[12] (rpntr_n_12), - .\gc0.count_reg[12] (rpntr_n_26), - .out(p_2_out), + .out(out), .p_0_out(p_0_out), .rd_clk(rd_clk), .rd_en(rd_en)); rx_packet_fifo_rd_bin_cntr rpntr (.D(rd_pntr_plus1), - .E(\gras.rsts_n_3 ), - .I6(I6), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .E(\gras.rsts_n_2 ), .Q(Q), - .WR_PNTR_RD(WR_PNTR_RD[12]), - .enb_array(enb_array), - .\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] (\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0] ), - .out(p_2_out), - .ram_empty_fb_i_reg(rpntr_n_12), - .ram_empty_fb_i_reg_0(rpntr_n_26), + .out(out), .rd_clk(rd_clk), - .rd_en(rd_en), - .sel_pipe(sel_pipe)); + .rd_en(rd_en)); endmodule (* ORIG_REF_NAME = "rd_pe_as" *) module rx_packet_fifo_rd_pe_as (prog_empty, - rd_clk, p_0_out, WR_PNTR_RD, S, \gnxpm_cdc.wr_pntr_bin_reg[7] , \gnxpm_cdc.wr_pntr_bin_reg[11] , - \gnxpm_cdc.wr_pntr_bin_reg[12] , + \gnxpm_cdc.wr_pntr_bin_reg[13] , + rd_clk, out); output prog_empty; - input rd_clk; input p_0_out; - input [11:0]WR_PNTR_RD; + input [12:0]WR_PNTR_RD; input [3:0]S; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; - input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[12] ; + input [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; + input rd_clk; input out; wire [3:0]S; - wire [11:0]WR_PNTR_RD; - wire [13:11]diff_pntr_pad; + wire [12:0]WR_PNTR_RD; + wire [14:11]diff_pntr_pad; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[11] ; - wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[12] ; + wire [1:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[7] ; wire \gpe1.prog_empty_i_i_1_n_0 ; wire out; wire p_0_out; - wire [13:11]plusOp; + wire [14:11]plusOp; wire plusOp_carry__0_n_0; wire plusOp_carry__0_n_1; wire plusOp_carry__0_n_2; @@ -6606,6 +9202,7 @@ module rx_packet_fifo_rd_pe_as wire plusOp_carry__1_n_1; wire plusOp_carry__1_n_2; wire plusOp_carry__1_n_3; + wire plusOp_carry__2_n_3; wire plusOp_carry_n_0; wire plusOp_carry_n_1; wire plusOp_carry_n_2; @@ -6615,8 +9212,8 @@ module rx_packet_fifo_rd_pe_as wire [3:0]NLW_plusOp_carry_O_UNCONNECTED; wire [3:0]NLW_plusOp_carry__0_O_UNCONNECTED; wire [1:0]NLW_plusOp_carry__1_O_UNCONNECTED; - wire [3:0]NLW_plusOp_carry__2_CO_UNCONNECTED; - wire [3:1]NLW_plusOp_carry__2_O_UNCONNECTED; + wire [3:1]NLW_plusOp_carry__2_CO_UNCONNECTED; + wire [3:2]NLW_plusOp_carry__2_O_UNCONNECTED; FDRE #( .INIT(1'b0)) @@ -6642,14 +9239,23 @@ module rx_packet_fifo_rd_pe_as .D(plusOp[13]), .Q(diff_pntr_pad[13]), .R(1'b0)); - LUT5 #( - .INIT(32'h8888888B)) + FDRE #( + .INIT(1'b0)) + \gdiff.diff_pntr_pad_reg[14] + (.C(rd_clk), + .CE(1'b1), + .D(plusOp[14]), + .Q(diff_pntr_pad[14]), + .R(1'b0)); + LUT6 #( + .INIT(64'h888888888888888B)) \gpe1.prog_empty_i_i_1 (.I0(prog_empty), .I1(out), .I2(diff_pntr_pad[13]), - .I3(diff_pntr_pad[11]), + .I3(diff_pntr_pad[14]), .I4(diff_pntr_pad[12]), + .I5(diff_pntr_pad[11]), .O(\gpe1.prog_empty_i_i_1_n_0 )); FDRE #( .INIT(1'b1)) @@ -6682,52 +9288,40 @@ module rx_packet_fifo_rd_pe_as .S(\gnxpm_cdc.wr_pntr_bin_reg[11] )); CARRY4 plusOp_carry__2 (.CI(plusOp_carry__1_n_0), - .CO(NLW_plusOp_carry__2_CO_UNCONNECTED[3:0]), + .CO({NLW_plusOp_carry__2_CO_UNCONNECTED[3:1],plusOp_carry__2_n_3}), .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({NLW_plusOp_carry__2_O_UNCONNECTED[3:1],plusOp[13]}), - .S({1'b0,1'b0,1'b0,\gnxpm_cdc.wr_pntr_bin_reg[12] })); + .DI({1'b0,1'b0,1'b0,WR_PNTR_RD[12]}), + .O({NLW_plusOp_carry__2_O_UNCONNECTED[3:2],plusOp[14:13]}), + .S({1'b0,1'b0,\gnxpm_cdc.wr_pntr_bin_reg[13] })); endmodule (* ORIG_REF_NAME = "rd_status_flags_as" *) module rx_packet_fifo_rd_status_flags_as (empty, out, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , E, p_0_out, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , - \gc0.count_d1_reg[12] , - \gc0.count_reg[12] , rd_clk, rd_en, - Q, WR_PNTR_RD, + Q, D); output empty; output out; - output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; output [0:0]E; output p_0_out; - output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; - input \gc0.count_d1_reg[12] ; - input \gc0.count_reg[12] ; input rd_clk; input rd_en; - input [12:0]Q; - input [11:0]WR_PNTR_RD; - input [11:0]D; + input [13:0]WR_PNTR_RD; + input [13:0]Q; + input [13:0]D; - wire [11:0]D; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [13:0]D; wire [0:0]E; - wire [12:0]Q; - wire [11:0]WR_PNTR_RD; + wire [13:0]Q; + wire [13:0]WR_PNTR_RD; wire comp0; wire comp1; - wire \gc0.count_d1_reg[12] ; - wire \gc0.count_reg[12] ; wire p_0_out; (* DONT_TOUCH *) wire ram_empty_fb_i; (* DONT_TOUCH *) wire ram_empty_i; @@ -6737,32 +9331,17 @@ module rx_packet_fifo_rd_status_flags_as assign empty = ram_empty_i; assign out = ram_empty_fb_i; - LUT2 #( - .INIT(4'h2)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0 - (.I0(rd_en), - .I1(ram_empty_fb_i), - .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); - LUT3 #( - .INIT(8'h04)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1 - (.I0(ram_empty_fb_i), - .I1(rd_en), - .I2(Q[12]), - .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); - rx_packet_fifo_compare_1 c0 - (.Q(Q[11:0]), + rx_packet_fifo_compare_2 c0 + (.Q(Q), .WR_PNTR_RD(WR_PNTR_RD), - .comp0(comp0), - .\gc0.count_d1_reg[12] (\gc0.count_d1_reg[12] )); - rx_packet_fifo_compare_2 c1 + .comp0(comp0)); + rx_packet_fifo_compare_3 c1 (.D(D), .WR_PNTR_RD(WR_PNTR_RD), - .comp1(comp1), - .\gc0.count_reg[12] (\gc0.count_reg[12] )); + .comp1(comp1)); LUT2 #( .INIT(4'h2)) - \gc0.count_d1[12]_i_1 + \gc0.count_d1[13]_i_1 (.I0(rd_en), .I1(ram_empty_fb_i), .O(E)); @@ -6809,15 +9388,15 @@ module rx_packet_fifo_synchronizer_ff (out, in0, rd_clk); - output [12:0]out; - input [12:0]in0; + output [13:0]out; + input [13:0]in0; input rd_clk; - (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; - wire [12:0]in0; + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; + wire [13:0]in0; wire rd_clk; - assign out[12:0] = Q_reg; + assign out[13:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -6865,6 +9444,17 @@ module rx_packet_fifo_synchronizer_ff (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(in0[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -6964,19 +9554,19 @@ module rx_packet_fifo_synchronizer_ff endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) -module rx_packet_fifo_synchronizer_ff_3 +module rx_packet_fifo_synchronizer_ff_4 (out, Q, wr_clk); - output [12:0]out; - input [12:0]Q; + output [13:0]out; + input [13:0]Q; input wr_clk; - wire [12:0]Q; - (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire [13:0]Q; + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; wire wr_clk; - assign out[12:0] = Q_reg; + assign out[13:0] = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -7024,6 +9614,17 @@ module rx_packet_fifo_synchronizer_ff_3 (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(wr_clk), + .CE(1'b1), + .D(Q[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -7123,24 +9724,32 @@ module rx_packet_fifo_synchronizer_ff_3 endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) -module rx_packet_fifo_synchronizer_ff_4 - (\gnxpm_cdc.wr_pntr_bin_reg[12] , +module rx_packet_fifo_synchronizer_ff_5 + (\gnxpm_cdc.wr_pntr_bin_reg[13] , D, out, rd_clk); - output [0:0]\gnxpm_cdc.wr_pntr_bin_reg[12] ; - output [11:0]D; - input [12:0]out; + output [0:0]\gnxpm_cdc.wr_pntr_bin_reg[13] ; + output [12:0]D; + input [13:0]out; input rd_clk; - wire [11:0]D; - (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; + wire [12:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; wire \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ; wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ; - wire [12:0]out; + wire \gnxpm_cdc.wr_pntr_bin[2]_i_3_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[5]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[5]_i_3_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[5]_i_4_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[6]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 ; + wire [13:0]out; wire rd_clk; - assign \gnxpm_cdc.wr_pntr_bin_reg[12] [0] = Q_reg[12]; + assign \gnxpm_cdc.wr_pntr_bin_reg[13] [0] = Q_reg[13]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -7188,6 +9797,17 @@ module rx_packet_fifo_synchronizer_ff_4 (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(rd_clk), + .CE(1'b1), + .D(out[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -7284,147 +9904,217 @@ module rx_packet_fifo_synchronizer_ff_4 .D(out[9]), .Q(Q_reg[9]), .R(1'b0)); - LUT6 #( - .INIT(64'h6996966996696996)) - \gnxpm_cdc.wr_pntr_bin[0]_i_1 - (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), - .I1(Q_reg[1]), - .I2(Q_reg[0]), - .I3(Q_reg[3]), - .I4(Q_reg[2]), - .I5(D[7]), - .O(D[0])); LUT3 #( .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[0]_i_1 + (.I0(Q_reg[1]), + .I1(Q_reg[0]), + .I2(D[2]), + .O(D[0])); + LUT4 #( + .INIT(16'h6996)) \gnxpm_cdc.wr_pntr_bin[10]_i_1 (.I0(Q_reg[11]), .I1(Q_reg[10]), - .I2(Q_reg[12]), + .I2(Q_reg[13]), + .I3(Q_reg[12]), .O(D[10])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_bin[11]_i_1 - (.I0(Q_reg[11]), - .I1(Q_reg[12]), - .O(D[11])); - LUT5 #( - .INIT(32'h96696996)) - \gnxpm_cdc.wr_pntr_bin[1]_i_1 - (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), - .I1(Q_reg[2]), - .I2(Q_reg[1]), - .I3(Q_reg[3]), - .I4(D[7]), - .O(D[1])); LUT3 #( .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[11]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(Q_reg[13]), + .O(D[11])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[12]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[13]), + .O(D[12])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 ), + .I1(Q_reg[7]), + .I2(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), + .O(D[1])); + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[1]_i_2 (.I0(Q_reg[5]), - .I1(Q_reg[4]), - .I2(Q_reg[6]), + .I1(Q_reg[6]), + .I2(Q_reg[2]), + .I3(Q_reg[1]), + .I4(Q_reg[4]), + .I5(Q_reg[3]), .O(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[2]_i_1 - (.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), - .I1(Q_reg[7]), - .I2(Q_reg[3]), - .I3(Q_reg[2]), - .I4(Q_reg[4]), - .I5(D[8]), + (.I0(Q_reg[4]), + .I1(Q_reg[5]), + .I2(Q_reg[2]), + .I3(Q_reg[3]), + .I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ), + .I5(\gnxpm_cdc.wr_pntr_bin[2]_i_3_n_0 ), .O(D[2])); LUT2 #( .INIT(4'h6)) \gnxpm_cdc.wr_pntr_bin[2]_i_2 - (.I0(Q_reg[5]), + (.I0(Q_reg[10]), .I1(Q_reg[6]), .O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) - \gnxpm_cdc.wr_pntr_bin[3]_i_1 - (.I0(Q_reg[6]), + \gnxpm_cdc.wr_pntr_bin[2]_i_3 + (.I0(Q_reg[8]), .I1(Q_reg[7]), - .I2(Q_reg[4]), - .I3(Q_reg[3]), - .I4(Q_reg[5]), - .I5(D[8]), + .I2(Q_reg[12]), + .I3(Q_reg[9]), + .I4(Q_reg[13]), + .I5(Q_reg[11]), + .O(\gnxpm_cdc.wr_pntr_bin[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[3]_i_1 + (.I0(Q_reg[11]), + .I1(Q_reg[12]), + .I2(Q_reg[7]), + .I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ), + .I4(Q_reg[13]), + .I5(Q_reg[8]), .O(D[3])); LUT6 #( .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[3]_i_2 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[4]), + .I3(Q_reg[3]), + .I4(Q_reg[6]), + .I5(Q_reg[5]), + .O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[4]_i_1 (.I0(Q_reg[7]), - .I1(Q_reg[8]), + .I1(\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ), + .I2(Q_reg[11]), + .I3(Q_reg[8]), + .I4(Q_reg[13]), + .O(D[4])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[4]_i_2 + (.I0(Q_reg[9]), + .I1(Q_reg[12]), .I2(Q_reg[5]), .I3(Q_reg[4]), - .I4(Q_reg[6]), - .I5(D[9]), - .O(D[4])); - LUT5 #( - .INIT(32'h96696996)) + .I4(Q_reg[10]), + .I5(Q_reg[6]), + .O(\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[5]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(\gnxpm_cdc.wr_pntr_bin[5]_i_2_n_0 ), + .I3(\gnxpm_cdc.wr_pntr_bin[5]_i_3_n_0 ), + .I4(Q_reg[7]), + .I5(\gnxpm_cdc.wr_pntr_bin[5]_i_4_n_0 ), + .O(D[5])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[5]_i_2 + (.I0(Q_reg[6]), + .I1(Q_reg[5]), + .O(\gnxpm_cdc.wr_pntr_bin[5]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[5]_i_3 + (.I0(Q_reg[9]), + .I1(Q_reg[10]), + .O(\gnxpm_cdc.wr_pntr_bin[5]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[5]_i_4 + (.I0(Q_reg[13]), + .I1(Q_reg[8]), + .O(\gnxpm_cdc.wr_pntr_bin[5]_i_4_n_0 )); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[6]_i_1 (.I0(Q_reg[7]), .I1(Q_reg[8]), - .I2(Q_reg[5]), - .I3(Q_reg[6]), - .I4(D[9]), - .O(D[5])); - LUT5 #( - .INIT(32'h96696996)) - \gnxpm_cdc.wr_pntr_bin[6]_i_1 - (.I0(Q_reg[8]), - .I1(Q_reg[9]), - .I2(Q_reg[6]), - .I3(Q_reg[7]), - .I4(D[10]), + .I2(\gnxpm_cdc.wr_pntr_bin[6]_i_2_n_0 ), .O(D[6])); LUT6 #( .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[6]_i_2 + (.I0(Q_reg[11]), + .I1(Q_reg[13]), + .I2(Q_reg[10]), + .I3(Q_reg[6]), + .I4(Q_reg[12]), + .I5(Q_reg[9]), + .O(\gnxpm_cdc.wr_pntr_bin[6]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) \gnxpm_cdc.wr_pntr_bin[7]_i_1 - (.I0(Q_reg[9]), - .I1(Q_reg[7]), - .I2(Q_reg[8]), - .I3(Q_reg[12]), - .I4(Q_reg[10]), - .I5(Q_reg[11]), + (.I0(Q_reg[7]), + .I1(\gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 ), .O(D[7])); - LUT5 #( - .INIT(32'h96696996)) + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[7]_i_2 + (.I0(Q_reg[13]), + .I1(Q_reg[8]), + .I2(Q_reg[9]), + .I3(Q_reg[10]), + .I4(Q_reg[11]), + .I5(Q_reg[12]), + .O(\gnxpm_cdc.wr_pntr_bin[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.wr_pntr_bin[8]_i_1 (.I0(Q_reg[10]), .I1(Q_reg[8]), .I2(Q_reg[9]), - .I3(Q_reg[12]), + .I3(Q_reg[13]), .I4(Q_reg[11]), + .I5(Q_reg[12]), .O(D[8])); - LUT4 #( - .INIT(16'h6996)) + LUT5 #( + .INIT(32'h96696996)) \gnxpm_cdc.wr_pntr_bin[9]_i_1 - (.I0(Q_reg[10]), + (.I0(Q_reg[11]), .I1(Q_reg[9]), - .I2(Q_reg[12]), - .I3(Q_reg[11]), + .I2(Q_reg[10]), + .I3(Q_reg[13]), + .I4(Q_reg[12]), .O(D[9])); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) -module rx_packet_fifo_synchronizer_ff_5 - (\gnxpm_cdc.rd_pntr_bin_reg[12] , +module rx_packet_fifo_synchronizer_ff_6 + (\gnxpm_cdc.rd_pntr_bin_reg[13] , D, out, wr_clk); - output [0:0]\gnxpm_cdc.rd_pntr_bin_reg[12] ; - output [11:0]D; - input [12:0]out; + output [0:0]\gnxpm_cdc.rd_pntr_bin_reg[13] ; + output [12:0]D; + input [13:0]out; input wr_clk; - wire [11:0]D; - (* async_reg = "true" *) (* msgon = "true" *) wire [12:0]Q_reg; - wire \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ; - wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ; - wire [12:0]out; + wire [12:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [13:0]Q_reg; + wire \gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 ; + wire \gnxpm_cdc.rd_pntr_bin[7]_i_2_n_0 ; + wire [13:0]out; wire wr_clk; - assign \gnxpm_cdc.rd_pntr_bin_reg[12] [0] = Q_reg[12]; + assign \gnxpm_cdc.rd_pntr_bin_reg[13] [0] = Q_reg[13]; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -7472,6 +10162,17 @@ module rx_packet_fifo_synchronizer_ff_5 (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[13] + (.C(wr_clk), + .CE(1'b1), + .D(out[13]), + .Q(Q_reg[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) FDRE #( .INIT(1'b0)) \Q_reg_reg[1] @@ -7571,155 +10272,163 @@ module rx_packet_fifo_synchronizer_ff_5 LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[0]_i_1 - (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), - .I1(Q_reg[1]), - .I2(Q_reg[0]), - .I3(Q_reg[3]), - .I4(Q_reg[2]), - .I5(D[7]), + (.I0(Q_reg[1]), + .I1(Q_reg[0]), + .I2(Q_reg[2]), + .I3(Q_reg[4]), + .I4(D[5]), + .I5(Q_reg[3]), .O(D[0])); - LUT3 #( - .INIT(8'h96)) + LUT4 #( + .INIT(16'h6996)) \gnxpm_cdc.rd_pntr_bin[10]_i_1 (.I0(Q_reg[11]), .I1(Q_reg[10]), - .I2(Q_reg[12]), + .I2(Q_reg[13]), + .I3(Q_reg[12]), .O(D[10])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.rd_pntr_bin[11]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(Q_reg[13]), + .O(D[11])); LUT2 #( .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_bin[11]_i_1 - (.I0(Q_reg[11]), - .I1(Q_reg[12]), - .O(D[11])); + \gnxpm_cdc.rd_pntr_bin[12]_i_1 + (.I0(Q_reg[12]), + .I1(Q_reg[13]), + .O(D[12])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[1]_i_1 - (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), - .I1(Q_reg[2]), - .I2(Q_reg[1]), - .I3(Q_reg[3]), - .I4(D[7]), - .O(D[1])); - LUT3 #( - .INIT(8'h96)) - \gnxpm_cdc.rd_pntr_bin[1]_i_2 - (.I0(Q_reg[5]), + (.I0(Q_reg[2]), .I1(Q_reg[4]), - .I2(Q_reg[6]), - .O(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 )); + .I2(D[5]), + .I3(Q_reg[3]), + .I4(Q_reg[1]), + .O(D[1])); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[2]_i_1 - (.I0(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ), - .I1(Q_reg[7]), - .I2(Q_reg[3]), - .I3(Q_reg[2]), + (.I0(Q_reg[3]), + .I1(Q_reg[5]), + .I2(D[7]), + .I3(Q_reg[6]), .I4(Q_reg[4]), - .I5(D[8]), + .I5(Q_reg[2]), .O(D[2])); - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.rd_pntr_bin[2]_i_2 - (.I0(Q_reg[5]), - .I1(Q_reg[6]), - .O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 )); - LUT6 #( - .INIT(64'h6996966996696996)) - \gnxpm_cdc.rd_pntr_bin[3]_i_1 - (.I0(Q_reg[6]), - .I1(Q_reg[7]), - .I2(Q_reg[4]), - .I3(Q_reg[3]), - .I4(Q_reg[5]), - .I5(D[8]), - .O(D[3])); - LUT6 #( - .INIT(64'h6996966996696996)) - \gnxpm_cdc.rd_pntr_bin[4]_i_1 - (.I0(Q_reg[7]), - .I1(Q_reg[8]), - .I2(Q_reg[5]), - .I3(Q_reg[4]), - .I4(Q_reg[6]), - .I5(D[9]), - .O(D[4])); LUT5 #( .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[3]_i_1 + (.I0(Q_reg[4]), + .I1(Q_reg[6]), + .I2(D[7]), + .I3(Q_reg[5]), + .I4(Q_reg[3]), + .O(D[3])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[4]_i_1 + (.I0(Q_reg[5]), + .I1(D[7]), + .I2(Q_reg[6]), + .I3(Q_reg[4]), + .O(D[4])); + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[5]_i_1 - (.I0(Q_reg[7]), - .I1(Q_reg[8]), - .I2(Q_reg[5]), - .I3(Q_reg[6]), - .I4(D[9]), + (.I0(Q_reg[6]), + .I1(Q_reg[13]), + .I2(Q_reg[7]), + .I3(Q_reg[8]), + .I4(\gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 ), + .I5(Q_reg[5]), .O(D[5])); LUT5 #( .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[6]_i_1 - (.I0(Q_reg[8]), - .I1(Q_reg[9]), - .I2(Q_reg[6]), - .I3(Q_reg[7]), - .I4(D[10]), + (.I0(\gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 ), + .I1(Q_reg[8]), + .I2(Q_reg[7]), + .I3(Q_reg[13]), + .I4(Q_reg[6]), .O(D[6])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[6]_i_2 + (.I0(Q_reg[12]), + .I1(Q_reg[11]), + .I2(Q_reg[10]), + .I3(Q_reg[9]), + .O(\gnxpm_cdc.rd_pntr_bin[6]_i_2_n_0 )); LUT6 #( .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[7]_i_1 - (.I0(Q_reg[9]), + (.I0(Q_reg[13]), .I1(Q_reg[7]), .I2(Q_reg[8]), - .I3(Q_reg[12]), - .I4(Q_reg[10]), - .I5(Q_reg[11]), + .I3(\gnxpm_cdc.rd_pntr_bin[7]_i_2_n_0 ), + .I4(Q_reg[11]), + .I5(Q_reg[12]), .O(D[7])); - LUT5 #( - .INIT(32'h96696996)) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[7]_i_2 + (.I0(Q_reg[9]), + .I1(Q_reg[10]), + .O(\gnxpm_cdc.rd_pntr_bin[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) \gnxpm_cdc.rd_pntr_bin[8]_i_1 (.I0(Q_reg[10]), .I1(Q_reg[8]), .I2(Q_reg[9]), - .I3(Q_reg[12]), + .I3(Q_reg[13]), .I4(Q_reg[11]), + .I5(Q_reg[12]), .O(D[8])); - LUT4 #( - .INIT(16'h6996)) + LUT5 #( + .INIT(32'h96696996)) \gnxpm_cdc.rd_pntr_bin[9]_i_1 - (.I0(Q_reg[10]), + (.I0(Q_reg[11]), .I1(Q_reg[9]), - .I2(Q_reg[12]), - .I3(Q_reg[11]), + .I2(Q_reg[10]), + .I3(Q_reg[13]), + .I4(Q_reg[12]), .O(D[9])); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) module rx_packet_fifo_wr_bin_cntr (D, - ena_array, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , Q, - \gic0.gc0.count_d2_reg[12]_0 , - bin2gray, - ram_full_fb_i_reg, + \gic0.gc0.count_d2_reg[13]_0 , + E, wr_clk, - out, - wr_en); - output [12:0]D; - output [0:0]ena_array; - output [12:0]Q; - output [12:0]\gic0.gc0.count_d2_reg[12]_0 ; - output [11:0]bin2gray; - input ram_full_fb_i_reg; + wr_en, + out); + output [13:0]D; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [13:0]Q; + output [13:0]\gic0.gc0.count_d2_reg[13]_0 ; + input [0:0]E; input wr_clk; - input out; input wr_en; + input out; - wire [12:0]D; - wire [12:0]Q; - wire [11:0]bin2gray; - wire [0:0]ena_array; + wire [13:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]E; + wire [13:0]Q; wire \gic0.gc0.count[0]_i_2_n_0 ; wire \gic0.gc0.count[0]_i_3_n_0 ; wire \gic0.gc0.count[0]_i_4_n_0 ; wire \gic0.gc0.count[0]_i_5_n_0 ; wire \gic0.gc0.count[12]_i_2_n_0 ; + wire \gic0.gc0.count[12]_i_3_n_0 ; wire \gic0.gc0.count[4]_i_2_n_0 ; wire \gic0.gc0.count[4]_i_3_n_0 ; wire \gic0.gc0.count[4]_i_4_n_0 ; @@ -7728,7 +10437,7 @@ module rx_packet_fifo_wr_bin_cntr wire \gic0.gc0.count[8]_i_3_n_0 ; wire \gic0.gc0.count[8]_i_4_n_0 ; wire \gic0.gc0.count[8]_i_5_n_0 ; - wire [12:0]\gic0.gc0.count_d2_reg[12]_0 ; + wire [13:0]\gic0.gc0.count_d2_reg[13]_0 ; wire \gic0.gc0.count_reg[0]_i_1_n_0 ; wire \gic0.gc0.count_reg[0]_i_1_n_1 ; wire \gic0.gc0.count_reg[0]_i_1_n_2 ; @@ -7737,6 +10446,8 @@ module rx_packet_fifo_wr_bin_cntr wire \gic0.gc0.count_reg[0]_i_1_n_5 ; wire \gic0.gc0.count_reg[0]_i_1_n_6 ; wire \gic0.gc0.count_reg[0]_i_1_n_7 ; + wire \gic0.gc0.count_reg[12]_i_1_n_3 ; + wire \gic0.gc0.count_reg[12]_i_1_n_6 ; wire \gic0.gc0.count_reg[12]_i_1_n_7 ; wire \gic0.gc0.count_reg[4]_i_1_n_0 ; wire \gic0.gc0.count_reg[4]_i_1_n_1 ; @@ -7755,19 +10466,19 @@ module rx_packet_fifo_wr_bin_cntr wire \gic0.gc0.count_reg[8]_i_1_n_6 ; wire \gic0.gc0.count_reg[8]_i_1_n_7 ; wire out; - wire ram_full_fb_i_reg; wire wr_clk; wire wr_en; - wire [3:0]\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED ; - wire [3:1]\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED ; + wire [3:1]\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:2]\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED ; - LUT3 #( - .INIT(8'h20)) + LUT4 #( + .INIT(16'h0080)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 - (.I0(Q[12]), - .I1(out), + (.I0(Q[13]), + .I1(Q[12]), .I2(wr_en), - .O(ena_array)); + .I3(out), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); LUT1 #( .INIT(2'h2)) \gic0.gc0.count[0]_i_2 @@ -7791,8 +10502,13 @@ module rx_packet_fifo_wr_bin_cntr LUT1 #( .INIT(2'h2)) \gic0.gc0.count[12]_i_2 - (.I0(D[12]), + (.I0(D[13]), .O(\gic0.gc0.count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[12]_i_3 + (.I0(D[12]), + .O(\gic0.gc0.count[12]_i_3_n_0 )); LUT1 #( .INIT(2'h2)) \gic0.gc0.count[4]_i_2 @@ -7837,215 +10553,231 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b1)) \gic0.gc0.count_d1_reg[0] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[0]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [0]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[10] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[10]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [10]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[11] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[11]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [11]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[12] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[12]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [12]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[13] + (.C(wr_clk), + .CE(E), + .D(D[13]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[1] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[1]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [1]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[2] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[2]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [2]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[3] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[3]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [3]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[4] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[4]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [4]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[5] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[5]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [5]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[6] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[6]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [6]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[7] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[7]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [7]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[8] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[8]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [8]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d1_reg[9] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(D[9]), - .Q(\gic0.gc0.count_d2_reg[12]_0 [9]), + .Q(\gic0.gc0.count_d2_reg[13]_0 [9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[0] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [0]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [0]), .Q(Q[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[10] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [10]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [10]), .Q(Q[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[11] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [11]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [11]), .Q(Q[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[12] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [12]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [12]), .Q(Q[12]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[13] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [13]), + .Q(Q[13]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[1] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [1]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [1]), .Q(Q[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[2] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [2]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [2]), .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[3] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [3]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [3]), .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[4] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [4]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [4]), .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[5] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [5]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [5]), .Q(Q[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[6] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [6]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [6]), .Q(Q[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[7] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [7]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [7]), .Q(Q[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[8] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [8]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [8]), .Q(Q[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_d2_reg[9] (.C(wr_clk), - .CE(ram_full_fb_i_reg), - .D(\gic0.gc0.count_d2_reg[12]_0 [9]), + .CE(E), + .D(\gic0.gc0.count_d2_reg[13]_0 [9]), .Q(Q[9]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gic0.gc0.count_reg[0] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[0]_i_1_n_7 ), .Q(D[0]), .R(1'b0)); @@ -8060,7 +10792,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[10] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[8]_i_1_n_5 ), .Q(D[10]), .R(1'b0)); @@ -8068,7 +10800,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[11] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[8]_i_1_n_4 ), .Q(D[11]), .R(1'b0)); @@ -8076,22 +10808,30 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[12] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[12]_i_1_n_7 ), .Q(D[12]), .R(1'b0)); CARRY4 \gic0.gc0.count_reg[12]_i_1 (.CI(\gic0.gc0.count_reg[8]_i_1_n_0 ), - .CO(\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CO({\NLW_gic0.gc0.count_reg[12]_i_1_CO_UNCONNECTED [3:1],\gic0.gc0.count_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED [3:1],\gic0.gc0.count_reg[12]_i_1_n_7 }), - .S({1'b0,1'b0,1'b0,\gic0.gc0.count[12]_i_2_n_0 })); + .O({\NLW_gic0.gc0.count_reg[12]_i_1_O_UNCONNECTED [3:2],\gic0.gc0.count_reg[12]_i_1_n_6 ,\gic0.gc0.count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,\gic0.gc0.count[12]_i_2_n_0 ,\gic0.gc0.count[12]_i_3_n_0 })); + FDRE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[13] + (.C(wr_clk), + .CE(E), + .D(\gic0.gc0.count_reg[12]_i_1_n_6 ), + .Q(D[13]), + .R(1'b0)); FDRE #( .INIT(1'b1)) \gic0.gc0.count_reg[1] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[0]_i_1_n_6 ), .Q(D[1]), .R(1'b0)); @@ -8099,7 +10839,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[2] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[0]_i_1_n_5 ), .Q(D[2]), .R(1'b0)); @@ -8107,7 +10847,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[3] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[0]_i_1_n_4 ), .Q(D[3]), .R(1'b0)); @@ -8115,7 +10855,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[4] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[4]_i_1_n_7 ), .Q(D[4]), .R(1'b0)); @@ -8130,7 +10870,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[5] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[4]_i_1_n_6 ), .Q(D[5]), .R(1'b0)); @@ -8138,7 +10878,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[6] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[4]_i_1_n_5 ), .Q(D[6]), .R(1'b0)); @@ -8146,7 +10886,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[7] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[4]_i_1_n_4 ), .Q(D[7]), .R(1'b0)); @@ -8154,7 +10894,7 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[8] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[8]_i_1_n_7 ), .Q(D[8]), .R(1'b0)); @@ -8169,167 +10909,68 @@ module rx_packet_fifo_wr_bin_cntr .INIT(1'b0)) \gic0.gc0.count_reg[9] (.C(wr_clk), - .CE(ram_full_fb_i_reg), + .CE(E), .D(\gic0.gc0.count_reg[8]_i_1_n_6 ), .Q(D[9]), .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[0]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .O(bin2gray[0])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[10]_i_1 - (.I0(Q[10]), - .I1(Q[11]), - .O(bin2gray[10])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[11]_i_1 - (.I0(Q[11]), - .I1(Q[12]), - .O(bin2gray[11])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[1]_i_1 - (.I0(Q[1]), - .I1(Q[2]), - .O(bin2gray[1])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[2]_i_1 - (.I0(Q[2]), - .I1(Q[3]), - .O(bin2gray[2])); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[3]_i_1 - (.I0(Q[3]), - .I1(Q[4]), - .O(bin2gray[3])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[4]_i_1 - (.I0(Q[4]), - .I1(Q[5]), - .O(bin2gray[4])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[5]_i_1 - (.I0(Q[5]), - .I1(Q[6]), - .O(bin2gray[5])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[6]_i_1 - (.I0(Q[6]), - .I1(Q[7]), - .O(bin2gray[6])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[7]_i_1 - (.I0(Q[7]), - .I1(Q[8]), - .O(bin2gray[7])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[8]_i_1 - (.I0(Q[8]), - .I1(Q[9]), - .O(bin2gray[8])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT2 #( - .INIT(4'h6)) - \gnxpm_cdc.wr_pntr_gc[9]_i_1 - (.I0(Q[9]), - .I1(Q[10]), - .O(bin2gray[9])); endmodule (* ORIG_REF_NAME = "wr_logic" *) module rx_packet_fifo_wr_logic (full, + out, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , Q, WEA, - D, - \gic0.gc0.count_d2_reg[12] , - bin2gray, - ena_array, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , - \gnxpm_cdc.rd_pntr_bin_reg[12] , - \gnxpm_cdc.rd_pntr_bin_reg[12]_0 , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 , wr_clk, wr_en, RD_PNTR_WR); output full; + output out; output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - output [12:0]Q; + output [13:0]Q; output [0:0]WEA; - output [0:0]D; - output [0:0]\gic0.gc0.count_d2_reg[12] ; - output [11:0]bin2gray; - output [0:0]ena_array; - output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; - input \gnxpm_cdc.rd_pntr_bin_reg[12] ; - input \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; input wr_clk; input wr_en; - input [11:0]RD_PNTR_WR; + input [13:0]RD_PNTR_WR; - wire [0:0]D; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; - wire [12:0]Q; - wire [11:0]RD_PNTR_WR; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ; + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; wire [0:0]WEA; - wire [11:0]bin2gray; - wire [0:0]ena_array; wire full; - wire [0:0]\gic0.gc0.count_d2_reg[12] ; - wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; - wire \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; - wire \gwas.wsts_n_1 ; - wire [11:0]p_13_out; + wire \gwas.wsts_n_2 ; + wire out; + wire [13:0]p_13_out; wire wr_clk; wire wr_en; - wire [11:0]wr_pntr_plus2; + wire [13:0]wr_pntr_plus2; rx_packet_fifo_wr_status_flags_as \gwas.wsts (.D(wr_pntr_plus2), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), - .Q(Q[12]), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ), + .E(\gwas.wsts_n_2 ), + .Q(p_13_out), .RD_PNTR_WR(RD_PNTR_WR), + .WEA(WEA), .full(full), - .\gic0.gc0.count_d1_reg[11] (p_13_out), - .\gic0.gc0.count_d1_reg[12] (WEA), - .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12] ), - .\gnxpm_cdc.rd_pntr_bin_reg[12]_0 (\gnxpm_cdc.rd_pntr_bin_reg[12]_0 ), - .out(\gwas.wsts_n_1 ), + .out(out), .wr_clk(wr_clk), .wr_en(wr_en)); rx_packet_fifo_wr_bin_cntr wpntr - (.D({D,wr_pntr_plus2}), + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ), + .E(\gwas.wsts_n_2 ), .Q(Q), - .bin2gray(bin2gray), - .ena_array(ena_array), - .\gic0.gc0.count_d2_reg[12]_0 ({\gic0.gc0.count_d2_reg[12] ,p_13_out}), - .out(\gwas.wsts_n_1 ), - .ram_full_fb_i_reg(WEA), + .\gic0.gc0.count_d2_reg[13]_0 (p_13_out), + .out(out), .wr_clk(wr_clk), .wr_en(wr_en)); endmodule @@ -8338,42 +10979,36 @@ endmodule module rx_packet_fifo_wr_status_flags_as (full, out, + E, + WEA, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , - \gic0.gc0.count_d1_reg[12] , \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 , - \gnxpm_cdc.rd_pntr_bin_reg[12] , - \gnxpm_cdc.rd_pntr_bin_reg[12]_0 , wr_clk, wr_en, Q, - \gic0.gc0.count_d1_reg[11] , RD_PNTR_WR, D); output full; output out; - output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - output \gic0.gc0.count_d1_reg[12] ; - output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; - input \gnxpm_cdc.rd_pntr_bin_reg[12] ; - input \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; + output [0:0]E; + output [0:0]WEA; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; input wr_clk; input wr_en; - input [0:0]Q; - input [11:0]\gic0.gc0.count_d1_reg[11] ; - input [11:0]RD_PNTR_WR; - input [11:0]D; + input [13:0]Q; + input [13:0]RD_PNTR_WR; + input [13:0]D; - wire [11:0]D; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; - wire [0:0]Q; - wire [11:0]RD_PNTR_WR; + wire [13:0]D; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ; + wire [0:0]E; + wire [13:0]Q; + wire [13:0]RD_PNTR_WR; + wire [0:0]WEA; wire c1_n_0; wire comp2; - wire [11:0]\gic0.gc0.count_d1_reg[11] ; - wire \gic0.gc0.count_d1_reg[12] ; - wire \gnxpm_cdc.rd_pntr_bin_reg[12] ; - wire \gnxpm_cdc.rd_pntr_bin_reg[12]_0 ; (* DONT_TOUCH *) wire ram_full_fb_i; (* DONT_TOUCH *) wire ram_full_i; wire wr_clk; @@ -8386,33 +11021,36 @@ module rx_packet_fifo_wr_status_flags_as \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0 (.I0(wr_en), .I1(ram_full_fb_i), - .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); - LUT3 #( - .INIT(8'h04)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1 - (.I0(ram_full_fb_i), - .I1(wr_en), - .I2(Q), .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram )); LUT2 #( .INIT(4'h2)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3 (.I0(wr_en), .I1(ram_full_fb_i), - .O(\gic0.gc0.count_d1_reg[12] )); + .O(WEA)); + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3__0 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 )); rx_packet_fifo_compare c1 - (.RD_PNTR_WR(RD_PNTR_WR), + (.Q(Q), + .RD_PNTR_WR(RD_PNTR_WR), .comp2(comp2), - .\gic0.gc0.count_d1_reg[11] (\gic0.gc0.count_d1_reg[11] ), - .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12] ), .out(ram_full_fb_i), .ram_full_i_reg(c1_n_0), .wr_en(wr_en)); - rx_packet_fifo_compare_0 c2 + rx_packet_fifo_compare_1 c2 (.D(D), .RD_PNTR_WR(RD_PNTR_WR), - .comp2(comp2), - .\gnxpm_cdc.rd_pntr_bin_reg[12] (\gnxpm_cdc.rd_pntr_bin_reg[12]_0 )); + .comp2(comp2)); + LUT2 #( + .INIT(4'h2)) + \gic0.gc0.count_d1[13]_i_1 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(E)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_stub.v b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_stub.v index 8492c36..d137824 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_stub.v +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016 -// Date : Mon Jan 16 15:31:50 2017 +// Date : Sat Apr 15 09:39:28 2017 // Host : david-desktop-arch running 64-bit unknown // Command : write_verilog -force -mode synth_stub // /home/dave/misc-projects/rftool-fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo_stub.v diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/sim/rx_packet_fifo.v b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/sim/rx_packet_fifo.v index 6df7230..66b386d 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/sim/rx_packet_fifo.v +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/sim/rx_packet_fifo.v @@ -87,7 +87,7 @@ output wire prog_empty; .C_COMMON_CLOCK(0), .C_SELECT_XPM(0), .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(13), + .C_DATA_COUNT_WIDTH(14), .C_DEFAULT_VALUE("BlankString"), .C_DIN_WIDTH(32), .C_DOUT_RST_VAL("0"), @@ -123,13 +123,13 @@ output wire prog_empty; .C_PROG_EMPTY_THRESH_ASSERT_VAL(1023), .C_PROG_EMPTY_THRESH_NEGATE_VAL(1024), .C_PROG_EMPTY_TYPE(1), - .C_PROG_FULL_THRESH_ASSERT_VAL(8189), - .C_PROG_FULL_THRESH_NEGATE_VAL(8188), + .C_PROG_FULL_THRESH_ASSERT_VAL(16381), + .C_PROG_FULL_THRESH_NEGATE_VAL(16380), .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(13), - .C_RD_DEPTH(8192), + .C_RD_DATA_COUNT_WIDTH(14), + .C_RD_DEPTH(16384), .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(13), + .C_RD_PNTR_WIDTH(14), .C_UNDERFLOW_LOW(0), .C_USE_DOUT_RST(0), .C_USE_ECC(0), @@ -140,10 +140,10 @@ output wire prog_empty; .C_USE_FWFT_DATA_COUNT(0), .C_VALID_LOW(0), .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(13), - .C_WR_DEPTH(8192), + .C_WR_DATA_COUNT_WIDTH(14), + .C_WR_DEPTH(16384), .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(13), + .C_WR_PNTR_WIDTH(14), .C_WR_RESPONSE_LATENCY(1), .C_MSGON_VAL(1), .C_ENABLE_RST_SYNC(1), @@ -299,12 +299,12 @@ output wire prog_empty; .din(din), .wr_en(wr_en), .rd_en(rd_en), - .prog_empty_thresh(13'B0), - .prog_empty_thresh_assert(13'B0), - .prog_empty_thresh_negate(13'B0), - .prog_full_thresh(13'B0), - .prog_full_thresh_assert(13'B0), - .prog_full_thresh_negate(13'B0), + .prog_empty_thresh(14'B0), + .prog_empty_thresh_assert(14'B0), + .prog_empty_thresh_negate(14'B0), + .prog_full_thresh(14'B0), + .prog_full_thresh_assert(14'B0), + .prog_full_thresh_negate(14'B0), .int_clk(1'D0), .injectdbiterr(1'D0), .injectsbiterr(1'D0), diff --git a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/synth/rx_packet_fifo.vhd b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/synth/rx_packet_fifo.vhd index ce13f71..f8e347a 100644 --- a/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/synth/rx_packet_fifo.vhd +++ b/fpga/projects/rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/synth/rx_packet_fifo.vhd @@ -291,12 +291,12 @@ ARCHITECTURE rx_packet_fifo_arch OF rx_packet_fifo IS din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; - prog_empty_thresh : IN STD_LOGIC_VECTOR(12 DOWNTO 0); - prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(12 DOWNTO 0); - prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(12 DOWNTO 0); - prog_full_thresh : IN STD_LOGIC_VECTOR(12 DOWNTO 0); - prog_full_thresh_assert : IN STD_LOGIC_VECTOR(12 DOWNTO 0); - prog_full_thresh_negate : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + prog_empty_thresh : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + prog_full_thresh : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + prog_full_thresh_assert : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + prog_full_thresh_negate : IN STD_LOGIC_VECTOR(13 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; @@ -310,9 +310,9 @@ ARCHITECTURE rx_packet_fifo_arch OF rx_packet_fifo IS almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; - data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); - rd_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); - wr_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + data_count : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + rd_data_count : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + wr_data_count : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; @@ -517,16 +517,16 @@ ARCHITECTURE rx_packet_fifo_arch OF rx_packet_fifo IS ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF rx_packet_fifo_arch : ARCHITECTURE IS "rx_packet_fifo,fifo_generator_v13_1_2,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; - ATTRIBUTE CORE_GENERATION_INFO OF rx_packet_fifo_arch: ARCHITECTURE IS "rx_packet_fifo,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=13,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" & -"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=8kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=1023,C_PROG_EMPTY_THRESH_NEGATE_VAL=1024,C_PROG_EMPTY_TYPE=1,C_PROG_FULL_THRESH_ASSERT_VAL=8189,C_PROG_F" & -"ULL_THRESH_NEGATE_VAL=8188,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=13,C_RD_DEPTH=8192,C_RD_FREQ=1,C_RD_PNTR_WIDTH=13,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=13,C_WR_DEPTH=8192,C_WR_FREQ=1,C_WR_PNTR_WIDTH=13,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C" & -"_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RU" & -"SER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTAT" & -"ION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WAC" & -"H=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_" & -"RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_" & -"WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRE" & -"SH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; + ATTRIBUTE CORE_GENERATION_INFO OF rx_packet_fifo_arch: ARCHITECTURE IS "rx_packet_fifo,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=14,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" & +"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=8kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=1023,C_PROG_EMPTY_THRESH_NEGATE_VAL=1024,C_PROG_EMPTY_TYPE=1,C_PROG_FULL_THRESH_ASSERT_VAL=16381,C_PROG_" & +"FULL_THRESH_NEGATE_VAL=16380,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=14,C_RD_DEPTH=16384,C_RD_FREQ=1,C_RD_PNTR_WIDTH=14,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=14,C_WR_DEPTH=16384,C_WR_FREQ=1,C_WR_PNTR_WIDTH=14,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE" & +"=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AX" & +"I_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEME" & +"NTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE" & +"_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WI" & +"DTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_" & +"VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_" & +"THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK"; @@ -542,7 +542,7 @@ BEGIN C_COMMON_CLOCK => 0, C_SELECT_XPM => 0, C_COUNT_TYPE => 0, - C_DATA_COUNT_WIDTH => 13, + C_DATA_COUNT_WIDTH => 14, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 32, C_DOUT_RST_VAL => "0", @@ -578,13 +578,13 @@ BEGIN C_PROG_EMPTY_THRESH_ASSERT_VAL => 1023, C_PROG_EMPTY_THRESH_NEGATE_VAL => 1024, C_PROG_EMPTY_TYPE => 1, - C_PROG_FULL_THRESH_ASSERT_VAL => 8189, - C_PROG_FULL_THRESH_NEGATE_VAL => 8188, + C_PROG_FULL_THRESH_ASSERT_VAL => 16381, + C_PROG_FULL_THRESH_NEGATE_VAL => 16380, C_PROG_FULL_TYPE => 0, - C_RD_DATA_COUNT_WIDTH => 13, - C_RD_DEPTH => 8192, + C_RD_DATA_COUNT_WIDTH => 14, + C_RD_DEPTH => 16384, C_RD_FREQ => 1, - C_RD_PNTR_WIDTH => 13, + C_RD_PNTR_WIDTH => 14, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 0, C_USE_ECC => 0, @@ -595,10 +595,10 @@ BEGIN C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, - C_WR_DATA_COUNT_WIDTH => 13, - C_WR_DEPTH => 8192, + C_WR_DATA_COUNT_WIDTH => 14, + C_WR_DEPTH => 16384, C_WR_FREQ => 1, - C_WR_PNTR_WIDTH => 13, + C_WR_PNTR_WIDTH => 14, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, @@ -755,12 +755,12 @@ BEGIN din => din, wr_en => wr_en, rd_en => rd_en, - prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), - prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), - prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), - prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), - prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), - prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)), + prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), + prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), + prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), + prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), + prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), + prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', diff --git a/fpga/projects/rx_only/rx_only.xpr b/fpga/projects/rx_only/rx_only.xpr index 1734898..a29c353 100644 --- a/fpga/projects/rx_only/rx_only.xpr +++ b/fpga/projects/rx_only/rx_only.xpr @@ -36,13 +36,13 @@