xilinx.com ipcache 848330eae6fd4c94 0 rx_packet_fifo 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock rx_packet_fifo 64 false 14 false false 0 1023 1022 1022 1022 1022 1022 1022 1024 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Block_RAM 0 16381 1023 1023 1023 1023 1023 1023 16380 false false false 0 Native false false false false false false false false false false false false false false 32 16384 1024 16 1024 16 1024 16 false 32 16384 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO Single_Programmable_Empty_Threshold_Constant No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 false 14 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered false Asynchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High false false false false false Active_High 0 false Active_High 1 false 14 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO artix7 xc7a50t ftg256 VHDL MIXED -2 TRUE TRUE f9fab666 848330eae6fd4c94 IP_Unknown 2 TRUE . . 2016.3 GLOBAL