564 lines
16 KiB
C
564 lines
16 KiB
C
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/***************************************************************************//**
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* @file ad9361_conv.c
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* @brief Implementation of AD9361 Conv Driver.
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********************************************************************************
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* Copyright 2014-2015(c) Analog Devices, Inc.
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Analog Devices, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* - The use of this software may or may not infringe the patent rights
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* of one or more patent holders. This license does not release you
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* from the requirement that you obtain separate licenses from these
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* patent holders to use this software.
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* - Use of the software either in source or binary form, must be run
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* on or directly connected to an Analog Devices Inc. component.
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*
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* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/******************************************************************************/
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/***************************** Include Files **********************************/
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/******************************************************************************/
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#include <inttypes.h>
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#include <string.h>
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#include "ad9361.h"
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#include "platform.h"
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#ifndef AXI_ADC_NOT_PRESENT
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/**
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* HDL loopback enable/disable.
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* @param phy The AD9361 state structure.
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* @param enable Enable/disable option.
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* @return 0 in case of success, negative error code otherwise.
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*/
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int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
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{
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struct axiadc_converter *conv = phy->adc_conv;
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struct axiadc_state *st = phy->adc_state;
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int32_t reg, addr, chan;
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uint32_t version = axiadc_read(st, 0x4000);
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/* Still there but implemented a bit different */
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if (PCORE_VERSION_MAJOR(version) > 7)
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addr = 0x4418;
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else
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addr = 0x4414;
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for (chan = 0; chan < conv->chip_info->num_channels; chan++) {
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reg = axiadc_read(st, addr + (chan) * 0x40);
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if (PCORE_VERSION_MAJOR(version) > 7) {
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if (enable && reg != 0x8) {
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conv->scratch_reg[chan] = reg;
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reg = 0x8;
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} else if (reg == 0x8) {
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reg = conv->scratch_reg[chan];
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}
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} else {
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/* DAC_LB_ENB If set enables loopback of receive data */
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if (enable)
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reg |= BIT(1);
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else
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reg &= ~BIT(1);
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}
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axiadc_write(st, addr + (chan) * 0x40, reg);
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}
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return 0;
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}
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/**
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* Set IO delay.
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* @param st The AXI ADC state structure.
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* @param lane Lane number.
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* @param val Value.
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* @param tx The Synthesizer TX = 1, RX = 0.
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* @return 0 in case of success, negative error code otherwise.
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*/
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static int32_t ad9361_iodelay_set(struct axiadc_state *st, unsigned lane,
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unsigned val, bool tx)
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{
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if (tx) {
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if (PCORE_VERSION_MAJOR(st->pcore_version) > 8)
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axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val);
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else
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return -ENODEV;
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} else {
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axiadc_idelay_set(st, lane, val);
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}
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return 0;
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}
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/**
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* Set midscale IO delay.
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* @param phy The AD9361 state structure.
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* @param tx The Synthesizer TX = 1, RX = 0.
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* @return 0 in case of success, negative error code otherwise.
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*/
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static int32_t ad9361_midscale_iodelay(struct ad9361_rf_phy *phy, bool tx)
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{
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struct axiadc_state *st = phy->adc_state;
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int32_t ret = 0, i;
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for (i = 0; i < 7; i++)
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ret |= ad9361_iodelay_set(st, i, 15, tx);
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return 0;
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}
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/**
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* Digital tune IO delay.
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* @param phy The AD9361 state structure.
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* @param tx The Synthesizer TX = 1, RX = 0.
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* @return 0 in case of success, negative error code otherwise.
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*/
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static int32_t ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx)
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{
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struct axiadc_converter *conv = phy->adc_conv;
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struct axiadc_state *st = phy->adc_state;
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int32_t ret, i, j, chan, num_chan;
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uint32_t s0, c0;
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uint8_t field[32];
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num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels;
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for (i = 0; i < 7; i++) {
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for (j = 0; j < 32; j++) {
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ad9361_iodelay_set(st, i, j, tx);
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mdelay(1);
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for (chan = 0; chan < num_chan; chan++)
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axiadc_write(st, ADI_REG_CHAN_STATUS(chan),
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ADI_PN_ERR | ADI_PN_OOS);
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mdelay(10);
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for (chan = 0, ret = 0; chan < num_chan; chan++)
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ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan));
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field[j] = ret;
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}
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c0 = ad9361_find_opt(&field[0], 32, &s0);
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ad9361_iodelay_set(st, i, s0 + c0 / 2, tx);
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dev_dbg(&phy->spi->dev,
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"%s Lane %"PRId32", window cnt %"PRIu32" , start %"PRIu32", IODELAY set to %"PRIu32"\n",
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tx ? "TX" :"RX", i , c0, s0, s0 + c0 / 2);
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}
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return 0;
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}
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/**
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* Digital tune verbose print.
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* @param phy The AD9361 state structure.
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* @param field Field.
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* @param tx The Synthesizer TX = 1, RX = 0.
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* @return 0 in case of success, negative error code otherwise.
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*/
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static void ad9361_dig_tune_verbose_print(struct ad9361_rf_phy *phy,
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uint8_t field[][16], bool tx)
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{
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int32_t i, j;
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printk("SAMPL CLK: %"PRIu32" tuning: %s\n",
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clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK]), tx ? "TX" : "RX");
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printk(" ");
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for (i = 0; i < 16; i++)
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printk("%"PRIx32":", i);
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printk("\n");
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for (i = 0; i < 2; i++) {
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printk("%"PRIx32":", i);
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for (j = 0; j < 16; j++) {
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printk("%c ", (field[i][j] ? '#' : 'o'));
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}
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printk("\n");
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}
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printk("\n");
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}
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/**
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* Digital interface timing analysis.
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* @param phy The AD9361 state structure.
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* @param buf The buffer.
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* @param buflen The buffer length.
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* @return The size in case of success, negative error code otherwise.
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*/
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int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
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char *buf, int32_t buflen)
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{
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struct axiadc_state *st = phy->adc_state;
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int32_t ret, i, j, chan, len = 0;
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uint8_t field[16][16];
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uint8_t rx;
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dev_dbg(&phy->spi->dev, "%s:\n", __func__);
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rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);
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ad9361_bist_prbs(phy, BIST_INJ_RX);
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for (i = 0; i < 16; i++) {
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for (j = 0; j < 16; j++) {
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ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY,
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DATA_CLK_DELAY(j) | RX_DATA_DELAY(i));
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for (chan = 0; chan < 4; chan++)
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axiadc_write(st, ADI_REG_CHAN_STATUS(chan),
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ADI_PN_ERR | ADI_PN_OOS);
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mdelay(1);
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if (axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS) {
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for (chan = 0, ret = 0; chan < 4; chan++)
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ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan));
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}
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else {
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ret = 1;
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}
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field[i][j] = ret;
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}
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}
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ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx);
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ad9361_bist_prbs(phy, BIST_DISABLE);
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len += snprintf(buf + len, buflen, "CLK: %"PRIu32" Hz 'o' = PASS\n",
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clk_get_rate(phy, phy->ref_clk_scale[RX_SAMPL_CLK]));
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len += snprintf(buf + len, buflen, "DC");
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for (i = 0; i < 16; i++)
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len += snprintf(buf + len, buflen, "%"PRIx32":", i);
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len += snprintf(buf + len, buflen, "\n");
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for (i = 0; i < 16; i++) {
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len += snprintf(buf + len, buflen, "%"PRIx32":", i);
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for (j = 0; j < 16; j++) {
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len += snprintf(buf + len, buflen, "%c ",
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(field[i][j] ? '.' : 'o'));
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}
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len += snprintf(buf + len, buflen, "\n");
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}
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len += snprintf(buf + len, buflen, "\n");
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return len;
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}
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/**
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* Digital tune.
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* @param phy The AD9361 state structure.
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* @param max_freq Maximum frequency.
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* @param flags Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY.
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* @return 0 in case of success, negative error code otherwise.
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*/
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int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq,
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enum dig_tune_flags flags)
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{
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struct axiadc_converter *conv = phy->adc_conv;
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struct axiadc_state *st = phy->adc_state;
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int32_t ret, i, j, k, chan, t, num_chan, err = 0;
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uint32_t s0, s1, c0, c1, tmp, saved = 0;
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uint8_t field[2][16];
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uint32_t rates[3] = {25000000U, 40000000U, 61440000U};
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uint32_t hdl_dac_version;
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dev_dbg(&phy->spi->dev, "%s: freq %u flags 0x%X\n", __func__,
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max_freq, flags);
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hdl_dac_version = axiadc_read(st, 0x4000);
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if ((phy->pdata->dig_interface_tune_skipmode == 2) ||
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(flags & RESTORE_DEFAULT)) {
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/* skip completely and use defaults */
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ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY,
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phy->pdata->port_ctrl.rx_clk_data_delay);
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ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY,
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phy->pdata->port_ctrl.tx_clk_data_delay);
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return 0;
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}
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if (flags & DO_IDELAY)
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ad9361_midscale_iodelay(phy, 0);
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if (flags & DO_ODELAY)
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ad9361_midscale_iodelay(phy, 1);
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if (!phy->pdata->fdd) {
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ad9361_set_ensm_mode(phy, true, false);
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ad9361_ensm_force_state(phy, ENSM_STATE_FDD);
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} else {
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ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
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ad9361_ensm_restore_prev_state(phy);
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}
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num_chan = (conv->chip_info->num_channels > 4) ? 4 :
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conv->chip_info->num_channels;
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ad9361_bist_prbs(phy, BIST_INJ_RX);
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for (t = 0; t < 2; t++) {
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memset(field, 0, 32);
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for (k = 0; (uint32_t)k < (max_freq ? ARRAY_SIZE(rates) : 1); k++) {
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if (max_freq)
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ad9361_set_trx_clock_chain_freq(phy, rates[k]);
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for (i = 0; i < 2; i++) {
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for (j = 0; j < 16; j++) {
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ad9361_spi_write(phy->spi,
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REG_RX_CLOCK_DATA_DELAY + t,
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RX_DATA_DELAY(i == 0 ? j : 0) |
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DATA_CLK_DELAY(i ? j : 0));
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for (chan = 0; chan < num_chan; chan++)
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axiadc_write(st, ADI_REG_CHAN_STATUS(chan),
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ADI_PN_ERR | ADI_PN_OOS);
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mdelay(4);
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if ((t == 1) || (axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS)) {
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for (chan = 0, ret = 0; chan < num_chan; chan++) {
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ret |= axiadc_read(st, ADI_REG_CHAN_STATUS(chan));
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}
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}
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else {
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ret = 1;
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}
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field[i][j] |= ret;
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}
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}
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if ((flags & BE_MOREVERBOSE) && max_freq) {
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ad9361_dig_tune_verbose_print(phy, field, t);
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}
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}
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c0 = ad9361_find_opt(&field[0][0], 16, &s0);
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c1 = ad9361_find_opt(&field[1][0], 16, &s1);
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if (!c0 && !c1) {
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ad9361_dig_tune_verbose_print(phy, field, t);
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dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__,
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t ? "TX" : "RX");
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err |= -EIO;
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} else if (flags & BE_VERBOSE) {
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ad9361_dig_tune_verbose_print(phy, field, t);
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}
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if (c1 > c0)
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ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY + t,
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DATA_CLK_DELAY(s1 + c1 / 2) |
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RX_DATA_DELAY(0));
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else
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ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY + t,
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DATA_CLK_DELAY(0) |
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RX_DATA_DELAY(s0 + c0 / 2));
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if (t == 0) {
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if (flags & DO_IDELAY)
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ad9361_dig_tune_iodelay(phy, 0);
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/* Now do the loopback and tune the digital out */
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ad9361_bist_prbs(phy, BIST_DISABLE);
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axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
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axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
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if (phy->pdata->dig_interface_tune_skipmode == 1) {
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/* skip TX */
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if (!(flags & SKIP_STORE_RESULT))
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phy->pdata->port_ctrl.rx_clk_data_delay =
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ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);
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if (!phy->pdata->fdd) {
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ad9361_set_ensm_mode(phy, phy->pdata->fdd,
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phy->pdata->ensm_pin_ctrl);
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ad9361_ensm_restore_prev_state(phy);
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}
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return 0;
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}
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ad9361_bist_loopback(phy, 1);
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axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
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for (chan = 0; chan < num_chan; chan++) {
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axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
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ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
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ADI_ENABLE | ADI_IQCOR_ENB);
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axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM);
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if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7)
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{
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axiadc_write(st, 0x4418 + (chan) * 0x40, 9);
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axiadc_write(st, 0x4044, 0x1);
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}
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else
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axiadc_write(st, 0x4414 + (chan) * 0x40, 1);
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}
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if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8) {
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saved = tmp = axiadc_read(st, 0x4048);
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tmp &= ~0xF;
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tmp |= 1;
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axiadc_write(st, 0x4048, tmp);
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}
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} else {
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if (flags & DO_ODELAY)
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ad9361_dig_tune_iodelay(phy, 1);
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ad9361_bist_loopback(phy, 0);
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if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8)
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axiadc_write(st, 0x4048, saved);
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for (chan = 0; chan < num_chan; chan++) {
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axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
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ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
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ADI_ENABLE | ADI_IQCOR_ENB);
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axiadc_set_pnsel(st, chan, ADC_PN9);
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if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7)
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{
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axiadc_write(st, 0x4418 + (chan) * 0x40, 0);
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axiadc_write(st, 0x4044, 0x1);
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}
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else
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axiadc_write(st, 0x4414 + (chan) * 0x40, 0);
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}
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if (err == -EIO) {
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ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY,
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phy->pdata->port_ctrl.rx_clk_data_delay);
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ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY,
|
|
phy->pdata->port_ctrl.tx_clk_data_delay);
|
|
if (!max_freq)
|
|
err = 0;
|
|
} else if (!(flags & SKIP_STORE_RESULT)) {
|
|
phy->pdata->port_ctrl.rx_clk_data_delay =
|
|
ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);
|
|
phy->pdata->port_ctrl.tx_clk_data_delay =
|
|
ad9361_spi_read(phy->spi, REG_TX_CLOCK_DATA_DELAY);
|
|
}
|
|
|
|
if (!phy->pdata->fdd) {
|
|
ad9361_set_ensm_mode(phy, phy->pdata->fdd, phy->pdata->ensm_pin_ctrl);
|
|
ad9361_ensm_restore_prev_state(phy);
|
|
}
|
|
|
|
axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
|
|
axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
|
|
|
|
return err;
|
|
}
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/**
|
|
* Setup the AD9361 device.
|
|
* @param phy The AD9361 state structure.
|
|
* @return 0 in case of success, negative error code otherwise.
|
|
*/
|
|
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
|
|
{
|
|
struct axiadc_converter *conv = phy->adc_conv;
|
|
struct axiadc_state *st = phy->adc_state;
|
|
int32_t rx2tx2 = phy->pdata->rx2tx2;
|
|
int32_t tmp, num_chan, flags;
|
|
int32_t i, ret;
|
|
|
|
num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels;
|
|
|
|
axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE);
|
|
tmp = axiadc_read(st, 0x4048);
|
|
|
|
if (!rx2tx2) {
|
|
axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */
|
|
axiadc_write(st, 0x404c, 1); /* RATE */
|
|
}
|
|
else {
|
|
tmp &= ~BIT(5);
|
|
axiadc_write(st, 0x4048, tmp);
|
|
axiadc_write(st, 0x404c, 3); /* RATE */
|
|
}
|
|
|
|
for (i = 0; i < num_chan; i++) {
|
|
axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i),
|
|
ADI_DCFILT_OFFSET(0));
|
|
axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i),
|
|
(i & 1) ? 0x00004000 : 0x40000000);
|
|
axiadc_write(st, ADI_REG_CHAN_CNTRL(i),
|
|
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
|
|
ADI_ENABLE | ADI_IQCOR_ENB);
|
|
}
|
|
|
|
flags = 0x0;
|
|
|
|
ret = ad9361_dig_tune(phy, ((conv->chip_info->num_channels > 4) ||
|
|
axiadc_read(st, 0x0004)) ? 0 : 61440000, flags);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (flags & (DO_IDELAY | DO_ODELAY)) {
|
|
ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ?
|
|
0 : 61440000, flags & BE_VERBOSE);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
ret = ad9361_set_trx_clock_chain(phy,
|
|
phy->pdata->rx_path_clks,
|
|
phy->pdata->tx_path_clks);
|
|
|
|
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
|
|
ad9361_ensm_restore_prev_state(phy);
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
/**
|
|
* HDL loopback enable/disable.
|
|
* @param phy The AD9361 state structure.
|
|
* @param enable Enable/disable option.
|
|
* @return 0 in case of success, negative error code otherwise.
|
|
*/
|
|
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
/**
|
|
* Setup the AD9361 device.
|
|
* @param phy The AD9361 state structure.
|
|
* @return 0 in case of success, negative error code otherwise.
|
|
*/
|
|
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|