54 lines
1.6 KiB
VHDL
54 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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--RX I/Q data packetiser
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--Copyright (C) 2016 David Shah
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--Licensed under the MIT License
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entity rx_packet_gen is
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port(
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clock : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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--IQ samples FIFO interface
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iq_fifo_q : in std_logic_vector(23 downto 0);
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iq_fifo_empty : in std_logic;
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iq_fifo_rden : out std_logic;
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--Rx packet FIFO interface
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packet_fifo_d : out std_logic_vector(31 downto 0);
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packet_fifo_wren : out std_logic;
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packet_fifo_full : in std_logic;
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--System signals
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streaming_mode : in std_logic
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);
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end rx_packet_gen;
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architecture Behavioral of rx_packet_gen is
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constant packet_len : natural := 256; --packet length in words
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constant samples_per_packet : natural := 255; --number of samples in each packet
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constant rx_packet_magic : std_logic_vector(31 downto 0) := x"51495852"; --"RXIQ" (little endian) in ASCII
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signal packet_word_count : natural range 0 to packet_len - 1 := 0;
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signal in_packet : std_logic := '0';
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signal fifo_empty_last : std_logic;
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begin
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iq_fifo_rden <= not iq_fifo_empty;
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packet_fifo_wren <= (not fifo_empty_last) and (not packet_fifo_full);
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--Use a simple encoding that ensures alignment can always be determined
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--This is not very efficient and a packet based approach with a header would be much better
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packet_fifo_d <= "11" & iq_fifo_q(23 downto 18) & "10" & iq_fifo_q(17 downto 12) & "01" & iq_fifo_q(11 downto 6) & "00" & iq_fifo_q(5 downto 0);
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process(clock)
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begin
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if rising_edge(clock) then
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fifo_empty_last <= iq_fifo_empty;
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end if;
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end process;
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end Behavioral;
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