83 lines
1.8 KiB
VHDL
83 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use STD.textio.ALL;
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entity wn_testbench is
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end wn_testbench;
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architecture Behavioral of wn_testbench is
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signal clock : std_logic := '0';
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signal i_val, q_val : std_logic_vector(11 downto 0);
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file outfile : text;
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begin
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i_gen : entity work.whitenoise_gen
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generic map(
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int_width => 32,
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ext_width => 12,
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num_lfsrs => 20,
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lfsr_poly => x"80000057")
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port map(
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clock => clock,
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reset => '0',
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enable => '1',
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data => i_val);
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q_gen : entity work.whitenoise_gen
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generic map(
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int_width => 32,
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ext_width => 12,
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num_lfsrs => 20,
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lfsr_poly => x"80000EA6")
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port map(
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clock => clock,
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reset => '0',
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enable => '1',
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data => q_val);
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-- q_gen : entity work.galois_lfsr
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-- generic map(
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-- size => 12,
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-- polynomial => x"829",
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-- init => x"001")
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-- port map(
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-- clock => clock,
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-- reset => '0',
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-- enable => '1',
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-- data => q_val);
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process
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variable i_tmp, q_tmp : integer;
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variable oline : line;
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begin
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file_open(outfile, "output.csv", write_mode);
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write(oline, string'("t, i, q,"));
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writeline(outfile, oline);
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for i in 1 to 65536 loop
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wait for 10 ns;
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clock <= '1';
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wait for 10 ns;
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clock <= '0';
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i_tmp := to_integer(signed(i_val));
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q_tmp := to_integer(signed(q_val));
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write(oline, (now / 1 ns), left, 4);
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write(oline, string'(", "));
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write(oline, i_tmp, left, 5);
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write(oline, string'(", "));
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write(oline, q_tmp, left, 5);
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write(oline, string'(", "));
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writeline(outfile, oline);
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end loop;
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file_close(outfile);
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wait;
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end process;
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end Behavioral;
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