51 lines
1.5 KiB
VHDL
51 lines
1.5 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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--Direct Digital Synthesis Core
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--Copyright (C) 2017 David Shah
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--Licensed under the MIT License
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entity dds_core is
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generic (
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N : natural := 24; --frequency word size
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M : natural := 12 --phase out size (M <= N)
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);
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port (
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clock : in std_logic; --control and synthesis clock
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reset : in std_logic; --sync reset
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enable : in std_logic;
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freq_val : in std_logic_vector(N-1 downto 0); --frequency setting word
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phase_val : in std_logic_vector(N-1 downto 0); --phase setting word
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phase_load : in std_logic; --update phase
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phase_out : out std_logic_vector(M-1 downto 0) --phase output
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);
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end dds_core;
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architecture Behavioral of dds_core is
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signal freq_reg : unsigned(N-1 downto 0) := (others => '0');
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signal phase_acc : unsigned(N-1 downto 0) := (others => '0');
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signal phase_out_reg : std_logic_vector(M-1 downto 0) := (others => '0');
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begin
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process(clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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freq_reg <= (others => '0');
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phase_acc <= (others => '0');
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phase_out_reg <= (others => '0');
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elsif enable = '1' then
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freq_reg <= unsigned(freq_val);
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if phase_load = '1' then
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phase_acc <= unsigned(phase_val);
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else
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phase_acc <= phase_acc + freq_reg;
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end if;
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phase_out_reg <= std_logic_vector(phase_acc(N-1 downto (N-M)));
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end if;
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end if;
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end process;
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phase_out <= phase_out_reg;
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end Behavioral;
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