572 lines
27 KiB
XML
572 lines
27 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<!-- Product Version: Vivado v2016.3 (64-bit) -->
|
|
<!-- -->
|
|
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
|
|
|
|
<Project Version="7" Minor="17" Path="/home/dave/misc-projects/rftool-fpga/projects/rx_tx_gen/rx_tx_gen.xpr">
|
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
<Configuration>
|
|
<Option Name="Id" Val="bfbef9a704614193a7f7360e74a577b4"/>
|
|
<Option Name="Part" Val="xc7a50tftg256-2"/>
|
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
<Option Name="TargetLanguage" Val="VHDL"/>
|
|
<Option Name="BoardPart" Val=""/>
|
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
<Option Name="IPCachePermission" Val="read"/>
|
|
<Option Name="IPCachePermission" Val="write"/>
|
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
<Option Name="IPUserFilesDir" Val="$PPRDIR/rx_tx_gen.ip_user_files"/>
|
|
<Option Name="IPStaticSourceDir" Val="$PPRDIR/rx_tx_gen.ip_user_files/ipstatic"/>
|
|
<Option Name="EnableBDX" Val="FALSE"/>
|
|
<Option Name="DSANumComputeUnits" Val="16"/>
|
|
<Option Name="WTXSimLaunchSim" Val="4"/>
|
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
<Option Name="WTXSimExportSim" Val="16"/>
|
|
<Option Name="WTModelSimExportSim" Val="16"/>
|
|
<Option Name="WTQuestaExportSim" Val="16"/>
|
|
<Option Name="WTIesExportSim" Val="16"/>
|
|
<Option Name="WTVcsExportSim" Val="16"/>
|
|
<Option Name="WTRivieraExportSim" Val="16"/>
|
|
<Option Name="WTActivehdlExportSim" Val="16"/>
|
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
<Option Name="XSimRadix" Val="hex"/>
|
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
<Option Name="XSimArrayDisplayLimit" Val="64"/>
|
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
</Configuration>
|
|
<FileSets Version="1" Minor="31">
|
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
|
<Filter Type="Srcs"/>
|
|
<File Path="$PPRDIR/../../whitenoise/galois-lfsr.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../dds/dds-sine-table.gen.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../dds/dds-core.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../whitenoise/whitenoise-gen.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../dds/dds-iq-sine-gen.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../ad9361/ad9361_bidir_if.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../pc/rx_packet_gen.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../pc/pc_control_handler.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../pc/ft60x_fifo_if.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../ad9361/ad9361_spi_if.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../siggen/siggen-top.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PSRCDIR/sources_1/new/rx_tx_gen_top.vhd">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../ad9361/ad9361_rx_if.vhd">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../whitenoise/whitenoise-testbench.vhd">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../../dds/dds-testbench.vhd">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="rx_tx_gen_top"/>
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
|
<Filter Type="Constrs"/>
|
|
<File Path="$PSRCDIR/constrs_1/new/rftool_rev1.xdc">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/constrs_1/new/rftool_rev1.xdc"/>
|
|
<Attr Name="ImportTime" Val="1482407418"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/rftool_rev1.xdc"/>
|
|
<Option Name="ConstrsType" Val="XDC"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
|
<Filter Type="Srcs"/>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="ad9361_sdr_bidir_if"/>
|
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
<Option Name="TransportPathDelay" Val="0"/>
|
|
<Option Name="TransportIntDelay" Val="0"/>
|
|
<Option Name="SrcSet" Val="sources_1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="command_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/command_fifo">
|
|
<File Path="$PSRCDIR/sources_1/ip/command_fifo/command_fifo.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/command_fifo/command_fifo.xci"/>
|
|
<Attr Name="ImportTime" Val="1481549884"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="command_fifo"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="response_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/response_fifo">
|
|
<File Path="$PSRCDIR/sources_1/ip/response_fifo/response_fifo.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/response_fifo/response_fifo.xci"/>
|
|
<Attr Name="ImportTime" Val="1481549899"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="response_fifo"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="rx_packet_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rx_packet_fifo">
|
|
<File Path="$PSRCDIR/sources_1/ip/rx_packet_fifo/rx_packet_fifo.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/rx_packet_fifo/rx_packet_fifo.xci"/>
|
|
<Attr Name="ImportTime" Val="1492245500"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="rx_packet_fifo"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="iq_sample_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/iq_sample_fifo">
|
|
<File Path="$PSRCDIR/sources_1/ip/iq_sample_fifo/iq_sample_fifo.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/iq_sample_fifo/iq_sample_fifo.xci"/>
|
|
<Attr Name="ImportTime" Val="1492246134"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="iq_sample_fifo"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="sys_pll" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sys_pll">
|
|
<File Path="$PSRCDIR/sources_1/ip/sys_pll/sys_pll.xci">
|
|
<FileInfo>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/sys_pll/sys_pll.xci"/>
|
|
<Attr Name="ImportTime" Val="1481551213"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="sys_pll"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_0">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_0/ila_0.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/ila_0/ila_0.xci"/>
|
|
<Attr Name="ImportTime" Val="1482163225"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_0"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_1">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_1/ila_1.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/ila_1/ila_1.xci"/>
|
|
<Attr Name="ImportTime" Val="1482170500"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_1"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="ila_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_2">
|
|
<File Path="$PSRCDIR/sources_1/ip/ila_2/ila_2.xci">
|
|
<FileInfo>
|
|
<Attr Name="AutoDisabled" Val="1"/>
|
|
<Attr Name="ImportPath" Val="$PPRDIR/../rx_only/rx_only.srcs/sources_1/ip/ila_2/ila_2.xci"/>
|
|
<Attr Name="ImportTime" Val="1482411688"/>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="ila_2"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="sg_ila" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sg_ila">
|
|
<File Path="$PSRCDIR/sources_1/ip/sg_ila/sg_ila.xci">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="TopModule" Val="sg_ila"/>
|
|
<Option Name="UseBlackboxStub" Val="1"/>
|
|
</Config>
|
|
</FileSet>
|
|
</FileSets>
|
|
<Simulators>
|
|
<Simulator Name="XSim">
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
|
<Option Name="CompiledLib" Val="0"/>
|
|
</Simulator>
|
|
<Simulator Name="ModelSim">
|
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="Questa">
|
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="IES">
|
|
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
|
</Simulator>
|
|
<Simulator Name="VCS">
|
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
|
</Simulator>
|
|
<Simulator Name="Riviera">
|
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
</Simulator>
|
|
</Simulators>
|
|
<Runs Version="1" Minor="10">
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a50tftg256-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="command_fifo_synth_1" Type="Ft3:Synth" SrcSet="command_fifo" Part="xc7a50tftg256-2" ConstrsSet="command_fifo" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/command_fifo_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="response_fifo_synth_1" Type="Ft3:Synth" SrcSet="response_fifo" Part="xc7a50tftg256-2" ConstrsSet="response_fifo" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/response_fifo_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="rx_packet_fifo_synth_1" Type="Ft3:Synth" SrcSet="rx_packet_fifo" Part="xc7a50tftg256-2" ConstrsSet="rx_packet_fifo" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/rx_packet_fifo_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="iq_sample_fifo_synth_1" Type="Ft3:Synth" SrcSet="iq_sample_fifo" Part="xc7a50tftg256-2" ConstrsSet="iq_sample_fifo" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/iq_sample_fifo_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="sys_pll_synth_1" Type="Ft3:Synth" SrcSet="sys_pll" Part="xc7a50tftg256-2" ConstrsSet="sys_pll" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sys_pll_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="ila_0_synth_1" Type="Ft3:Synth" SrcSet="ila_0" Part="xc7a50tftg256-2" ConstrsSet="ila_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/ila_0_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="ila_1_synth_1" Type="Ft3:Synth" SrcSet="ila_1" Part="xc7a50tftg256-2" ConstrsSet="ila_1" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/ila_1_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="ila_2_synth_1" Type="Ft3:Synth" SrcSet="ila_2" Part="xc7a50tftg256-2" ConstrsSet="ila_2" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/ila_2_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="sg_ila_synth_1" Type="Ft3:Synth" SrcSet="sg_ila" Part="xc7a50tftg256-2" ConstrsSet="sg_ila" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sg_ila_synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="command_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="command_fifo" Description="Default settings for Implementation." SynthRun="command_fifo_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="response_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="response_fifo" Description="Default settings for Implementation." SynthRun="response_fifo_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="rx_packet_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="rx_packet_fifo" Description="Default settings for Implementation." SynthRun="rx_packet_fifo_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="iq_sample_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="iq_sample_fifo" Description="Default settings for Implementation." SynthRun="iq_sample_fifo_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="sys_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="sys_pll" Description="Default settings for Implementation." SynthRun="sys_pll_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="ila_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="ila_0" Description="Default settings for Implementation." SynthRun="ila_0_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="ila_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="ila_1" Description="Default settings for Implementation." SynthRun="ila_1_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="ila_2_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="ila_2" Description="Default settings for Implementation." SynthRun="ila_2_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
<Run Id="sg_ila_impl_1" Type="Ft2:EntireDesign" Part="xc7a50tftg256-2" ConstrsSet="sg_ila" Description="Default settings for Implementation." SynthRun="sg_ila_synth_1" IncludeInArchive="false">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
</Run>
|
|
</Runs>
|
|
</Project>
|