70 lines
1.6 KiB
VHDL
70 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use STD.textio.ALL;
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entity dds_testbench is
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end dds_testbench;
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architecture Behavioral of dds_testbench is
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signal clock : std_logic := '0';
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signal i_val, q_val : std_logic_vector(11 downto 0);
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signal frequency : std_logic_vector(23 downto 0);
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signal q_phase : std_logic_vector(11 downto 0);
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signal i_amp, q_amp : std_logic_vector(7 downto 0);
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file outfile : text;
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begin
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frequency <= x"051EB8"; --1MHz with a 50MHz clock
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q_phase <= x"400"; --90 degree offset
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i_amp <= x"FF";
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q_amp <= x"7F";
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gen : entity work.dds_iq_sine_gen
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port map(
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clock => clock,
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reset => '0',
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enable => '1',
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frequency => frequency,
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global_phase => x"000000",
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global_phase_load => '0',
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q_phase_offset => q_phase,
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i_amplitude => i_amp,
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q_amplitude => q_amp,
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i_out => i_val,
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q_out => q_val);
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process
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variable i_tmp, q_tmp : integer;
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variable oline : line;
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begin
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file_open(outfile, "output.csv", write_mode);
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write(oline, string'("t, i, q,"));
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writeline(outfile, oline);
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for i in 1 to 1000 loop
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wait for 10 ns;
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clock <= '1';
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wait for 10 ns;
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clock <= '0';
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i_tmp := to_integer(signed(i_val));
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q_tmp := to_integer(signed(q_val));
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write(oline, (now / 1 ns), left, 4);
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write(oline, string'(", "));
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write(oline, i_tmp, left, 5);
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write(oline, string'(", "));
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write(oline, q_tmp, left, 5);
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write(oline, string'(", "));
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writeline(outfile, oline);
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end loop;
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file_close(outfile);
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wait;
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end process;
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end Behavioral;
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