27 lines
1018 B
Batchfile
27 lines
1018 B
Batchfile
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@echo off
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REM ****************************************************************************
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REM Vivado (TM) v2022.2 (64-bit)
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REM
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REM Filename : compile.bat
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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for compiling the simulation design source files
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REM
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REM Generated by Vivado on Sun May 26 03:58:29 +0800 2024
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REM SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
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REM
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REM IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
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REM
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REM usage: compile.bat
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REM
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REM ****************************************************************************
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REM compile Verilog/System Verilog design sources
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echo "xvlog --incr --relax -L uvm -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xilinx_vip -prj test_axi_v1_0_tb_vlog.prj"
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call xvlog --incr --relax -L uvm -L axi_vip_v1_1_13 -L processing_system7_vip_v1_0_15 -L xilinx_vip -prj test_axi_v1_0_tb_vlog.prj -log xvlog.log
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call type xvlog.log > compile.log
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if "%errorlevel%"=="1" goto END
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if "%errorlevel%"=="0" goto SUCCESS
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:END
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exit 1
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:SUCCESS
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exit 0
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