first commit
This commit is contained in:
commit
f048762aaf
@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>00e4d26f5ccf6a4d</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="axi_pwm_v1_0_S00_AXI" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">00e4d26f5ccf6a4d</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">d3562aff</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">39</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,46 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Tue May 28 18:57:06 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v
|
||||
// Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_pwm_v1_0_S00_AXI,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pwm_out, pwn_reg, S_AXI_ACLK, S_AXI_ARESETN,
|
||||
S_AXI_AWADDR, S_AXI_AWPROT, S_AXI_AWVALID, S_AXI_AWREADY, S_AXI_WDATA, S_AXI_WSTRB,
|
||||
S_AXI_WVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_BREADY, S_AXI_ARADDR,
|
||||
S_AXI_ARPROT, S_AXI_ARVALID, S_AXI_ARREADY, S_AXI_RDATA, S_AXI_RRESP, S_AXI_RVALID,
|
||||
S_AXI_RREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="pwm_out,pwn_reg[31:0],S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY" */;
|
||||
output pwm_out;
|
||||
output [31:0]pwn_reg;
|
||||
input S_AXI_ACLK;
|
||||
input S_AXI_ARESETN;
|
||||
input [3:0]S_AXI_AWADDR;
|
||||
input [2:0]S_AXI_AWPROT;
|
||||
input S_AXI_AWVALID;
|
||||
output S_AXI_AWREADY;
|
||||
input [31:0]S_AXI_WDATA;
|
||||
input [3:0]S_AXI_WSTRB;
|
||||
input S_AXI_WVALID;
|
||||
output S_AXI_WREADY;
|
||||
output [1:0]S_AXI_BRESP;
|
||||
output S_AXI_BVALID;
|
||||
input S_AXI_BREADY;
|
||||
input [3:0]S_AXI_ARADDR;
|
||||
input [2:0]S_AXI_ARPROT;
|
||||
input S_AXI_ARVALID;
|
||||
output S_AXI_ARREADY;
|
||||
output [31:0]S_AXI_RDATA;
|
||||
output [1:0]S_AXI_RRESP;
|
||||
output S_AXI_RVALID;
|
||||
input S_AXI_RREADY;
|
||||
endmodule
|
||||
@ -0,0 +1,52 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Tue May 28 18:57:06 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.vhdl
|
||||
-- Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
pwm_out : out STD_LOGIC;
|
||||
pwn_reg : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ACLK : in STD_LOGIC;
|
||||
S_AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "pwm_out,pwn_reg[31:0],S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_pwm_v1_0_S00_AXI,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>0bca3b91ff74aab9</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="axi_pwm_v1_0_S00_AXI" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">0bca3b91ff74aab9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">420890dd</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">43</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,45 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Tue May 28 14:33:51 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v
|
||||
// Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_pwm_v1_0_S00_AXI,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pwm_out, S_AXI_ACLK, S_AXI_ARESETN,
|
||||
S_AXI_AWADDR, S_AXI_AWPROT, S_AXI_AWVALID, S_AXI_AWREADY, S_AXI_WDATA, S_AXI_WSTRB,
|
||||
S_AXI_WVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_BREADY, S_AXI_ARADDR,
|
||||
S_AXI_ARPROT, S_AXI_ARVALID, S_AXI_ARREADY, S_AXI_RDATA, S_AXI_RRESP, S_AXI_RVALID,
|
||||
S_AXI_RREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY" */;
|
||||
output pwm_out;
|
||||
input S_AXI_ACLK;
|
||||
input S_AXI_ARESETN;
|
||||
input [3:0]S_AXI_AWADDR;
|
||||
input [2:0]S_AXI_AWPROT;
|
||||
input S_AXI_AWVALID;
|
||||
output S_AXI_AWREADY;
|
||||
input [31:0]S_AXI_WDATA;
|
||||
input [3:0]S_AXI_WSTRB;
|
||||
input S_AXI_WVALID;
|
||||
output S_AXI_WREADY;
|
||||
output [1:0]S_AXI_BRESP;
|
||||
output S_AXI_BVALID;
|
||||
input S_AXI_BREADY;
|
||||
input [3:0]S_AXI_ARADDR;
|
||||
input [2:0]S_AXI_ARPROT;
|
||||
input S_AXI_ARVALID;
|
||||
output S_AXI_ARREADY;
|
||||
output [31:0]S_AXI_RDATA;
|
||||
output [1:0]S_AXI_RRESP;
|
||||
output S_AXI_RVALID;
|
||||
input S_AXI_RREADY;
|
||||
endmodule
|
||||
@ -0,0 +1,51 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Tue May 28 14:33:51 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.vhdl
|
||||
-- Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
pwm_out : out STD_LOGIC;
|
||||
S_AXI_ACLK : in STD_LOGIC;
|
||||
S_AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_pwm_v1_0_S00_AXI,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,39 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>1025926fe6ef61a0</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_vlg_design_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="vlg_design" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CNT_MAX">1000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CNT_MAX_PERCENT">200</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_vlg_design_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">1025926fe6ef61a0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">14fae0ee</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">86</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
@ -0,0 +1,301 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 19 10:05:44 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_sim_netlist.v
|
||||
// Design : design_1_vlg_design_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_vlg_design_0_0,vlg_design,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* X_CORE_INFO = "vlg_design,Vivado 2022.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(i_clk,
|
||||
i_rst_n,
|
||||
i_en,
|
||||
o_vld,
|
||||
o_pwm);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_rst_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input i_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_rst_n;
|
||||
input i_en;
|
||||
output o_vld;
|
||||
output o_pwm;
|
||||
|
||||
wire \<const0> ;
|
||||
wire i_clk;
|
||||
wire i_en;
|
||||
wire i_rst_n;
|
||||
wire o_pwm;
|
||||
|
||||
assign o_vld = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design inst
|
||||
(.i_clk(i_clk),
|
||||
.i_en(i_en),
|
||||
.i_rst_n(i_rst_n),
|
||||
.o_pwm(o_pwm));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design
|
||||
(o_pwm,
|
||||
i_rst_n,
|
||||
i_en,
|
||||
i_clk);
|
||||
output o_pwm;
|
||||
input i_rst_n;
|
||||
input i_en;
|
||||
input i_clk;
|
||||
|
||||
wire \cnt[7]_i_2_n_0 ;
|
||||
wire [7:0]cnt_reg;
|
||||
wire i_clk;
|
||||
wire i_en;
|
||||
wire i_rst_n;
|
||||
wire o_pwm;
|
||||
wire o_pwm_i_1_n_0;
|
||||
wire o_pwm_i_3_n_0;
|
||||
wire [7:0]p_0_in;
|
||||
wire p_1_in;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\cnt[0]_i_1
|
||||
(.I0(cnt_reg[0]),
|
||||
.O(p_0_in[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\cnt[1]_i_1
|
||||
(.I0(cnt_reg[0]),
|
||||
.I1(cnt_reg[1]),
|
||||
.O(p_0_in[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\cnt[2]_i_1
|
||||
(.I0(cnt_reg[0]),
|
||||
.I1(cnt_reg[1]),
|
||||
.I2(cnt_reg[2]),
|
||||
.O(p_0_in[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\cnt[3]_i_1
|
||||
(.I0(cnt_reg[1]),
|
||||
.I1(cnt_reg[0]),
|
||||
.I2(cnt_reg[2]),
|
||||
.I3(cnt_reg[3]),
|
||||
.O(p_0_in[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\cnt[4]_i_1
|
||||
(.I0(cnt_reg[2]),
|
||||
.I1(cnt_reg[0]),
|
||||
.I2(cnt_reg[1]),
|
||||
.I3(cnt_reg[3]),
|
||||
.I4(cnt_reg[4]),
|
||||
.O(p_0_in[4]));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\cnt[5]_i_1
|
||||
(.I0(cnt_reg[3]),
|
||||
.I1(cnt_reg[1]),
|
||||
.I2(cnt_reg[0]),
|
||||
.I3(cnt_reg[2]),
|
||||
.I4(cnt_reg[4]),
|
||||
.I5(cnt_reg[5]),
|
||||
.O(p_0_in[5]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\cnt[6]_i_1
|
||||
(.I0(\cnt[7]_i_2_n_0 ),
|
||||
.I1(cnt_reg[6]),
|
||||
.O(p_0_in[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\cnt[7]_i_1
|
||||
(.I0(\cnt[7]_i_2_n_0 ),
|
||||
.I1(cnt_reg[6]),
|
||||
.I2(cnt_reg[7]),
|
||||
.O(p_0_in[7]));
|
||||
LUT6 #(
|
||||
.INIT(64'h8000000000000000))
|
||||
\cnt[7]_i_2
|
||||
(.I0(cnt_reg[5]),
|
||||
.I1(cnt_reg[3]),
|
||||
.I2(cnt_reg[1]),
|
||||
.I3(cnt_reg[0]),
|
||||
.I4(cnt_reg[2]),
|
||||
.I5(cnt_reg[4]),
|
||||
.O(\cnt[7]_i_2_n_0 ));
|
||||
FDRE \cnt_reg[0]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[0]),
|
||||
.Q(cnt_reg[0]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
FDRE \cnt_reg[1]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[1]),
|
||||
.Q(cnt_reg[1]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
FDRE \cnt_reg[2]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[2]),
|
||||
.Q(cnt_reg[2]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
FDRE \cnt_reg[3]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[3]),
|
||||
.Q(cnt_reg[3]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
FDRE \cnt_reg[4]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[4]),
|
||||
.Q(cnt_reg[4]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
FDRE \cnt_reg[5]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[5]),
|
||||
.Q(cnt_reg[5]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
FDRE \cnt_reg[6]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[6]),
|
||||
.Q(cnt_reg[6]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
FDRE \cnt_reg[7]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[7]),
|
||||
.Q(cnt_reg[7]),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
LUT2 #(
|
||||
.INIT(4'h7))
|
||||
o_pwm_i_1
|
||||
(.I0(i_rst_n),
|
||||
.I1(i_en),
|
||||
.O(o_pwm_i_1_n_0));
|
||||
LUT3 #(
|
||||
.INIT(8'hBF))
|
||||
o_pwm_i_2
|
||||
(.I0(o_pwm_i_3_n_0),
|
||||
.I1(cnt_reg[7]),
|
||||
.I2(cnt_reg[6]),
|
||||
.O(p_1_in));
|
||||
LUT6 #(
|
||||
.INIT(64'h0000000000005557))
|
||||
o_pwm_i_3
|
||||
(.I0(cnt_reg[3]),
|
||||
.I1(cnt_reg[2]),
|
||||
.I2(cnt_reg[1]),
|
||||
.I3(cnt_reg[0]),
|
||||
.I4(cnt_reg[5]),
|
||||
.I5(cnt_reg[4]),
|
||||
.O(o_pwm_i_3_n_0));
|
||||
FDRE o_pwm_reg
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(o_pwm),
|
||||
.R(o_pwm_i_1_n_0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@ -0,0 +1,286 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 19 10:05:44 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_vlg_design_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design is
|
||||
port (
|
||||
o_pwm : out STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
i_clk : in STD_LOGIC
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design is
|
||||
signal \cnt[7]_i_2_n_0\ : STD_LOGIC;
|
||||
signal cnt_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal o_pwm_i_1_n_0 : STD_LOGIC;
|
||||
signal o_pwm_i_3_n_0 : STD_LOGIC;
|
||||
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal p_1_in : STD_LOGIC;
|
||||
attribute SOFT_HLUTNM : string;
|
||||
attribute SOFT_HLUTNM of \cnt[1]_i_1\ : label is "soft_lutpair2";
|
||||
attribute SOFT_HLUTNM of \cnt[2]_i_1\ : label is "soft_lutpair2";
|
||||
attribute SOFT_HLUTNM of \cnt[3]_i_1\ : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of \cnt[4]_i_1\ : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of \cnt[6]_i_1\ : label is "soft_lutpair1";
|
||||
attribute SOFT_HLUTNM of \cnt[7]_i_1\ : label is "soft_lutpair1";
|
||||
begin
|
||||
\cnt[0]_i_1\: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(0),
|
||||
O => p_0_in(0)
|
||||
);
|
||||
\cnt[1]_i_1\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(0),
|
||||
I1 => cnt_reg(1),
|
||||
O => p_0_in(1)
|
||||
);
|
||||
\cnt[2]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"78"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(0),
|
||||
I1 => cnt_reg(1),
|
||||
I2 => cnt_reg(2),
|
||||
O => p_0_in(2)
|
||||
);
|
||||
\cnt[3]_i_1\: unisim.vcomponents.LUT4
|
||||
generic map(
|
||||
INIT => X"7F80"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(1),
|
||||
I1 => cnt_reg(0),
|
||||
I2 => cnt_reg(2),
|
||||
I3 => cnt_reg(3),
|
||||
O => p_0_in(3)
|
||||
);
|
||||
\cnt[4]_i_1\: unisim.vcomponents.LUT5
|
||||
generic map(
|
||||
INIT => X"7FFF8000"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(2),
|
||||
I1 => cnt_reg(0),
|
||||
I2 => cnt_reg(1),
|
||||
I3 => cnt_reg(3),
|
||||
I4 => cnt_reg(4),
|
||||
O => p_0_in(4)
|
||||
);
|
||||
\cnt[5]_i_1\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"7FFFFFFF80000000"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(3),
|
||||
I1 => cnt_reg(1),
|
||||
I2 => cnt_reg(0),
|
||||
I3 => cnt_reg(2),
|
||||
I4 => cnt_reg(4),
|
||||
I5 => cnt_reg(5),
|
||||
O => p_0_in(5)
|
||||
);
|
||||
\cnt[6]_i_1\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => \cnt[7]_i_2_n_0\,
|
||||
I1 => cnt_reg(6),
|
||||
O => p_0_in(6)
|
||||
);
|
||||
\cnt[7]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"78"
|
||||
)
|
||||
port map (
|
||||
I0 => \cnt[7]_i_2_n_0\,
|
||||
I1 => cnt_reg(6),
|
||||
I2 => cnt_reg(7),
|
||||
O => p_0_in(7)
|
||||
);
|
||||
\cnt[7]_i_2\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"8000000000000000"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(5),
|
||||
I1 => cnt_reg(3),
|
||||
I2 => cnt_reg(1),
|
||||
I3 => cnt_reg(0),
|
||||
I4 => cnt_reg(2),
|
||||
I5 => cnt_reg(4),
|
||||
O => \cnt[7]_i_2_n_0\
|
||||
);
|
||||
\cnt_reg[0]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(0),
|
||||
Q => cnt_reg(0),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
\cnt_reg[1]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(1),
|
||||
Q => cnt_reg(1),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
\cnt_reg[2]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(2),
|
||||
Q => cnt_reg(2),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
\cnt_reg[3]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(3),
|
||||
Q => cnt_reg(3),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
\cnt_reg[4]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(4),
|
||||
Q => cnt_reg(4),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
\cnt_reg[5]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(5),
|
||||
Q => cnt_reg(5),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
\cnt_reg[6]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(6),
|
||||
Q => cnt_reg(6),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
\cnt_reg[7]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(7),
|
||||
Q => cnt_reg(7),
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
o_pwm_i_1: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"7"
|
||||
)
|
||||
port map (
|
||||
I0 => i_rst_n,
|
||||
I1 => i_en,
|
||||
O => o_pwm_i_1_n_0
|
||||
);
|
||||
o_pwm_i_2: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"BF"
|
||||
)
|
||||
port map (
|
||||
I0 => o_pwm_i_3_n_0,
|
||||
I1 => cnt_reg(7),
|
||||
I2 => cnt_reg(6),
|
||||
O => p_1_in
|
||||
);
|
||||
o_pwm_i_3: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"0000000000005557"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(3),
|
||||
I1 => cnt_reg(2),
|
||||
I2 => cnt_reg(1),
|
||||
I3 => cnt_reg(0),
|
||||
I4 => cnt_reg(5),
|
||||
I5 => cnt_reg(4),
|
||||
O => o_pwm_i_3_n_0
|
||||
);
|
||||
o_pwm_reg: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_1_in,
|
||||
Q => o_pwm,
|
||||
R => o_pwm_i_1_n_0
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
i_clk : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
o_vld : out STD_LOGIC;
|
||||
o_pwm : out STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_vlg_design_0_0,vlg_design,{}";
|
||||
attribute DowngradeIPIdentifiedWarnings : string;
|
||||
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute IP_DEFINITION_SOURCE : string;
|
||||
attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "module_ref";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vlg_design,Vivado 2022.2";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i_clk : signal is "xilinx.com:signal:clock:1.0 i_clk CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of i_clk : signal is "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_rst_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of i_rst_n : signal is "xilinx.com:signal:reset:1.0 i_rst_n RST";
|
||||
attribute X_INTERFACE_PARAMETER of i_rst_n : signal is "XIL_INTERFACENAME i_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
begin
|
||||
o_vld <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design
|
||||
port map (
|
||||
i_clk => i_clk,
|
||||
i_en => i_en,
|
||||
i_rst_n => i_rst_n,
|
||||
o_pwm => o_pwm
|
||||
);
|
||||
end STRUCTURE;
|
||||
@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 19 10:05:44 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_stub.v
|
||||
// Design : design_1_vlg_design_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vlg_design,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(i_clk, i_rst_n, i_en, o_vld, o_pwm)
|
||||
/* synthesis syn_black_box black_box_pad_pin="i_clk,i_rst_n,i_en,o_vld,o_pwm" */;
|
||||
input i_clk;
|
||||
input i_rst_n;
|
||||
input i_en;
|
||||
output o_vld;
|
||||
output o_pwm;
|
||||
endmodule
|
||||
@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 19 10:05:44 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_stub.vhdl
|
||||
-- Design : design_1_vlg_design_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
i_clk : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
o_vld : out STD_LOGIC;
|
||||
o_pwm : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "i_clk,i_rst_n,i_en,o_vld,o_pwm";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vlg_design,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
3146
ax_dma.cache/ip/2022.2/1/2/12b793b88cebb0ed/12b793b88cebb0ed.xci
Normal file
3146
ax_dma.cache/ip/2022.2/1/2/12b793b88cebb0ed/12b793b88cebb0ed.xci
Normal file
File diff suppressed because it is too large
Load Diff
BIN
ax_dma.cache/ip/2022.2/1/2/12b793b88cebb0ed/design_1_ila_0_0.dcp
Normal file
BIN
ax_dma.cache/ip/2022.2/1/2/12b793b88cebb0ed/design_1_ila_0_0.dcp
Normal file
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -0,0 +1,23 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 26 20:08:42 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_ila_0_0_stub.v
|
||||
// Design : design_1_ila_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
endmodule
|
||||
@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 26 20:08:42 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_ila_0_0_stub.vhdl
|
||||
-- Design : design_1_ila_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,51 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>1fd50b2e878b726d</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_auto_pc_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_protocol_converter" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_auto_pc_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_PROTOCOL">AXI3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRANSLATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">1fd50b2e878b726d</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">e97dabbb</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">119</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,87 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 26 20:07:38 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_stub.v
|
||||
// Design : design_1_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_27_axi_protocol_converter,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
@ -0,0 +1,88 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 26 20:07:38 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_stub.vhdl
|
||||
-- Design : design_1_auto_pc_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_awvalid : out STD_LOGIC;
|
||||
m_axi_awready : in STD_LOGIC;
|
||||
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_wvalid : out STD_LOGIC;
|
||||
m_axi_wready : in STD_LOGIC;
|
||||
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_bvalid : in STD_LOGIC;
|
||||
m_axi_bready : out STD_LOGIC;
|
||||
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_arvalid : out STD_LOGIC;
|
||||
m_axi_arready : in STD_LOGIC;
|
||||
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_rvalid : in STD_LOGIC;
|
||||
m_axi_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_27_axi_protocol_converter,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
2
ax_dma.cache/ip/2022.2/1/f/1fd50b2e878b726d/stats.txt
Normal file
2
ax_dma.cache/ip/2022.2/1/f/1fd50b2e878b726d/stats.txt
Normal file
@ -0,0 +1,2 @@
|
||||
NumberHits:32
|
||||
Timestamp: Tue May 28 13:44:49 UTC 2024
|
||||
3146
ax_dma.cache/ip/2022.2/2/0/2059d880a7ffc8c2/2059d880a7ffc8c2.xci
Normal file
3146
ax_dma.cache/ip/2022.2/2/0/2059d880a7ffc8c2/2059d880a7ffc8c2.xci
Normal file
File diff suppressed because it is too large
Load Diff
BIN
ax_dma.cache/ip/2022.2/2/0/2059d880a7ffc8c2/design_1_ila_0_0.dcp
Normal file
BIN
ax_dma.cache/ip/2022.2/2/0/2059d880a7ffc8c2/design_1_ila_0_0.dcp
Normal file
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 26 03:49:29 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_ila_0_0_stub.v
|
||||
// Design : design_1_ila_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
endmodule
|
||||
@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 26 03:49:29 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_ila_0_0_stub.vhdl
|
||||
-- Design : design_1_ila_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
2
ax_dma.cache/ip/2022.2/2/0/2059d880a7ffc8c2/stats.txt
Normal file
2
ax_dma.cache/ip/2022.2/2/0/2059d880a7ffc8c2/stats.txt
Normal file
@ -0,0 +1,2 @@
|
||||
NumberHits:3
|
||||
Timestamp: Tue May 28 08:46:48 UTC 2024
|
||||
@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>25a52dffdf0e4b40</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="axi_pwm_v1_0_S00_AXI" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">25a52dffdf0e4b40</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">908f4181</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">91</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,45 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 26 20:07:10 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v
|
||||
// Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_pwm_v1_0_S00_AXI,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pwm_out, S_AXI_ACLK, S_AXI_ARESETN,
|
||||
S_AXI_AWADDR, S_AXI_AWPROT, S_AXI_AWVALID, S_AXI_AWREADY, S_AXI_WDATA, S_AXI_WSTRB,
|
||||
S_AXI_WVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_BREADY, S_AXI_ARADDR,
|
||||
S_AXI_ARPROT, S_AXI_ARVALID, S_AXI_ARREADY, S_AXI_RDATA, S_AXI_RRESP, S_AXI_RVALID,
|
||||
S_AXI_RREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY" */;
|
||||
output pwm_out;
|
||||
input S_AXI_ACLK;
|
||||
input S_AXI_ARESETN;
|
||||
input [3:0]S_AXI_AWADDR;
|
||||
input [2:0]S_AXI_AWPROT;
|
||||
input S_AXI_AWVALID;
|
||||
output S_AXI_AWREADY;
|
||||
input [31:0]S_AXI_WDATA;
|
||||
input [3:0]S_AXI_WSTRB;
|
||||
input S_AXI_WVALID;
|
||||
output S_AXI_WREADY;
|
||||
output [1:0]S_AXI_BRESP;
|
||||
output S_AXI_BVALID;
|
||||
input S_AXI_BREADY;
|
||||
input [3:0]S_AXI_ARADDR;
|
||||
input [2:0]S_AXI_ARPROT;
|
||||
input S_AXI_ARVALID;
|
||||
output S_AXI_ARREADY;
|
||||
output [31:0]S_AXI_RDATA;
|
||||
output [1:0]S_AXI_RRESP;
|
||||
output S_AXI_RVALID;
|
||||
input S_AXI_RREADY;
|
||||
endmodule
|
||||
@ -0,0 +1,51 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 26 20:07:10 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.vhdl
|
||||
-- Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
pwm_out : out STD_LOGIC;
|
||||
S_AXI_ACLK : in STD_LOGIC;
|
||||
S_AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_pwm_v1_0_S00_AXI,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
2
ax_dma.cache/ip/2022.2/2/5/25a52dffdf0e4b40/stats.txt
Normal file
2
ax_dma.cache/ip/2022.2/2/5/25a52dffdf0e4b40/stats.txt
Normal file
@ -0,0 +1,2 @@
|
||||
NumberHits:2
|
||||
Timestamp: Tue May 28 01:31:25 UTC 2024
|
||||
@ -0,0 +1,39 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>30807cbbadab74ba</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_vlg_design_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="vlg_design" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CNT_MAX">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CNT_MAX_PERCENT">25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_vlg_design_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">30807cbbadab74ba</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">7aa944fa</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">38</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
@ -0,0 +1,328 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 19 11:18:12 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_sim_netlist.v
|
||||
// Design : design_1_vlg_design_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_vlg_design_0_0,vlg_design,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* X_CORE_INFO = "vlg_design,Vivado 2022.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(i_clk,
|
||||
i_rst_n,
|
||||
i_en,
|
||||
o_vld,
|
||||
o_pwm);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_rst_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input i_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_rst_n;
|
||||
input i_en;
|
||||
output o_vld;
|
||||
output o_pwm;
|
||||
|
||||
wire i_clk;
|
||||
wire i_en;
|
||||
wire i_rst_n;
|
||||
wire o_pwm;
|
||||
wire o_vld;
|
||||
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design inst
|
||||
(.i_clk(i_clk),
|
||||
.i_en(i_en),
|
||||
.i_rst_n(i_rst_n),
|
||||
.o_pwm(o_pwm),
|
||||
.o_vld(o_vld));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design
|
||||
(o_vld,
|
||||
o_pwm,
|
||||
i_clk,
|
||||
i_en,
|
||||
i_rst_n);
|
||||
output o_vld;
|
||||
output o_pwm;
|
||||
input i_clk;
|
||||
input i_en;
|
||||
input i_rst_n;
|
||||
|
||||
wire \cnt[6]_i_1_n_0 ;
|
||||
wire \cnt[6]_i_3_n_0 ;
|
||||
wire \cnt[6]_i_4_n_0 ;
|
||||
wire [6:0]cnt_reg;
|
||||
wire i_clk;
|
||||
wire i_en;
|
||||
wire i_rst_n;
|
||||
wire o_pwm;
|
||||
wire o_pwm_i_1_n_0;
|
||||
wire o_vld;
|
||||
wire o_vld_i_1_n_0;
|
||||
wire o_vld_i_2_n_0;
|
||||
wire [6:0]p_0_in;
|
||||
wire p_0_in__0;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\cnt[0]_i_1
|
||||
(.I0(cnt_reg[0]),
|
||||
.O(p_0_in[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\cnt[1]_i_1
|
||||
(.I0(cnt_reg[0]),
|
||||
.I1(cnt_reg[1]),
|
||||
.O(p_0_in[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\cnt[2]_i_1
|
||||
(.I0(cnt_reg[0]),
|
||||
.I1(cnt_reg[1]),
|
||||
.I2(cnt_reg[2]),
|
||||
.O(p_0_in[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\cnt[3]_i_1
|
||||
(.I0(cnt_reg[1]),
|
||||
.I1(cnt_reg[0]),
|
||||
.I2(cnt_reg[2]),
|
||||
.I3(cnt_reg[3]),
|
||||
.O(p_0_in[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\cnt[4]_i_1
|
||||
(.I0(cnt_reg[2]),
|
||||
.I1(cnt_reg[0]),
|
||||
.I2(cnt_reg[1]),
|
||||
.I3(cnt_reg[3]),
|
||||
.I4(cnt_reg[4]),
|
||||
.O(p_0_in[4]));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\cnt[5]_i_1
|
||||
(.I0(cnt_reg[3]),
|
||||
.I1(cnt_reg[1]),
|
||||
.I2(cnt_reg[0]),
|
||||
.I3(cnt_reg[2]),
|
||||
.I4(cnt_reg[4]),
|
||||
.I5(cnt_reg[5]),
|
||||
.O(p_0_in[5]));
|
||||
LUT6 #(
|
||||
.INIT(64'hD555D5D5FFFFFFFF))
|
||||
\cnt[6]_i_1
|
||||
(.I0(i_en),
|
||||
.I1(cnt_reg[6]),
|
||||
.I2(cnt_reg[5]),
|
||||
.I3(cnt_reg[2]),
|
||||
.I4(\cnt[6]_i_3_n_0 ),
|
||||
.I5(i_rst_n),
|
||||
.O(\cnt[6]_i_1_n_0 ));
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\cnt[6]_i_2
|
||||
(.I0(\cnt[6]_i_4_n_0 ),
|
||||
.I1(cnt_reg[5]),
|
||||
.I2(cnt_reg[6]),
|
||||
.O(p_0_in[6]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h1))
|
||||
\cnt[6]_i_3
|
||||
(.I0(cnt_reg[4]),
|
||||
.I1(cnt_reg[3]),
|
||||
.O(\cnt[6]_i_3_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h80000000))
|
||||
\cnt[6]_i_4
|
||||
(.I0(cnt_reg[4]),
|
||||
.I1(cnt_reg[2]),
|
||||
.I2(cnt_reg[0]),
|
||||
.I3(cnt_reg[1]),
|
||||
.I4(cnt_reg[3]),
|
||||
.O(\cnt[6]_i_4_n_0 ));
|
||||
FDRE \cnt_reg[0]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[0]),
|
||||
.Q(cnt_reg[0]),
|
||||
.R(\cnt[6]_i_1_n_0 ));
|
||||
FDRE \cnt_reg[1]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[1]),
|
||||
.Q(cnt_reg[1]),
|
||||
.R(\cnt[6]_i_1_n_0 ));
|
||||
FDRE \cnt_reg[2]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[2]),
|
||||
.Q(cnt_reg[2]),
|
||||
.R(\cnt[6]_i_1_n_0 ));
|
||||
FDRE \cnt_reg[3]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[3]),
|
||||
.Q(cnt_reg[3]),
|
||||
.R(\cnt[6]_i_1_n_0 ));
|
||||
FDRE \cnt_reg[4]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[4]),
|
||||
.Q(cnt_reg[4]),
|
||||
.R(\cnt[6]_i_1_n_0 ));
|
||||
FDRE \cnt_reg[5]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[5]),
|
||||
.Q(cnt_reg[5]),
|
||||
.R(\cnt[6]_i_1_n_0 ));
|
||||
FDRE \cnt_reg[6]
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_0_in[6]),
|
||||
.Q(cnt_reg[6]),
|
||||
.R(\cnt[6]_i_1_n_0 ));
|
||||
LUT3 #(
|
||||
.INIT(8'h80))
|
||||
o_pwm_i_1
|
||||
(.I0(p_0_in__0),
|
||||
.I1(i_en),
|
||||
.I2(i_rst_n),
|
||||
.O(o_pwm_i_1_n_0));
|
||||
LUT6 #(
|
||||
.INIT(64'h0000000000001FFF))
|
||||
o_pwm_i_2
|
||||
(.I0(cnt_reg[1]),
|
||||
.I1(cnt_reg[2]),
|
||||
.I2(cnt_reg[3]),
|
||||
.I3(cnt_reg[4]),
|
||||
.I4(cnt_reg[6]),
|
||||
.I5(cnt_reg[5]),
|
||||
.O(p_0_in__0));
|
||||
FDRE o_pwm_reg
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(o_pwm_i_1_n_0),
|
||||
.Q(o_pwm),
|
||||
.R(1'b0));
|
||||
LUT6 #(
|
||||
.INIT(64'h0004000000000000))
|
||||
o_vld_i_1
|
||||
(.I0(o_vld_i_2_n_0),
|
||||
.I1(cnt_reg[6]),
|
||||
.I2(cnt_reg[0]),
|
||||
.I3(cnt_reg[1]),
|
||||
.I4(i_en),
|
||||
.I5(i_rst_n),
|
||||
.O(o_vld_i_1_n_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'hEFFF))
|
||||
o_vld_i_2
|
||||
(.I0(cnt_reg[3]),
|
||||
.I1(cnt_reg[4]),
|
||||
.I2(cnt_reg[2]),
|
||||
.I3(cnt_reg[5]),
|
||||
.O(o_vld_i_2_n_0));
|
||||
FDRE o_vld_reg
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(o_vld_i_1_n_0),
|
||||
.Q(o_vld),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@ -0,0 +1,314 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 19 11:18:12 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_vlg_design_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design is
|
||||
port (
|
||||
o_vld : out STD_LOGIC;
|
||||
o_pwm : out STD_LOGIC;
|
||||
i_clk : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design is
|
||||
signal \cnt[6]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \cnt[6]_i_3_n_0\ : STD_LOGIC;
|
||||
signal \cnt[6]_i_4_n_0\ : STD_LOGIC;
|
||||
signal cnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
signal o_pwm_i_1_n_0 : STD_LOGIC;
|
||||
signal o_vld_i_1_n_0 : STD_LOGIC;
|
||||
signal o_vld_i_2_n_0 : STD_LOGIC;
|
||||
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
signal \p_0_in__0\ : STD_LOGIC;
|
||||
attribute SOFT_HLUTNM : string;
|
||||
attribute SOFT_HLUTNM of \cnt[0]_i_1\ : label is "soft_lutpair3";
|
||||
attribute SOFT_HLUTNM of \cnt[1]_i_1\ : label is "soft_lutpair3";
|
||||
attribute SOFT_HLUTNM of \cnt[2]_i_1\ : label is "soft_lutpair1";
|
||||
attribute SOFT_HLUTNM of \cnt[3]_i_1\ : label is "soft_lutpair1";
|
||||
attribute SOFT_HLUTNM of \cnt[4]_i_1\ : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of \cnt[6]_i_3\ : label is "soft_lutpair2";
|
||||
attribute SOFT_HLUTNM of \cnt[6]_i_4\ : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of o_vld_i_2 : label is "soft_lutpair2";
|
||||
begin
|
||||
\cnt[0]_i_1\: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(0),
|
||||
O => p_0_in(0)
|
||||
);
|
||||
\cnt[1]_i_1\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(0),
|
||||
I1 => cnt_reg(1),
|
||||
O => p_0_in(1)
|
||||
);
|
||||
\cnt[2]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"78"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(0),
|
||||
I1 => cnt_reg(1),
|
||||
I2 => cnt_reg(2),
|
||||
O => p_0_in(2)
|
||||
);
|
||||
\cnt[3]_i_1\: unisim.vcomponents.LUT4
|
||||
generic map(
|
||||
INIT => X"7F80"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(1),
|
||||
I1 => cnt_reg(0),
|
||||
I2 => cnt_reg(2),
|
||||
I3 => cnt_reg(3),
|
||||
O => p_0_in(3)
|
||||
);
|
||||
\cnt[4]_i_1\: unisim.vcomponents.LUT5
|
||||
generic map(
|
||||
INIT => X"7FFF8000"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(2),
|
||||
I1 => cnt_reg(0),
|
||||
I2 => cnt_reg(1),
|
||||
I3 => cnt_reg(3),
|
||||
I4 => cnt_reg(4),
|
||||
O => p_0_in(4)
|
||||
);
|
||||
\cnt[5]_i_1\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"7FFFFFFF80000000"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(3),
|
||||
I1 => cnt_reg(1),
|
||||
I2 => cnt_reg(0),
|
||||
I3 => cnt_reg(2),
|
||||
I4 => cnt_reg(4),
|
||||
I5 => cnt_reg(5),
|
||||
O => p_0_in(5)
|
||||
);
|
||||
\cnt[6]_i_1\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"D555D5D5FFFFFFFF"
|
||||
)
|
||||
port map (
|
||||
I0 => i_en,
|
||||
I1 => cnt_reg(6),
|
||||
I2 => cnt_reg(5),
|
||||
I3 => cnt_reg(2),
|
||||
I4 => \cnt[6]_i_3_n_0\,
|
||||
I5 => i_rst_n,
|
||||
O => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
\cnt[6]_i_2\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"78"
|
||||
)
|
||||
port map (
|
||||
I0 => \cnt[6]_i_4_n_0\,
|
||||
I1 => cnt_reg(5),
|
||||
I2 => cnt_reg(6),
|
||||
O => p_0_in(6)
|
||||
);
|
||||
\cnt[6]_i_3\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(4),
|
||||
I1 => cnt_reg(3),
|
||||
O => \cnt[6]_i_3_n_0\
|
||||
);
|
||||
\cnt[6]_i_4\: unisim.vcomponents.LUT5
|
||||
generic map(
|
||||
INIT => X"80000000"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(4),
|
||||
I1 => cnt_reg(2),
|
||||
I2 => cnt_reg(0),
|
||||
I3 => cnt_reg(1),
|
||||
I4 => cnt_reg(3),
|
||||
O => \cnt[6]_i_4_n_0\
|
||||
);
|
||||
\cnt_reg[0]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(0),
|
||||
Q => cnt_reg(0),
|
||||
R => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
\cnt_reg[1]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(1),
|
||||
Q => cnt_reg(1),
|
||||
R => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
\cnt_reg[2]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(2),
|
||||
Q => cnt_reg(2),
|
||||
R => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
\cnt_reg[3]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(3),
|
||||
Q => cnt_reg(3),
|
||||
R => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
\cnt_reg[4]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(4),
|
||||
Q => cnt_reg(4),
|
||||
R => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
\cnt_reg[5]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(5),
|
||||
Q => cnt_reg(5),
|
||||
R => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
\cnt_reg[6]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => p_0_in(6),
|
||||
Q => cnt_reg(6),
|
||||
R => \cnt[6]_i_1_n_0\
|
||||
);
|
||||
o_pwm_i_1: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"80"
|
||||
)
|
||||
port map (
|
||||
I0 => \p_0_in__0\,
|
||||
I1 => i_en,
|
||||
I2 => i_rst_n,
|
||||
O => o_pwm_i_1_n_0
|
||||
);
|
||||
o_pwm_i_2: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"0000000000001FFF"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(1),
|
||||
I1 => cnt_reg(2),
|
||||
I2 => cnt_reg(3),
|
||||
I3 => cnt_reg(4),
|
||||
I4 => cnt_reg(6),
|
||||
I5 => cnt_reg(5),
|
||||
O => \p_0_in__0\
|
||||
);
|
||||
o_pwm_reg: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => o_pwm_i_1_n_0,
|
||||
Q => o_pwm,
|
||||
R => '0'
|
||||
);
|
||||
o_vld_i_1: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"0004000000000000"
|
||||
)
|
||||
port map (
|
||||
I0 => o_vld_i_2_n_0,
|
||||
I1 => cnt_reg(6),
|
||||
I2 => cnt_reg(0),
|
||||
I3 => cnt_reg(1),
|
||||
I4 => i_en,
|
||||
I5 => i_rst_n,
|
||||
O => o_vld_i_1_n_0
|
||||
);
|
||||
o_vld_i_2: unisim.vcomponents.LUT4
|
||||
generic map(
|
||||
INIT => X"EFFF"
|
||||
)
|
||||
port map (
|
||||
I0 => cnt_reg(3),
|
||||
I1 => cnt_reg(4),
|
||||
I2 => cnt_reg(2),
|
||||
I3 => cnt_reg(5),
|
||||
O => o_vld_i_2_n_0
|
||||
);
|
||||
o_vld_reg: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => o_vld_i_1_n_0,
|
||||
Q => o_vld,
|
||||
R => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
i_clk : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
o_vld : out STD_LOGIC;
|
||||
o_pwm : out STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_vlg_design_0_0,vlg_design,{}";
|
||||
attribute DowngradeIPIdentifiedWarnings : string;
|
||||
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute IP_DEFINITION_SOURCE : string;
|
||||
attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "module_ref";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vlg_design,Vivado 2022.2";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i_clk : signal is "xilinx.com:signal:clock:1.0 i_clk CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of i_clk : signal is "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_rst_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of i_rst_n : signal is "xilinx.com:signal:reset:1.0 i_rst_n RST";
|
||||
attribute X_INTERFACE_PARAMETER of i_rst_n : signal is "XIL_INTERFACENAME i_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
begin
|
||||
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design
|
||||
port map (
|
||||
i_clk => i_clk,
|
||||
i_en => i_en,
|
||||
i_rst_n => i_rst_n,
|
||||
o_pwm => o_pwm,
|
||||
o_vld => o_vld
|
||||
);
|
||||
end STRUCTURE;
|
||||
@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 19 11:18:12 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_stub.v
|
||||
// Design : design_1_vlg_design_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vlg_design,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(i_clk, i_rst_n, i_en, o_vld, o_pwm)
|
||||
/* synthesis syn_black_box black_box_pad_pin="i_clk,i_rst_n,i_en,o_vld,o_pwm" */;
|
||||
input i_clk;
|
||||
input i_rst_n;
|
||||
input i_en;
|
||||
output o_vld;
|
||||
output o_pwm;
|
||||
endmodule
|
||||
@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 19 11:18:12 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_stub.vhdl
|
||||
-- Design : design_1_vlg_design_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
i_clk : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
o_vld : out STD_LOGIC;
|
||||
o_pwm : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "i_clk,i_rst_n,i_en,o_vld,o_pwm";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vlg_design,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>335e54c50521197c</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="axi_pwm_v1_0_S00_AXI" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">335e54c50521197c</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">19b55241</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">55</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,46 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Tue May 28 21:46:09 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v
|
||||
// Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_pwm_v1_0_S00_AXI,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pwm_out, pwn_reg, S_AXI_ACLK, S_AXI_ARESETN,
|
||||
S_AXI_AWADDR, S_AXI_AWPROT, S_AXI_AWVALID, S_AXI_AWREADY, S_AXI_WDATA, S_AXI_WSTRB,
|
||||
S_AXI_WVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_BREADY, S_AXI_ARADDR,
|
||||
S_AXI_ARPROT, S_AXI_ARVALID, S_AXI_ARREADY, S_AXI_RDATA, S_AXI_RRESP, S_AXI_RVALID,
|
||||
S_AXI_RREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="pwm_out,pwn_reg[31:0],S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY" */;
|
||||
output pwm_out;
|
||||
output [31:0]pwn_reg;
|
||||
input S_AXI_ACLK;
|
||||
input S_AXI_ARESETN;
|
||||
input [3:0]S_AXI_AWADDR;
|
||||
input [2:0]S_AXI_AWPROT;
|
||||
input S_AXI_AWVALID;
|
||||
output S_AXI_AWREADY;
|
||||
input [31:0]S_AXI_WDATA;
|
||||
input [3:0]S_AXI_WSTRB;
|
||||
input S_AXI_WVALID;
|
||||
output S_AXI_WREADY;
|
||||
output [1:0]S_AXI_BRESP;
|
||||
output S_AXI_BVALID;
|
||||
input S_AXI_BREADY;
|
||||
input [3:0]S_AXI_ARADDR;
|
||||
input [2:0]S_AXI_ARPROT;
|
||||
input S_AXI_ARVALID;
|
||||
output S_AXI_ARREADY;
|
||||
output [31:0]S_AXI_RDATA;
|
||||
output [1:0]S_AXI_RRESP;
|
||||
output S_AXI_RVALID;
|
||||
input S_AXI_RREADY;
|
||||
endmodule
|
||||
@ -0,0 +1,52 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Tue May 28 21:46:09 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.vhdl
|
||||
-- Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
pwm_out : out STD_LOGIC;
|
||||
pwn_reg : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ACLK : in STD_LOGIC;
|
||||
S_AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "pwm_out,pwn_reg[31:0],S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_pwm_v1_0_S00_AXI,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,66 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>37a04589c4edf9fa</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>dbg_hub</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xsdbm" spirit:version="3.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCANID">76546592</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCAN_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCAN_MODE_WITH_CORE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BUILD_REVISION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLK_INPUT_FREQ_HZ">300000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MAJOR_VER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MINOR_ALPHA_VER">97</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MINOR_VER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DCLK_HAS_RESET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DIVCLK_DIVIDE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ENABLE_CLK_DIVIDER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_BSCANID_VEC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_INT_SIM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_STYLE">SUBCORE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MAJOR_VERSION">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MINOR_VERSION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BSCAN_MASTER_PORTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TWO_PRIM_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USER_SCAN_CHAIN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USER_SCAN_CHAIN1">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BUFR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXT_BSCAN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_NUM_SLAVES">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_PERIOD_FRC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_PERIOD_INT">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">dbg_hub</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">37a04589c4edf9fa</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">c7aff28e</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">87</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub.dcp
Normal file
BIN
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub.dcp
Normal file
Binary file not shown.
13866
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub_sim_netlist.v
Normal file
13866
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub_sim_netlist.v
Normal file
File diff suppressed because it is too large
Load Diff
18943
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub_sim_netlist.vhdl
Normal file
18943
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub_sim_netlist.vhdl
Normal file
File diff suppressed because it is too large
Load Diff
25
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub_stub.v
Normal file
25
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/dbg_hub_stub.v
Normal file
@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Tue May 28 10:35:15 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.v
|
||||
// Design : dbg_hub
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "xsdbm_v3_0_0_xsdbm,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sl_iport0_o, sl_iport1_o, sl_oport0_i,
|
||||
sl_oport1_i, clk)
|
||||
/* synthesis syn_black_box black_box_pad_pin="sl_iport0_o[36:0],sl_iport1_o[36:0],sl_oport0_i[16:0],sl_oport1_i[16:0],clk" */;
|
||||
output [36:0]sl_iport0_o;
|
||||
output [36:0]sl_iport1_o;
|
||||
input [16:0]sl_oport0_i;
|
||||
input [16:0]sl_oport1_i;
|
||||
input clk;
|
||||
endmodule
|
||||
@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Tue May 28 10:35:15 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.vhdl
|
||||
-- Design : dbg_hub
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
sl_iport0_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
|
||||
sl_iport1_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
|
||||
sl_oport0_i : in STD_LOGIC_VECTOR ( 16 downto 0 );
|
||||
sl_oport1_i : in STD_LOGIC_VECTOR ( 16 downto 0 );
|
||||
clk : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "sl_iport0_o[36:0],sl_iport1_o[36:0],sl_oport0_i[16:0],sl_oport1_i[16:0],clk";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "xsdbm_v3_0_0_xsdbm,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
2
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/stats.txt
Normal file
2
ax_dma.cache/ip/2022.2/3/7/37a04589c4edf9fa/stats.txt
Normal file
@ -0,0 +1,2 @@
|
||||
NumberHits:17
|
||||
Timestamp: Tue May 28 13:49:29 UTC 2024
|
||||
@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>3db80204adfc9bc0</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="axi_pwm_v1_0_S00_AXI" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">3db80204adfc9bc0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">cdb8b834</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">42</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,45 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Tue May 28 14:18:13 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v
|
||||
// Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_pwm_v1_0_S00_AXI,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pwm_out, S_AXI_ACLK, S_AXI_ARESETN,
|
||||
S_AXI_AWADDR, S_AXI_AWPROT, S_AXI_AWVALID, S_AXI_AWREADY, S_AXI_WDATA, S_AXI_WSTRB,
|
||||
S_AXI_WVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_BREADY, S_AXI_ARADDR,
|
||||
S_AXI_ARPROT, S_AXI_ARVALID, S_AXI_ARREADY, S_AXI_RDATA, S_AXI_RRESP, S_AXI_RVALID,
|
||||
S_AXI_RREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY" */;
|
||||
output pwm_out;
|
||||
input S_AXI_ACLK;
|
||||
input S_AXI_ARESETN;
|
||||
input [3:0]S_AXI_AWADDR;
|
||||
input [2:0]S_AXI_AWPROT;
|
||||
input S_AXI_AWVALID;
|
||||
output S_AXI_AWREADY;
|
||||
input [31:0]S_AXI_WDATA;
|
||||
input [3:0]S_AXI_WSTRB;
|
||||
input S_AXI_WVALID;
|
||||
output S_AXI_WREADY;
|
||||
output [1:0]S_AXI_BRESP;
|
||||
output S_AXI_BVALID;
|
||||
input S_AXI_BREADY;
|
||||
input [3:0]S_AXI_ARADDR;
|
||||
input [2:0]S_AXI_ARPROT;
|
||||
input S_AXI_ARVALID;
|
||||
output S_AXI_ARREADY;
|
||||
output [31:0]S_AXI_RDATA;
|
||||
output [1:0]S_AXI_RRESP;
|
||||
output S_AXI_RVALID;
|
||||
input S_AXI_RREADY;
|
||||
endmodule
|
||||
@ -0,0 +1,51 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Tue May 28 14:18:13 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.vhdl
|
||||
-- Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
pwm_out : out STD_LOGIC;
|
||||
S_AXI_ACLK : in STD_LOGIC;
|
||||
S_AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_pwm_v1_0_S00_AXI,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>41fbe9fa773b1e7c</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="axi_pwm_v1_0_S00_AXI" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">49994999</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_axi_pwm_v1_0_S00_AXI_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">41fbe9fa773b1e7c</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">717201c5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">51</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,45 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Tue May 28 16:48:33 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v
|
||||
// Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_pwm_v1_0_S00_AXI,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pwm_out, S_AXI_ACLK, S_AXI_ARESETN,
|
||||
S_AXI_AWADDR, S_AXI_AWPROT, S_AXI_AWVALID, S_AXI_AWREADY, S_AXI_WDATA, S_AXI_WSTRB,
|
||||
S_AXI_WVALID, S_AXI_WREADY, S_AXI_BRESP, S_AXI_BVALID, S_AXI_BREADY, S_AXI_ARADDR,
|
||||
S_AXI_ARPROT, S_AXI_ARVALID, S_AXI_ARREADY, S_AXI_RDATA, S_AXI_RRESP, S_AXI_RVALID,
|
||||
S_AXI_RREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY" */;
|
||||
output pwm_out;
|
||||
input S_AXI_ACLK;
|
||||
input S_AXI_ARESETN;
|
||||
input [3:0]S_AXI_AWADDR;
|
||||
input [2:0]S_AXI_AWPROT;
|
||||
input S_AXI_AWVALID;
|
||||
output S_AXI_AWREADY;
|
||||
input [31:0]S_AXI_WDATA;
|
||||
input [3:0]S_AXI_WSTRB;
|
||||
input S_AXI_WVALID;
|
||||
output S_AXI_WREADY;
|
||||
output [1:0]S_AXI_BRESP;
|
||||
output S_AXI_BVALID;
|
||||
input S_AXI_BREADY;
|
||||
input [3:0]S_AXI_ARADDR;
|
||||
input [2:0]S_AXI_ARPROT;
|
||||
input S_AXI_ARVALID;
|
||||
output S_AXI_ARREADY;
|
||||
output [31:0]S_AXI_RDATA;
|
||||
output [1:0]S_AXI_RRESP;
|
||||
output S_AXI_RVALID;
|
||||
input S_AXI_RREADY;
|
||||
endmodule
|
||||
@ -0,0 +1,51 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Tue May 28 16:48:33 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.vhdl
|
||||
-- Design : design_1_axi_pwm_v1_0_S00_AXI_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
pwm_out : out STD_LOGIC;
|
||||
S_AXI_ACLK : in STD_LOGIC;
|
||||
S_AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "pwm_out,S_AXI_ACLK,S_AXI_ARESETN,S_AXI_AWADDR[3:0],S_AXI_AWPROT[2:0],S_AXI_AWVALID,S_AXI_AWREADY,S_AXI_WDATA[31:0],S_AXI_WSTRB[3:0],S_AXI_WVALID,S_AXI_WREADY,S_AXI_BRESP[1:0],S_AXI_BVALID,S_AXI_BREADY,S_AXI_ARADDR[3:0],S_AXI_ARPROT[2:0],S_AXI_ARVALID,S_AXI_ARREADY,S_AXI_RDATA[31:0],S_AXI_RRESP[1:0],S_AXI_RVALID,S_AXI_RREADY";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_pwm_v1_0_S00_AXI,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,39 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>4ce5ed9715abea11</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>design_1_vlg_design_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="vlg_design" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.I_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CNT_MAX">5000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CNT_MAX_PERCENT">300</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_vlg_design_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">4ce5ed9715abea11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">14fae0ee</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">53</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
@ -0,0 +1,157 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 19 11:00:53 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_sim_netlist.v
|
||||
// Design : design_1_vlg_design_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_vlg_design_0_0,vlg_design,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* X_CORE_INFO = "vlg_design,Vivado 2022.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(i_clk,
|
||||
i_rst_n,
|
||||
i_en,
|
||||
o_vld,
|
||||
o_pwm);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_rst_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input i_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input i_rst_n;
|
||||
input i_en;
|
||||
output o_vld;
|
||||
output o_pwm;
|
||||
|
||||
wire \<const0> ;
|
||||
wire i_clk;
|
||||
wire i_en;
|
||||
wire i_rst_n;
|
||||
wire o_pwm;
|
||||
|
||||
assign o_vld = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design inst
|
||||
(.i_clk(i_clk),
|
||||
.i_en(i_en),
|
||||
.i_rst_n(i_rst_n),
|
||||
.o_pwm(o_pwm));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design
|
||||
(o_pwm,
|
||||
i_clk,
|
||||
i_rst_n,
|
||||
i_en);
|
||||
output o_pwm;
|
||||
input i_clk;
|
||||
input i_rst_n;
|
||||
input i_en;
|
||||
|
||||
wire i_clk;
|
||||
wire i_en;
|
||||
wire i_rst_n;
|
||||
wire o_pwm;
|
||||
wire o_pwm_i_1_n_0;
|
||||
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
o_pwm_i_1
|
||||
(.I0(i_rst_n),
|
||||
.I1(i_en),
|
||||
.O(o_pwm_i_1_n_0));
|
||||
FDRE o_pwm_reg
|
||||
(.C(i_clk),
|
||||
.CE(1'b1),
|
||||
.D(o_pwm_i_1_n_0),
|
||||
.Q(o_pwm),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@ -0,0 +1,92 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 19 11:00:53 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_vlg_design_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design is
|
||||
port (
|
||||
o_pwm : out STD_LOGIC;
|
||||
i_clk : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC
|
||||
);
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design is
|
||||
signal o_pwm_i_1_n_0 : STD_LOGIC;
|
||||
begin
|
||||
o_pwm_i_1: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"8"
|
||||
)
|
||||
port map (
|
||||
I0 => i_rst_n,
|
||||
I1 => i_en,
|
||||
O => o_pwm_i_1_n_0
|
||||
);
|
||||
o_pwm_reg: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => i_clk,
|
||||
CE => '1',
|
||||
D => o_pwm_i_1_n_0,
|
||||
Q => o_pwm,
|
||||
R => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
i_clk : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
o_vld : out STD_LOGIC;
|
||||
o_pwm : out STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_vlg_design_0_0,vlg_design,{}";
|
||||
attribute DowngradeIPIdentifiedWarnings : string;
|
||||
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute IP_DEFINITION_SOURCE : string;
|
||||
attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "module_ref";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vlg_design,Vivado 2022.2";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i_clk : signal is "xilinx.com:signal:clock:1.0 i_clk CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of i_clk : signal is "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_rst_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of i_rst_n : signal is "xilinx.com:signal:reset:1.0 i_rst_n RST";
|
||||
attribute X_INTERFACE_PARAMETER of i_rst_n : signal is "XIL_INTERFACENAME i_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
begin
|
||||
o_vld <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vlg_design
|
||||
port map (
|
||||
i_clk => i_clk,
|
||||
i_en => i_en,
|
||||
i_rst_n => i_rst_n,
|
||||
o_pwm => o_pwm
|
||||
);
|
||||
end STRUCTURE;
|
||||
@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 19 11:00:53 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_stub.v
|
||||
// Design : design_1_vlg_design_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vlg_design,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(i_clk, i_rst_n, i_en, o_vld, o_pwm)
|
||||
/* synthesis syn_black_box black_box_pad_pin="i_clk,i_rst_n,i_en,o_vld,o_pwm" */;
|
||||
input i_clk;
|
||||
input i_rst_n;
|
||||
input i_en;
|
||||
output o_vld;
|
||||
output o_pwm;
|
||||
endmodule
|
||||
@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 19 11:00:53 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_vlg_design_0_0_stub.vhdl
|
||||
-- Design : design_1_vlg_design_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
i_clk : in STD_LOGIC;
|
||||
i_rst_n : in STD_LOGIC;
|
||||
i_en : in STD_LOGIC;
|
||||
o_vld : out STD_LOGIC;
|
||||
o_pwm : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "i_clk,i_rst_n,i_en,o_vld,o_pwm";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vlg_design,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
@ -0,0 +1,66 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>4f84a6a0cf5711dd</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>dbg_hub</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xsdbm" spirit:version="3.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCANID">76546592</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCAN_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BSCAN_MODE_WITH_CORE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BUILD_REVISION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CLK_INPUT_FREQ_HZ">300000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MAJOR_VER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MINOR_ALPHA_VER">97</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_MINOR_VER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_CORE_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DCLK_HAS_RESET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DIVCLK_DIVIDE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ENABLE_CLK_DIVIDER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_BSCANID_VEC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_INT_SIM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_STYLE">SUBCORE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MAJOR_VERSION">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MINOR_VERSION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BSCAN_MASTER_PORTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TWO_PRIM_MODE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USER_SCAN_CHAIN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USER_SCAN_CHAIN1">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BUFR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_EXT_BSCAN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_NUM_SLAVES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_PERIOD_FRC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XSDB_PERIOD_INT">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">dbg_hub</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">4f84a6a0cf5711dd</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">c7aff28e</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">57</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub.dcp
Normal file
BIN
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub.dcp
Normal file
Binary file not shown.
13628
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub_sim_netlist.v
Normal file
13628
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub_sim_netlist.v
Normal file
File diff suppressed because it is too large
Load Diff
18630
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub_sim_netlist.vhdl
Normal file
18630
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub_sim_netlist.vhdl
Normal file
File diff suppressed because it is too large
Load Diff
22
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub_stub.v
Normal file
22
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/dbg_hub_stub.v
Normal file
@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Sun May 19 03:11:04 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.v
|
||||
// Design : dbg_hub
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "xsdbm_v3_0_0_xsdbm,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sl_iport0_o, sl_oport0_i, clk)
|
||||
/* synthesis syn_black_box black_box_pad_pin="sl_iport0_o[36:0],sl_oport0_i[16:0],clk" */;
|
||||
output [36:0]sl_iport0_o;
|
||||
input [16:0]sl_oport0_i;
|
||||
input clk;
|
||||
endmodule
|
||||
@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Sun May 19 03:11:04 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_hub_stub.vhdl
|
||||
-- Design : dbg_hub
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
sl_iport0_o : out STD_LOGIC_VECTOR ( 36 downto 0 );
|
||||
sl_oport0_i : in STD_LOGIC_VECTOR ( 16 downto 0 );
|
||||
clk : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "sl_iport0_o[36:0],sl_oport0_i[16:0],clk";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "xsdbm_v3_0_0_xsdbm,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
2
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/stats.txt
Normal file
2
ax_dma.cache/ip/2022.2/4/f/4f84a6a0cf5711dd/stats.txt
Normal file
@ -0,0 +1,2 @@
|
||||
NumberHits:32
|
||||
Timestamp: Tue May 28 01:50:40 UTC 2024
|
||||
3903
ax_dma.cache/ip/2022.2/5/6/56ba640a64e41460/56ba640a64e41460.xci
Normal file
3903
ax_dma.cache/ip/2022.2/5/6/56ba640a64e41460/56ba640a64e41460.xci
Normal file
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -0,0 +1,68 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
// Date : Tue May 28 10:31:18 2024
|
||||
// Host : destop1 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_system_ila_0_0_stub.v
|
||||
// Design : design_1_system_ila_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z010iclg400-1L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "bd_f60c,Vivado 2022.2" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, SLOT_0_AXI_awid, SLOT_0_AXI_awaddr,
|
||||
SLOT_0_AXI_awlen, SLOT_0_AXI_awsize, SLOT_0_AXI_awburst, SLOT_0_AXI_awlock,
|
||||
SLOT_0_AXI_awcache, SLOT_0_AXI_awprot, SLOT_0_AXI_awqos, SLOT_0_AXI_awvalid,
|
||||
SLOT_0_AXI_awready, SLOT_0_AXI_wid, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, SLOT_0_AXI_wlast,
|
||||
SLOT_0_AXI_wvalid, SLOT_0_AXI_wready, SLOT_0_AXI_bid, SLOT_0_AXI_bresp,
|
||||
SLOT_0_AXI_bvalid, SLOT_0_AXI_bready, SLOT_0_AXI_arid, SLOT_0_AXI_araddr,
|
||||
SLOT_0_AXI_arlen, SLOT_0_AXI_arsize, SLOT_0_AXI_arburst, SLOT_0_AXI_arlock,
|
||||
SLOT_0_AXI_arcache, SLOT_0_AXI_arprot, SLOT_0_AXI_arqos, SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_arready, SLOT_0_AXI_rid, SLOT_0_AXI_rdata, SLOT_0_AXI_rresp, SLOT_0_AXI_rlast,
|
||||
SLOT_0_AXI_rvalid, SLOT_0_AXI_rready, resetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,SLOT_0_AXI_awid[11:0],SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awlen[3:0],SLOT_0_AXI_awsize[2:0],SLOT_0_AXI_awburst[1:0],SLOT_0_AXI_awlock[1:0],SLOT_0_AXI_awcache[3:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awqos[3:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wid[11:0],SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wlast,SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bid[11:0],SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_arid[11:0],SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arlen[3:0],SLOT_0_AXI_arsize[2:0],SLOT_0_AXI_arburst[1:0],SLOT_0_AXI_arlock[1:0],SLOT_0_AXI_arcache[3:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arqos[3:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rid[11:0],SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rlast,SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn" */;
|
||||
input clk;
|
||||
input [11:0]SLOT_0_AXI_awid;
|
||||
input [31:0]SLOT_0_AXI_awaddr;
|
||||
input [3:0]SLOT_0_AXI_awlen;
|
||||
input [2:0]SLOT_0_AXI_awsize;
|
||||
input [1:0]SLOT_0_AXI_awburst;
|
||||
input [1:0]SLOT_0_AXI_awlock;
|
||||
input [3:0]SLOT_0_AXI_awcache;
|
||||
input [2:0]SLOT_0_AXI_awprot;
|
||||
input [3:0]SLOT_0_AXI_awqos;
|
||||
input SLOT_0_AXI_awvalid;
|
||||
input SLOT_0_AXI_awready;
|
||||
input [11:0]SLOT_0_AXI_wid;
|
||||
input [31:0]SLOT_0_AXI_wdata;
|
||||
input [3:0]SLOT_0_AXI_wstrb;
|
||||
input SLOT_0_AXI_wlast;
|
||||
input SLOT_0_AXI_wvalid;
|
||||
input SLOT_0_AXI_wready;
|
||||
input [11:0]SLOT_0_AXI_bid;
|
||||
input [1:0]SLOT_0_AXI_bresp;
|
||||
input SLOT_0_AXI_bvalid;
|
||||
input SLOT_0_AXI_bready;
|
||||
input [11:0]SLOT_0_AXI_arid;
|
||||
input [31:0]SLOT_0_AXI_araddr;
|
||||
input [3:0]SLOT_0_AXI_arlen;
|
||||
input [2:0]SLOT_0_AXI_arsize;
|
||||
input [1:0]SLOT_0_AXI_arburst;
|
||||
input [1:0]SLOT_0_AXI_arlock;
|
||||
input [3:0]SLOT_0_AXI_arcache;
|
||||
input [2:0]SLOT_0_AXI_arprot;
|
||||
input [3:0]SLOT_0_AXI_arqos;
|
||||
input SLOT_0_AXI_arvalid;
|
||||
input SLOT_0_AXI_arready;
|
||||
input [11:0]SLOT_0_AXI_rid;
|
||||
input [31:0]SLOT_0_AXI_rdata;
|
||||
input [1:0]SLOT_0_AXI_rresp;
|
||||
input SLOT_0_AXI_rlast;
|
||||
input SLOT_0_AXI_rvalid;
|
||||
input SLOT_0_AXI_rready;
|
||||
input resetn;
|
||||
endmodule
|
||||
@ -0,0 +1,69 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
|
||||
-- Date : Tue May 28 10:31:18 2024
|
||||
-- Host : destop1 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_system_ila_0_0_stub.vhdl
|
||||
-- Design : design_1_system_ila_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z010iclg400-1L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
SLOT_0_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wlast : in STD_LOGIC;
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rlast : in STD_LOGIC;
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,SLOT_0_AXI_awid[11:0],SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awlen[3:0],SLOT_0_AXI_awsize[2:0],SLOT_0_AXI_awburst[1:0],SLOT_0_AXI_awlock[1:0],SLOT_0_AXI_awcache[3:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awqos[3:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wid[11:0],SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wlast,SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bid[11:0],SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_arid[11:0],SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arlen[3:0],SLOT_0_AXI_arsize[2:0],SLOT_0_AXI_arburst[1:0],SLOT_0_AXI_arlock[1:0],SLOT_0_AXI_arcache[3:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arqos[3:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rid[11:0],SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rlast,SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "bd_f60c,Vivado 2022.2";
|
||||
begin
|
||||
end;
|
||||
2
ax_dma.cache/ip/2022.2/5/6/56ba640a64e41460/stats.txt
Normal file
2
ax_dma.cache/ip/2022.2/5/6/56ba640a64e41460/stats.txt
Normal file
@ -0,0 +1,2 @@
|
||||
NumberHits:18
|
||||
Timestamp: Tue May 28 13:44:49 UTC 2024
|
||||
3146
ax_dma.cache/ip/2022.2/6/5/651880bbf50e545c/651880bbf50e545c.xci
Normal file
3146
ax_dma.cache/ip/2022.2/6/5/651880bbf50e545c/651880bbf50e545c.xci
Normal file
File diff suppressed because it is too large
Load Diff
BIN
ax_dma.cache/ip/2022.2/6/5/651880bbf50e545c/design_1_ila_0_0.dcp
Normal file
BIN
ax_dma.cache/ip/2022.2/6/5/651880bbf50e545c/design_1_ila_0_0.dcp
Normal file
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user