34 lines
4.1 KiB
Plaintext
34 lines
4.1 KiB
Plaintext
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/design_1/ip/design_1_ila_0_0/sim/design_1_ila_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_1_ila_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/design_1/ip/design_1_vlg_design_0_0/sim/design_1_vlg_design_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_1_vlg_design_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_1_processing_system7_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/sources_1/new/vlg_design.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module vlg_design
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module design_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/sources_1/new/axi_pwm_v1_0_S00_AXI.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module axi_pwm_v1_0_S00_AXI
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/test_axi_v1_0_bfm_1/ipshared/079a/hdl/test_axi_v1_0_M00_AXI.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module test_axi_v1_0_M00_AXI
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/test_axi_v1_0_bfm_1/ipshared/079a/hdl/test_axi_v1_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module test_axi_v1_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/test_axi_v1_0_bfm_1/ip/test_axi_v1_0_bfm_1_test_axi_0_0/sim/test_axi_v1_0_bfm_1_test_axi_0_0.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module test_axi_v1_0_bfm_1_test_axi_0_0
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/test_axi_v1_0_bfm_1/ip/test_axi_v1_0_bfm_1_slave_0_0/sim/test_axi_v1_0_bfm_1_slave_0_0_pkg.sv" into library xil_defaultlib
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/test_axi_v1_0_bfm_1/ip/test_axi_v1_0_bfm_1_slave_0_0/sim/test_axi_v1_0_bfm_1_slave_0_0.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module test_axi_v1_0_bfm_1_slave_0_0
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.ip_user_files/bd/test_axi_v1_0_bfm_1/sim/test_axi_v1_0_bfm_1.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module test_axi_v1_0_bfm_1
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/sources_1/imports/hdl/test_axi_v1_0_bfm_1_wrapper.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module test_axi_v1_0_bfm_1_wrapper
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/sim_1/new/testbench_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module testbench_top
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/sim_1/imports/bfm_design/test_axi_v1_0_tb.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module test_axi_v1_0_tb
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INFO: [VRFC 10-2263] Analyzing Verilog file "E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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