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axi_lite_pwm/ax_dma.sim/sim_1/synth/timing/xsim
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zcy f048762aaf first commit
2024-05-29 08:51:51 +08:00
..
xsim.dir first commit 2024-05-29 08:51:51 +08:00
compile.bat first commit 2024-05-29 08:51:51 +08:00
elaborate.bat first commit 2024-05-29 08:51:51 +08:00
elaborate.log first commit 2024-05-29 08:51:51 +08:00
simulate.bat first commit 2024-05-29 08:51:51 +08:00
simulate.log first commit 2024-05-29 08:51:51 +08:00
testbench_top_time_synth.sdf first commit 2024-05-29 08:51:51 +08:00
testbench_top_time_synth.v first commit 2024-05-29 08:51:51 +08:00
testbench_top_time_synth.wdb first commit 2024-05-29 08:51:51 +08:00
testbench_top_vlog.prj first commit 2024-05-29 08:51:51 +08:00
testbench_top.tcl first commit 2024-05-29 08:51:51 +08:00
xelab.pb first commit 2024-05-29 08:51:51 +08:00
xsim.ini first commit 2024-05-29 08:51:51 +08:00
xsim.ini.bak first commit 2024-05-29 08:51:51 +08:00
xvlog.log first commit 2024-05-29 08:51:51 +08:00
xvlog.pb first commit 2024-05-29 08:51:51 +08:00