403 lines
61 KiB
Plaintext
403 lines
61 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2022.2 (64-bit)
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# SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022
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# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
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# Start of session at: Tue May 28 21:46:40 2024
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# Process ID: 377636
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# Current directory: E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1
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# Command line: vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl
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# Log file: E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/design_1_wrapper.vds
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# Journal file: E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1\vivado.jou
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# Running On: destop1, OS: Windows, CPU Frequency: 3600 MHz, CPU Physical cores: 12, Host memory: 17087 MB
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#-----------------------------------------------------------
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source design_1_wrapper.tcl -notrace
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create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 374.148 ; gain = 65.074
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/zybo_base_system/source/vivado/hw/ip_repo/test_axi_1_0'.
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INFO: [IP_Flow 19-1700] Loaded user IP repository 'e:/zybo_base_system/source/vivado/hw/ip_repo/myip_1_0'.
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'.
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add_files: Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 469.602 ; gain = 70.598
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Command: read_checkpoint -auto_incremental -incremental E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/utils_1/imports/synth_1/axi_pwm_v1_0_S00_AXI.dcp
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INFO: [Vivado 12-5825] Read reference checkpoint from E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/utils_1/imports/synth_1/axi_pwm_v1_0_S00_AXI.dcp for incremental synthesis
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INFO: [Vivado 12-7989] Please ensure there are no constraint changes
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Command: synth_design -top design_1_wrapper -part xc7z010iclg400-1L
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010i'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010i'
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INFO: [Device 21-403] Loading part xc7z010iclg400-1L
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INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
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INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
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INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
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INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
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INFO: [Synth 8-7075] Helper process launched with PID 388508
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INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1269.375 ; gain = 415.762
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12]
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INFO: [Synth 8-6157] synthesizing module 'design_1' [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:12]
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INFO: [Synth 8-6157] synthesizing module 'design_1_axi_pwm_v1_0_S00_AXI_0_0' [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_axi_pwm_v1_0_S00_AXI_0_0' (0#1) [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_axi_pwm_v1_0_S00_AXI_0_0_stub.v:5]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:118]
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INFO: [Synth 8-6157] synthesizing module 'design_1_ila_0_0' [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_ila_0_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_ila_0_0' (0#1) [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_ila_0_0_stub.v:5]
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INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_processing_system7_0_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (0#1) [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_processing_system7_0_0_stub.v:5]
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INFO: [Synth 8-6157] synthesizing module 'design_1_ps7_0_axi_periph_0' [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:284]
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INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_UYSKKA' [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:599]
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INFO: [Synth 8-6157] synthesizing module 'design_1_auto_pc_0' [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_auto_pc_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_auto_pc_0' (0#1) [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_auto_pc_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_UYSKKA' (0#1) [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:599]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_ps7_0_axi_periph_0' (0#1) [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:284]
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INFO: [Synth 8-6157] synthesizing module 'design_1_rst_ps7_0_49M_0' [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_rst_ps7_0_49M_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_rst_ps7_0_49M_0' (0#1) [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_rst_ps7_0_49M_0_stub.v:5]
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WARNING: [Synth 8-7071] port 'mb_reset' of module 'design_1_rst_ps7_0_49M_0' is unconnected for instance 'rst_ps7_0_49M' [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:234]
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WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'design_1_rst_ps7_0_49M_0' is unconnected for instance 'rst_ps7_0_49M' [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:234]
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WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'design_1_rst_ps7_0_49M_0' is unconnected for instance 'rst_ps7_0_49M' [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:234]
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WARNING: [Synth 8-7071] port 'interconnect_aresetn' of module 'design_1_rst_ps7_0_49M_0' is unconnected for instance 'rst_ps7_0_49M' [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:234]
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WARNING: [Synth 8-7023] instance 'rst_ps7_0_49M' of module 'design_1_rst_ps7_0_49M_0' has 10 connections declared, but only 6 given [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:234]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:241]
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INFO: [Synth 8-6157] synthesizing module 'design_1_system_ila_0_0' [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_system_ila_0_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_system_ila_0_0' (0#1) [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/.Xil/Vivado-377636-destop1/realtime/design_1_system_ila_0_0_stub.v:5]
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INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:12]
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INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:12]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'axi_pwm_v1_0_S00_AXI_0'. This will prevent further optimization [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:94]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ila_0'. This will prevent further optimization [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:118]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'design_1_i'. This will prevent further optimization [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:30]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'rst_ps7_0_49M'. This will prevent further optimization [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:234]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'system_ila_0'. This will prevent further optimization [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:241]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'ps7_0_axi_periph'. This will prevent further optimization [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/synth/design_1.v:170]
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WARNING: [Synth 8-7129] Port M_ACLK in module s00_couplers_imp_UYSKKA is either unconnected or has no load
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WARNING: [Synth 8-7129] Port M_ARESETN in module s00_couplers_imp_UYSKKA is either unconnected or has no load
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WARNING: [Synth 8-7129] Port ACLK in module design_1_ps7_0_axi_periph_0 is either unconnected or has no load
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WARNING: [Synth 8-7129] Port ARESETN in module design_1_ps7_0_axi_periph_0 is either unconnected or has no load
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1363.016 ; gain = 509.402
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1363.016 ; gain = 509.402
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1363.016 ; gain = 509.402
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---------------------------------------------------------------------------------
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1363.016 ; gain = 0.000
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Processing XDC Constraints
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Initializing timing engine
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Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0/design_1_ila_0_0_in_context.xdc] for cell 'design_1_i/ila_0'
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Finished Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_ila_0_0/design_1_ila_0_0/design_1_ila_0_0_in_context.xdc] for cell 'design_1_i/ila_0'
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Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0'
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Finished Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0'
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Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0/design_1_auto_pc_0_in_context.xdc] for cell 'design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc'
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Finished Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0/design_1_auto_pc_0_in_context.xdc] for cell 'design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc'
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Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_49M_0/design_1_rst_ps7_0_49M_0/design_1_rst_ps7_0_49M_0_in_context.xdc] for cell 'design_1_i/rst_ps7_0_49M'
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Finished Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_49M_0/design_1_rst_ps7_0_49M_0/design_1_rst_ps7_0_49M_0_in_context.xdc] for cell 'design_1_i/rst_ps7_0_49M'
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Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0/design_1_system_ila_0_0_in_context.xdc] for cell 'design_1_i/system_ila_0'
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Finished Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0/design_1_system_ila_0_0_in_context.xdc] for cell 'design_1_i/system_ila_0'
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Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_axi_pwm_v1_0_S00_AXI_0_0/design_1_axi_pwm_v1_0_S00_AXI_0_0/design_1_axi_pwm_v1_0_S00_AXI_0_0_in_context.xdc] for cell 'design_1_i/axi_pwm_v1_0_S00_AXI_0'
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Finished Parsing XDC File [e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_axi_pwm_v1_0_S00_AXI_0_0/design_1_axi_pwm_v1_0_S00_AXI_0_0/design_1_axi_pwm_v1_0_S00_AXI_0_0_in_context.xdc] for cell 'design_1_i/axi_pwm_v1_0_S00_AXI_0'
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Parsing XDC File [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/constrs_1/new/io.xdc]
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Finished Parsing XDC File [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/constrs_1/new/io.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.srcs/constrs_1/new/io.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/dont_touch.xdc]
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Finished Parsing XDC File [E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/dont_touch.xdc]
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Completed Processing XDC Constraints
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1374.938 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1374.938 ; gain = 0.000
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INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
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INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
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INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [C:/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:21 . Memory (MB): peak = 1374.938 ; gain = 521.324
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7z010iclg400-1L
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:21 . Memory (MB): peak = 1374.938 ; gain = 521.324
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 2).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 3).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 4).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 5).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 6).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 7).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 8).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 9).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 10).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 11).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 12).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 13).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 14).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 15).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 16).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 17).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 18).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 19).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 20).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 21).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 22).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 23).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 24).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 25).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 26).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 27).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 28).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 29).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 30).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 31).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 32).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 33).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 34).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 35).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 36).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 37).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 38).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 39).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 40).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 41).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 42).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 43).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 44).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 45).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 46).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 47).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 48).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 49).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 50).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 51).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 52).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 53).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 54).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 55).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 56).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 57).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 58).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 59).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 60).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 61).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 62).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 63).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 64).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 65).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 66).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 67).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 68).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 69).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 70).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 71).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 72).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 73).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 74).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 75).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 76).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 77).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 78).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 79).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 80).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 81).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 82).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 83).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 84).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 85).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 86).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 87).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 88).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 89).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 90).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 91).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 92).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 93).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 94).
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|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 95).
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|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 96).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 97).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 98).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 99).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 100).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 101).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 102).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 103).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 104).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 105).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 106).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 107).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 108).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 109).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 110).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 111).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 112).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 113).
|
|
Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 114).
|
|
Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file e:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 115).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/ila_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/processing_system7_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/ps7_0_axi_periph. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/rst_ps7_0_49M. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/system_ila_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/axi_pwm_v1_0_S00_AXI_0. (constraint file auto generated constraint).
|
|
---------------------------------------------------------------------------------
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:22 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:22 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Detailed RTL Component Info :
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 80 (col length:40)
|
|
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
|
WARNING: [Synth 8-7129] Port ACLK in module design_1_ps7_0_axi_periph_0 is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port ARESETN in module design_1_ps7_0_axi_periph_0 is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port M00_ACLK in module design_1_ps7_0_axi_periph_0 is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port M00_ARESETN in module design_1_ps7_0_axi_periph_0 is either unconnected or has no load
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:24 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Applying XDC Timing Constraints
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:31 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:31 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:31 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+------+----------------------------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+------+----------------------------------+----------+
|
|
|1 |design_1_auto_pc_0 | 1|
|
|
|2 |design_1_axi_pwm_v1_0_S00_AXI_0_0 | 1|
|
|
|3 |design_1_ila_0_0 | 1|
|
|
|4 |design_1_processing_system7_0_0 | 1|
|
|
|5 |design_1_rst_ps7_0_49M_0 | 1|
|
|
|6 |design_1_system_ila_0_0 | 1|
|
|
+------+----------------------------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+--------------------------------+------+
|
|
| |Cell |Count |
|
|
+------+--------------------------------+------+
|
|
|1 |design_1_auto_pc | 1|
|
|
|2 |design_1_axi_pwm_v1_0_S00_AXI_0 | 1|
|
|
|3 |design_1_ila_0 | 1|
|
|
|4 |design_1_processing_system7_0 | 1|
|
|
|5 |design_1_rst_ps7_0_49M | 1|
|
|
|6 |design_1_system_ila_0 | 1|
|
|
|7 |IBUF | 1|
|
|
+------+--------------------------------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:35 . Memory (MB): peak = 1374.938 ; gain = 509.402
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:38 . Memory (MB): peak = 1374.938 ; gain = 521.324
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1385.973 ; gain = 0.000
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1391.602 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Synth Design complete, checksum: 946fe278
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INFO: [Common 17-83] Releasing license: Synthesis
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51 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
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synth_design completed successfully
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synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:46 . Memory (MB): peak = 1391.602 ; gain = 913.926
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INFO: [Common 17-1381] The checkpoint 'E:/zybo_base_system/source/vivado/hw/ax_dma/ax_dma.runs/synth_1/design_1_wrapper.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb
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INFO: [Common 17-206] Exiting Vivado at Tue May 28 21:47:47 2024...
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