Fixed DAC overflow, added UHD args and clock source

This commit is contained in:
madengr 2018-01-13 15:01:59 -06:00
parent 27d747039b
commit 4d11c06949

View File

@ -20,16 +20,11 @@ class top_block(gr.top_block):
##################################################
# Blocks
##################################################
self.uhd_usrp_sink = uhd.usrp_sink(
",".join(("", "")),
uhd.stream_args(
cpu_format="fc32",
channels=range(1),
),
)
self.uhd_usrp_sink = uhd.usrp_sink(options.args, uhd.io_type_t.COMPLEX_FLOAT32, 1)
self.uhd_usrp_sink.set_samp_rate(options.sample_rate)
self.uhd_usrp_sink.set_center_freq(options.frequency, 0)
self.uhd_usrp_sink.set_gain(options.gain, 0)
self.uhd_usrp_sink.set_clock_source(options.clock_source)
if options.bits == 16:
# a file source for the file generated by the gps-sdr-sim
@ -55,7 +50,13 @@ class top_block(gr.top_block):
self.connect((self.blocks_file_source, 0), (self.blocks_char_to_short, 0))
self.connect((self.blocks_char_to_short, 0), (self.blocks_interleaved_short_to_complex, 0))
self.connect((self.blocks_interleaved_short_to_complex, 0), (self.uhd_usrp_sink, 0))
# scale complex values to within +/- 1.0 so don't overflow USRP DAC
# scale of 1.0/2**11 will scale it to +/- 0.5
self.blocks_multiply_const = blocks.multiply_const_vcc((1.0/2**11, ))
# establish the connections
self.connect((self.blocks_interleaved_short_to_complex, 0), (self.blocks_multiply_const, 0))
self.connect((self.blocks_multiply_const, 0), (self.uhd_usrp_sink, 0))
def get_options():
parser = OptionParser(option_class=eng_option)
@ -71,6 +72,11 @@ def get_options():
help="set output file name [default=gpssim.bin]")
parser.add_option("-b", "--bits", type="eng_float", default=16,
help="set size of every sample [default=16]")
parser.add_option("-a", "--args", type="string", default="",
help="set UHD arguments [default='']")
parser.add_option("-c", "--clock_source", type="string", default="internal",
help="set clock source [default='internal']")
(options, args) = parser.parse_args()
if len(args) != 0: