388 lines
12 KiB
Plaintext
388 lines
12 KiB
Plaintext
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*$
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* TLV354
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*************************************************************************************************
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* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.
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*************************************************************************************************
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** This model is designed as an aid for customers of Texas Instruments.
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** TI and its licensor's and suppliers make no warranties, either expressed
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** or implied, with respect to this model, including the warranties of
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** merchantability or fitness for a particular purpose. The model is
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** provided solely on an "as is" basis. The entire risk as to its quality
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** and performance is with the customer
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*************************************************************************************************
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*
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* This model is subject to change without notice. Texas Instruments
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* Incorporated is not responsible for updating this model.
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*
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*************************************************************************************************
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*
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** Released by: Online Design Tools, Texas Instruments Inc.
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* Part: TLV354
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* Date: 13FEB2019
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* Model Type: Generic (suitable for all analysis types)
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* EVM Order Number: N/A
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* EVM Users Guide: N/A
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* Datasheet: SBOS756 -OCTOBER 2016
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* Created with Green-Williams-Lis Op Amp Macro-model Architecture
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*
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* Model Version: Final 1.2
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*
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*****************************************************************************
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*
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* Updates:
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*
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* Final 1.2
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* Updated with unique subckt name,Current Noise, Vos drift and edits in claw block
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*
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*
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* Final 1.1
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* Release to Web.
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*
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****************************************************************************
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* Model Usage Notes:
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* 1. The following parameters are modeled:
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* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)
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* UNITY GAIN BANDWIDTH (GBW)
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* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)
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* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)
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* DIFFERENTIAL INPUT IMPEDANCE (Zid)
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* COMMON-MODE INPUT IMPEDANCE (Zic)
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* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)
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* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)
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* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)
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* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)
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* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)
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* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
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* QUIESCENT CURRENT (Iq)
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* SETTLING TIME VS. CAPACITIVE LOAD (ts)
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* SLEW RATE (SR)
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* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD
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* LARGE SIGNAL RESPONSE
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* OVERLOAD RECOVERY TIME (tor)
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* INPUT BIAS CURRENT (Ib)
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* INPUT OFFSET CURRENT (Ios)
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* INPUT OFFSET VOLTAGE (Vos)
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* INPUT OFFSET VOLTAGE VS. TEMPERATURE (VOS DRIFT)
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* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
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* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)
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* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)
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******************************************************
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.subckt TLV354 IN+ IN- VCC VEE OUT
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******************************************************
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* MODEL DEFINITIONS:
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.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=100e-3 Voff=0)
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.model R_NOISELESS RES(T_ABS=-273.15)
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.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)
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.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)
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******************************************************
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XV_OS VOS N037 VOS_DRIFT_TLV354
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R1 N036 CMR R_NOISELESS 1e-3
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R2 FB- VOS- R_NOISELESS 1e-3
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R3 N054 0 R_NOISELESS 1e12
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C1 N054 0 1
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R4 VCC_B N053 R_NOISELESS 1e-3
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C2 N053 0 1e-15
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C3 N055 0 1e-15
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R5 N055 VEE_B R_NOISELESS 1e-3
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G_PSR N036 PSR N010 N009 1e-3
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R6 MID N039 R_NOISELESS 1e12
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VCM_MIN N040 VEE_B -0.1
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R7 N040 MID R_NOISELESS 1e12
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VCM_MAX N039 VCC_B +0.1
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XVCM_CLAMP PSR MID N038 MID N039 N040 VCCS_EXT_LIM_TLV354
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R8 N038 MID R_NOISELESS 1
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C4 VCM_CLAMP MID 1e-15
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R9 N038 VCM_CLAMP R_NOISELESS 1e-3
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V4 N052 OUT 0
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R10 MID N044 R_NOISELESS 1e12
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R11 MID N045 R_NOISELESS 1e12
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XIQp VIMON MID VCC MID VCCS_LIM_IQ_TLV354
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XIQn MID VIMON VEE MID VCCS_LIM_IQ_TLV354
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R12 VCC_B N013 R_NOISELESS 1e3
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R13 N026 VEE_B R_NOISELESS 1e3
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XCLAWp VIMON MID N013 VCC_B VCCS_LIM_CLAWp_TLV354
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XCLAWn MID VIMON VEE_B N026 VCCS_LIM_CLAWn_TLV354
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R14 VEE_CLP MID R_NOISELESS 1e3
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R15 MID VCC_CLP R_NOISELESS 1e3
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R16 N014 N013 R_NOISELESS 1e-3
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R17 N027 N026 R_NOISELESS 1e-3
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C5 MID N014 1e-15
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C6 N027 MID 1e-15
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R18 VOUT_S N045 R_NOISELESS 100
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C7 VOUT_S MID 1e-12
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G2 MID VCC_CLP N014 MID 1e-3
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G3 MID VEE_CLP N027 MID 1e-3
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XCL_AMP N008 N034 VIMON MID N017 N024 CLAMP_AMP_LO_TLV354
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V_ISCp N008 MID 150
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V_ISCn N034 MID -165
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XOL_SENSE_TLV354 MID N057 OLN OLP OL_SENSE_TLV354
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R19 N034 MID R_NOISELESS 1e9
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R20 N024 MID R_NOISELESS 1
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C8 N025 MID 1e-15
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R21 MID N017 R_NOISELESS 1
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R22 MID N008 R_NOISELESS 1e9
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C9 MID N018 1e-15
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XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N015 N022 CLAMP_AMP_LO_TLV354
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R23 VEE_CLP MID R_NOISELESS 1e9
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R24 N022 MID R_NOISELESS 1
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C10 N023 MID 1e-15
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R25 MID N015 R_NOISELESS 1
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R26 MID VCC_CLP R_NOISELESS 1e9
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C11 MID N016 1e-15
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XCL_SRC N018 N025 CL_CLAMP MID VCCS_LIM_4_TLV354
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XCLAW_SRC N016 N023 CLAW_CLAMP MID VCCS_LIM_3_TLV354
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R27 N015 N016 R_NOISELESS 1e-3
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R28 N023 N022 R_NOISELESS 1e-3
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R29 N017 N018 R_NOISELESS 1e-3
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R30 N025 N024 R_NOISELESS 1e-3
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R31 N057 MID R_NOISELESS 1
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R32 N057 SW_OL R_NOISELESS 100
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C12 SW_OL MID 1e-12
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R33 VIMON N044 R_NOISELESS 100
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C13 VIMON MID 1e-12
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C_DIFF N011 VOS- 2e-12
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C_CMn VOS- MID 2e-12
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C_CMp MID N011 2e-12
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I_Q VCC VEE 5.2e-3
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I_B PSR MID 3e-12
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I_OS FB- MID 2e-12
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R36 N032 MID R_NOISELESS 1
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R37 N035 MID R_NOISELESS 1e9
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R38 MID N020 R_NOISELESS 1
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R39 MID N012 R_NOISELESS 1e9
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XGR_AMP N012 N035 N019 MID N020 N032 CLAMP_AMP_HI_TLV354
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XGR_SRC N021 N033 CLAMP MID VCCS_LIM_GR_TLV354
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C17 MID N021 1e-15
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C18 N033 MID 1e-15
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V_GRn N035 MID -120
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V_GRp N012 MID 110
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R40 N020 N021 R_NOISELESS 1e-3
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R41 N033 N032 R_NOISELESS 1e-3
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R42 VSENSE N019 R_NOISELESS 1e-3
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C19 MID N019 1e-15
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R43 MID VSENSE R_NOISELESS 1e3
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G_CMR VOS CMR N007 MID 1e-3
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G8 MID CLAW_CLAMP N041 MID 1e-3
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R45 MID CLAW_CLAMP R_NOISELESS 1e3
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G9 MID CL_CLAMP CLAW_CLAMP MID 1e-3
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R46 MID CL_CLAMP R_NOISELESS 1e3
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R47 N050 VCLP R_NOISELESS 100
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C24 MID VCLP 1e-12
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E4 N050 MID CL_CLAMP MID 1
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E5 N045 MID OUT MID 1
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H1 N044 MID V4 1e3
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S1 N043 N042 SW_OL MID OL_SW
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R52 MID N011 R_NOISELESS 1T
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R53 VOS- MID R_NOISELESS 1T
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R_CMR CMR VOS R_NOISELESS 1e3
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R59 N053 N054 R_NOISELESS 1e6
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R60 N054 N055 R_NOISELESS 1e6
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R_PSR PSR N036 R_NOISELESS 1e3
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G15 MID VSENSE CLAMP MID 1e-3
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E6 VD2 MID N031 MID 1
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V_ORp N031 VCLP 0.65
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V_ORn N028 VCLP -0.65
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E7 VD1 MID N028 MID 1
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V11 N029 VD1 0
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V12 N030 VD2 0
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H2 OLN MID V11 -1
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H3 OLP MID V12 1
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S2 VCC IN- IN- VCC ESD_SW
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S3 VCC IN+ IN+ VCC ESD_SW
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S4 IN- VEE VEE IN- ESD_SW
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S5 IN+ VEE VEE IN+ ESD_SW
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S6 VCC OUT OUT VCC ESD_SW
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S7 OUT VEE VEE OUT ESD_SW
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E1 MID 0 N054 0 1
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G16 0 VCC_B VCC 0 1
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G17 0 VEE_B VEE 0 1
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R88 VCC_B 0 R_NOISELESS 1
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R89 VEE_B 0 R_NOISELESS 1
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S8 N030 CLAMP CLAMP N030 OR_SW
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S9 CLAMP N029 N029 CLAMP OR_SW
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XVCCS_LIM_1_TLV354 VCM_CLAMP FB- MID GAIN_1 VCCS_LIM_1_TLV354
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XVCCS_LIM_2_TLV354 GAIN_1 MID MID CLAMP VCCS_LIM_2_TLV354
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R44 GAIN_1 MID R_NOISELESS 1e6
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R58 CLAMP MID R_NOISELESS 1e6
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C20 CLAMP MID 6.5e-10
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R34 N011 IN+ R_NOISELESS 1e-3
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R35 VOS- IN- R_NOISELESS 1e-3
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R48 MID N041 R_NOISELESS 1e6
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G1 MID N041 VSENSE MID 1e-6
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C14 N041 MID 7.23e-16
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Xe_n N037 N011 VNSE_TLV354
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C22 N002 N001 4.547e-15
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G_adjust1 MID N001 N011 MID 3.985e-2
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Rsrc1 N001 MID R_NOISELESS 1
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R56 N002 MID R_NOISELESS 2.063e5
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R57 N002 N001 R_NOISELESS 1e8
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Rsrc2 N007 MID R_NOISELESS 1
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G5 MID N007 N002 MID 1
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C23 N005 N006 1.36e-14
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G_adjust2 MID N006 VCC_B MID 8.834e-1
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Rsrc3 N006 MID R_NOISELESS 1
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R61 N005 MID R_NOISELESS 4.256e4
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R62 N005 N006 R_NOISELESS 1e8
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G6 MID N010 N005 MID 1
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Rsrc4 N010 MID R_NOISELESS 1
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C25 N004 N003 6.366e-14
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R63 N004 MID R_NOISELESS 2.501e4
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R64 N004 N003 R_NOISELESS 1e8
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G7 MID N009 N004 MID 1
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Rsrc6 N009 MID R_NOISELESS 1
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G10 MID N003 VEE_B MID 6.64e-1
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R65 N003 MID R_NOISELESS 1
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Rx1 N052 N051 R_NOISELESS 6.67e4
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Rdummy1 N052 MID R_NOISELESS 6.67e3
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G_Zo MID N042 CL_CLAMP N052 89
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Rdc N042 MID R_NOISELESS 1
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R69 N043 N042 R_NOISELESS 10e3
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R70 MID N043 R_NOISELESS 4.65e2
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G12 MID N046 N043 MID 22.5
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R71 N046 MID R_NOISELESS 1
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C28 N043 N042 6e-8
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R75 N047 N046 R_NOISELESS 2.3e4
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R76 N056 N047 R_NOISELESS 10e3
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C29 MID N056 4.823e-14
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G14 MID N048 N047 MID 1
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R77 N048 MID R_NOISELESS 1
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R78 N049 N048 R_NOISELESS 10e3
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R79 MID N049 R_NOISELESS 3.311e1
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C30 N049 N048 4.823e-14
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XU1 N049 MID N051 MID VCVS_LIM_1_TLV354
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Xi_np N037 MID FEMT_TLV354
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Xi_nn VOS- MID FEMT_TLV354
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.ends TLV354
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*
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.SUBCKT VOS_DRIFT_TLV354 VOS+ VOS-
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.PARAM DC = 645e-6
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.PARAM POL = 1
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.PARAM DRIFT = 4.5E-06
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E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
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.ENDS
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*
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.subckt CLAMP_AMP_HI_TLV354 VC+ VC- VIN COM VO+ VO-
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.param G=10
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GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
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GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
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.ends CLAMP_AMP_HI_TLV354
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*
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.subckt OL_SENSE_TLV354 1 2 3 4
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GSW+ 1 2 Value = {IF((V(3,1)>1e-3 | V(4,1)>1e-3),1,0)}
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.ends OL_SENSE_TLV354
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*
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.subckt FEMT_TLV354 1 2
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.param NVRF=50
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.param RNVF={1.184*PWR(NVRF,2)}
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E1 3 0 5 0 10
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R1 5 0 {RNVF}
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R2 5 0 {RNVF}
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G1 1 2 3 0 1e-6
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.ends FEMT_TLV354
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*
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.subckt VCCS_EXT_LIM_TLV354 VIN+ VIN- IOUT- IOUT+ VP+ VP-
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.param Gain = 1
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G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
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.ends VCCS_EXT_LIM_TLV354
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*
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.subckt VCCS_LIM_1_TLV354 VC+ VC- IOUT+ IOUT-
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.param Gain = 1e-4
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.param Ipos = .5
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.param Ineg = -.5
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G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
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.ends VCCS_LIM_1_TLV354
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*
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.subckt VCCS_LIM_2_TLV354 VC+ VC- IOUT+ IOUT-
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.param Gain = 4.71e-3
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.param Ipos = 99.6e-3
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.param Ineg = -99.6e-3
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G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
|
||
|
|
.ends VCCS_LIM_2_TLV354
|
||
|
|
*
|
||
|
|
.subckt VCCS_LIM_3_TLV354 VC+ VC- IOUT+ IOUT-
|
||
|
|
.param Gain = 1
|
||
|
|
.param Ipos = 220e-3
|
||
|
|
.param Ineg = -240e-3
|
||
|
|
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
|
||
|
|
.ends VCCS_LIM_3_TLV354
|
||
|
|
*
|
||
|
|
.subckt VCCS_LIM_4_TLV354 VC+ VC- IOUT+ IOUT-
|
||
|
|
.param Gain = 1
|
||
|
|
.param Ipos = 230e-3
|
||
|
|
.param Ineg = -250e-3
|
||
|
|
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
|
||
|
|
.ends VCCS_LIM_4_TLV354
|
||
|
|
*
|
||
|
|
.subckt VCCS_LIM_CLAWn_TLV354 VC+ VC- IOUT+ IOUT-
|
||
|
|
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
|
||
|
|
+(0, 1.0064e-4)
|
||
|
|
+(10, 1.28e-4)
|
||
|
|
+(20, 2.16e-4)
|
||
|
|
+(50, 5.31e-4)
|
||
|
|
+(90.6, 9.91e-4)
|
||
|
|
+(120, 1.39e-3)
|
||
|
|
+(140, 1.7e-3)
|
||
|
|
+(163.7, 2.16e-3)
|
||
|
|
.ends VCCS_LIM_CLAWn_TLV354
|
||
|
|
*
|
||
|
|
.subckt VCCS_LIM_IQ_TLV354 VC+ VC- IOUT+ IOUT-
|
||
|
|
.param Gain = 1e-3
|
||
|
|
G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )}
|
||
|
|
.ends VCCS_LIM_IQ_TLV354
|
||
|
|
*
|
||
|
|
.subckt VCVS_LIM_1_TLV354 VC+ VC- VOUT+ VOUT-
|
||
|
|
.param Gain = 3.03e2
|
||
|
|
.param Vpos = 20.5e3
|
||
|
|
.param Vneg = -22.5e3
|
||
|
|
E1 VOUT+ VOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Vneg,Vpos)}
|
||
|
|
.ends VCVS_LIM_1_TLV354
|
||
|
|
*
|
||
|
|
.subckt VNSE_TLV354 1 2
|
||
|
|
.param FLW=10
|
||
|
|
.param NLF=605
|
||
|
|
.param NVR=7.3
|
||
|
|
.param GLF={PWR(FLW,0.25)*NLF/1164}
|
||
|
|
.param RNV={1.184*PWR(NVR,2)}
|
||
|
|
.model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
|
||
|
|
I1 0 7 10E-3
|
||
|
|
I2 0 8 10E-3
|
||
|
|
D1 7 0 DVN
|
||
|
|
D2 8 0 DVN
|
||
|
|
E1 3 6 7 8 {GLF}
|
||
|
|
R1 3 0 1E9
|
||
|
|
R2 3 0 1E9
|
||
|
|
R3 3 6 1E9
|
||
|
|
E2 6 4 5 0 10
|
||
|
|
R4 5 0 {RNV}
|
||
|
|
R5 5 0 {RNV}
|
||
|
|
R6 3 4 1E9
|
||
|
|
R7 4 0 1E9
|
||
|
|
E3 1 2 3 4 1
|
||
|
|
.ends VNSE_TLV354
|
||
|
|
*
|
||
|
|
.subckt CLAMP_AMP_LO_TLV354 VC+ VC- VIN COM VO+ VO-
|
||
|
|
.param G=1
|
||
|
|
GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
|
||
|
|
GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
|
||
|
|
.ends CLAMP_AMP_LO_TLV354
|
||
|
|
*
|
||
|
|
.subckt VCCS_LIM_GR_TLV354 VC+ VC- IOUT+ IOUT-
|
||
|
|
.param Gain = 1
|
||
|
|
.param Ipos = 0.25
|
||
|
|
.param Ineg = -0.25
|
||
|
|
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
|
||
|
|
.ends VCCS_LIM_GR_TLV354
|
||
|
|
*
|
||
|
|
.subckt VCCS_LIM_CLAWp_TLV354 VC+ VC- IOUT+ IOUT-
|
||
|
|
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
|
||
|
|
+(0, 1.0064e-4)
|
||
|
|
+(9.82, 1.1e-4)
|
||
|
|
+(20, 2.31e-4)
|
||
|
|
+(40.51, 4.34e-4)
|
||
|
|
+(70, 7.51e-4)
|
||
|
|
+(100, 1.17e-3)
|
||
|
|
+(120, 1.52e-3)
|
||
|
|
+(150, 2.11e-3)
|
||
|
|
.ends VCCS_LIM_CLAWp_TLV354
|
||
|
|
*
|