added simulation files

sim/AD8129.asy

@@ -0,0 +1,31 @@
+Version 4
+SymbolType BLOCK
+LINE Normal -80 112 -80 -112
+LINE Normal 144 0 -80 -112
+LINE Normal -80 112 144 0
+WINDOW 0 -26 -156 Bottom 2
+WINDOW 3 -13 123 Top 2
+SYMATTR Prefix X
+SYMATTR Value AD8129
+SYMATTR ModelFile Z:\home\wbraun\Projects\little-bee\modeling\ad8129.cir
+PIN -80 -80 LEFT 8
+PINATTR PinName IN+
+PINATTR SpiceOrder 1
+PIN -80 -32 LEFT 8
+PINATTR PinName IN-
+PINATTR SpiceOrder 2
+PIN -80 32 LEFT 8
+PINATTR PinName REF
+PINATTR SpiceOrder 3
+PIN -80 80 LEFT 8
+PINATTR PinName FB
+PINATTR SpiceOrder 4
+PIN 16 -64 VRIGHT 8
+PINATTR PinName V+
+PINATTR SpiceOrder 5
+PIN 16 64 VLEFT 8
+PINATTR PinName V-
+PINATTR SpiceOrder 6
+PIN 144 0 RIGHT 8
+PINATTR PinName OUT 
+PINATTR SpiceOrder 7

sim/TLV354.LIB

@@ -0,0 +1,387 @@
+*$
+* TLV354
+*************************************************************************************************
+* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.                                            
+*************************************************************************************************
+** This model is designed as an aid for customers of Texas Instruments.
+** TI and its licensor's and suppliers make no warranties, either expressed
+** or implied, with respect to this model, including the warranties of 
+** merchantability or fitness for a particular purpose.  The model is
+** provided solely on an "as is" basis.  The entire risk as to its quality
+** and performance is with the customer
+*************************************************************************************************
+*
+* This model is subject to change without notice. Texas Instruments
+* Incorporated is not responsible for updating this model.
+*
+*************************************************************************************************
+*
+** Released by: Online Design Tools, Texas Instruments Inc.
+* Part: TLV354
+* Date: 13FEB2019
+* Model Type: Generic (suitable for all analysis types)
+* EVM Order Number: N/A 
+* EVM Users Guide:  N/A 
+* Datasheet: SBOS756 -OCTOBER 2016
+* Created with Green-Williams-Lis Op Amp Macro-model Architecture
+*
+* Model Version: Final 1.2
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.2
+* Updated with unique subckt name,Current Noise, Vos drift and edits in claw block
+*
+*
+* Final 1.1
+* Release to Web.
+*
+****************************************************************************
+* Model Usage Notes:
+* 1. The following parameters are modeled: 
+* 		OPEN-LOOP GAIN AND PHASE VS. FREQUENCY  WITH RL, CL EFFECTS (Aol)
+* 		UNITY GAIN BANDWIDTH (GBW)
+* 		INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)
+* 		POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)
+* 		DIFFERENTIAL INPUT IMPEDANCE (Zid)
+* 		COMMON-MODE INPUT IMPEDANCE (Zic)
+* 		OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)
+* 		OUTPUT CURRENT THROUGH THE SUPPLY (Iout)
+* 		INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)
+* 		INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)
+* 		OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)
+* 		SHORT-CIRCUIT OUTPUT CURRENT (Isc)
+* 		QUIESCENT CURRENT (Iq)
+* 		SETTLING TIME VS. CAPACITIVE LOAD (ts)
+* 		SLEW RATE (SR)
+* 		SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD
+* 		LARGE SIGNAL RESPONSE
+* 		OVERLOAD RECOVERY TIME (tor)
+* 		INPUT BIAS CURRENT (Ib)
+* 		INPUT OFFSET CURRENT (Ios)
+* 		INPUT OFFSET VOLTAGE (Vos)
+* 		INPUT OFFSET VOLTAGE VS. TEMPERATURE (VOS DRIFT)
+* 		INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
+* 		INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)
+* 		INPUT/OUTPUT ESD CELLS (ESDin, ESDout)
+******************************************************
+.subckt TLV354 IN+ IN- VCC VEE OUT
+******************************************************
+* MODEL DEFINITIONS:
+.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=100e-3 Voff=0)
+.model R_NOISELESS RES(T_ABS=-273.15)
+.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)
+.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)
+******************************************************
+XV_OS VOS N037 VOS_DRIFT_TLV354
+R1 N036 CMR R_NOISELESS 1e-3 
+R2 FB- VOS- R_NOISELESS 1e-3 
+R3 N054 0 R_NOISELESS 1e12 
+C1 N054 0 1
+R4 VCC_B N053 R_NOISELESS 1e-3 
+C2 N053 0 1e-15
+C3 N055 0 1e-15
+R5 N055 VEE_B R_NOISELESS 1e-3 
+G_PSR N036 PSR N010 N009 1e-3
+R6 MID N039 R_NOISELESS 1e12 
+VCM_MIN N040 VEE_B -0.1
+R7 N040 MID R_NOISELESS 1e12 
+VCM_MAX N039 VCC_B +0.1
+XVCM_CLAMP PSR MID N038 MID N039 N040 VCCS_EXT_LIM_TLV354
+R8 N038 MID R_NOISELESS 1 
+C4 VCM_CLAMP MID 1e-15
+R9 N038 VCM_CLAMP R_NOISELESS 1e-3 
+V4 N052 OUT 0
+R10 MID N044 R_NOISELESS 1e12 
+R11 MID N045 R_NOISELESS 1e12 
+XIQp VIMON MID VCC MID VCCS_LIM_IQ_TLV354
+XIQn MID VIMON VEE MID VCCS_LIM_IQ_TLV354
+R12 VCC_B N013 R_NOISELESS 1e3 
+R13 N026 VEE_B R_NOISELESS 1e3 
+XCLAWp VIMON MID N013 VCC_B VCCS_LIM_CLAWp_TLV354
+XCLAWn MID VIMON VEE_B N026 VCCS_LIM_CLAWn_TLV354
+R14 VEE_CLP MID R_NOISELESS 1e3 
+R15 MID VCC_CLP R_NOISELESS 1e3 
+R16 N014 N013 R_NOISELESS 1e-3 
+R17 N027 N026 R_NOISELESS 1e-3 
+C5 MID N014 1e-15
+C6 N027 MID 1e-15
+R18 VOUT_S N045 R_NOISELESS 100 
+C7 VOUT_S MID 1e-12
+G2 MID VCC_CLP N014 MID 1e-3
+G3 MID VEE_CLP N027 MID 1e-3
+XCL_AMP N008 N034 VIMON MID N017 N024 CLAMP_AMP_LO_TLV354
+V_ISCp N008 MID 150
+V_ISCn N034 MID -165
+XOL_SENSE_TLV354 MID N057 OLN OLP OL_SENSE_TLV354
+R19 N034 MID R_NOISELESS 1e9 
+R20 N024 MID R_NOISELESS 1 
+C8 N025 MID 1e-15
+R21 MID N017 R_NOISELESS 1 
+R22 MID N008 R_NOISELESS 1e9 
+C9 MID N018 1e-15
+XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N015 N022 CLAMP_AMP_LO_TLV354
+R23 VEE_CLP MID R_NOISELESS 1e9 
+R24 N022 MID R_NOISELESS 1 
+C10 N023 MID 1e-15
+R25 MID N015 R_NOISELESS 1 
+R26 MID VCC_CLP R_NOISELESS 1e9 
+C11 MID N016 1e-15
+XCL_SRC N018 N025 CL_CLAMP MID VCCS_LIM_4_TLV354
+XCLAW_SRC N016 N023 CLAW_CLAMP MID VCCS_LIM_3_TLV354
+R27 N015 N016 R_NOISELESS 1e-3 
+R28 N023 N022 R_NOISELESS 1e-3 
+R29 N017 N018 R_NOISELESS 1e-3 
+R30 N025 N024 R_NOISELESS 1e-3 
+R31 N057 MID R_NOISELESS 1 
+R32 N057 SW_OL R_NOISELESS 100 
+C12 SW_OL MID 1e-12
+R33 VIMON N044 R_NOISELESS 100 
+C13 VIMON MID 1e-12
+C_DIFF N011 VOS- 2e-12
+C_CMn VOS- MID 2e-12
+C_CMp MID N011 2e-12
+I_Q VCC VEE 5.2e-3
+I_B PSR MID 3e-12
+I_OS FB- MID 2e-12
+R36 N032 MID R_NOISELESS 1 
+R37 N035 MID R_NOISELESS 1e9 
+R38 MID N020 R_NOISELESS 1 
+R39 MID N012 R_NOISELESS 1e9 
+XGR_AMP N012 N035 N019 MID N020 N032 CLAMP_AMP_HI_TLV354
+XGR_SRC N021 N033 CLAMP MID VCCS_LIM_GR_TLV354
+C17 MID N021 1e-15
+C18 N033 MID 1e-15
+V_GRn N035 MID -120
+V_GRp N012 MID 110
+R40 N020 N021 R_NOISELESS 1e-3 
+R41 N033 N032 R_NOISELESS 1e-3 
+R42 VSENSE N019 R_NOISELESS 1e-3 
+C19 MID N019 1e-15
+R43 MID VSENSE R_NOISELESS 1e3 
+G_CMR VOS CMR N007 MID 1e-3
+G8 MID CLAW_CLAMP N041 MID 1e-3
+R45 MID CLAW_CLAMP R_NOISELESS 1e3 
+G9 MID CL_CLAMP CLAW_CLAMP MID 1e-3
+R46 MID CL_CLAMP R_NOISELESS 1e3 
+R47 N050 VCLP R_NOISELESS 100 
+C24 MID VCLP 1e-12
+E4 N050 MID CL_CLAMP MID 1
+E5 N045 MID OUT MID 1
+H1 N044 MID V4 1e3
+S1 N043 N042 SW_OL MID OL_SW
+R52 MID N011 R_NOISELESS 1T
+R53 VOS- MID R_NOISELESS 1T
+R_CMR CMR VOS R_NOISELESS 1e3 
+R59 N053 N054 R_NOISELESS 1e6 
+R60 N054 N055 R_NOISELESS 1e6 
+R_PSR PSR N036 R_NOISELESS 1e3 
+G15 MID VSENSE CLAMP MID 1e-3
+E6 VD2 MID N031 MID 1
+V_ORp N031 VCLP 0.65
+V_ORn N028 VCLP -0.65
+E7 VD1 MID N028 MID 1
+V11 N029 VD1 0
+V12 N030 VD2 0
+H2 OLN MID V11 -1
+H3 OLP MID V12 1
+S2 VCC IN- IN- VCC ESD_SW
+S3 VCC IN+ IN+ VCC ESD_SW
+S4 IN- VEE VEE IN- ESD_SW
+S5 IN+ VEE VEE IN+ ESD_SW
+S6 VCC OUT OUT VCC ESD_SW
+S7 OUT VEE VEE OUT ESD_SW
+E1 MID 0 N054 0 1
+G16 0 VCC_B VCC 0 1
+G17 0 VEE_B VEE 0 1
+R88 VCC_B 0 R_NOISELESS 1 
+R89 VEE_B 0 R_NOISELESS 1 
+S8 N030 CLAMP CLAMP N030 OR_SW
+S9 CLAMP N029 N029 CLAMP OR_SW
+XVCCS_LIM_1_TLV354 VCM_CLAMP FB- MID GAIN_1 VCCS_LIM_1_TLV354
+XVCCS_LIM_2_TLV354 GAIN_1 MID MID CLAMP VCCS_LIM_2_TLV354
+R44 GAIN_1 MID R_NOISELESS 1e6 
+R58 CLAMP MID R_NOISELESS 1e6 
+C20 CLAMP MID 6.5e-10
+R34 N011 IN+ R_NOISELESS 1e-3 
+R35 VOS- IN- R_NOISELESS 1e-3 
+R48 MID N041 R_NOISELESS 1e6 
+G1 MID N041 VSENSE MID 1e-6
+C14 N041 MID 7.23e-16
+Xe_n N037 N011 VNSE_TLV354
+C22 N002 N001 4.547e-15
+G_adjust1 MID N001 N011 MID 3.985e-2
+Rsrc1 N001 MID R_NOISELESS 1 
+R56 N002 MID R_NOISELESS 2.063e5 
+R57 N002 N001 R_NOISELESS 1e8 
+Rsrc2 N007 MID R_NOISELESS 1 
+G5 MID N007 N002 MID 1
+C23 N005 N006 1.36e-14
+G_adjust2 MID N006 VCC_B MID 8.834e-1
+Rsrc3 N006 MID R_NOISELESS 1 
+R61 N005 MID R_NOISELESS 4.256e4 
+R62 N005 N006 R_NOISELESS 1e8 
+G6 MID N010 N005 MID 1
+Rsrc4 N010 MID R_NOISELESS 1 
+C25 N004 N003 6.366e-14
+R63 N004 MID R_NOISELESS 2.501e4 
+R64 N004 N003 R_NOISELESS 1e8 
+G7 MID N009 N004 MID 1
+Rsrc6 N009 MID R_NOISELESS 1 
+G10 MID N003 VEE_B MID 6.64e-1
+R65 N003 MID R_NOISELESS 1 
+Rx1 N052 N051 R_NOISELESS 6.67e4
+Rdummy1 N052 MID R_NOISELESS 6.67e3
+G_Zo MID N042 CL_CLAMP N052 89
+Rdc N042 MID R_NOISELESS 1
+R69 N043 N042 R_NOISELESS 10e3
+R70 MID N043 R_NOISELESS 4.65e2
+G12 MID N046 N043 MID 22.5
+R71 N046 MID R_NOISELESS 1
+C28 N043 N042 6e-8
+R75 N047 N046 R_NOISELESS 2.3e4
+R76 N056 N047 R_NOISELESS 10e3
+C29 MID N056 4.823e-14
+G14 MID N048 N047 MID 1
+R77 N048 MID R_NOISELESS 1
+R78 N049 N048 R_NOISELESS 10e3
+R79 MID N049 R_NOISELESS 3.311e1
+C30 N049 N048 4.823e-14
+XU1 N049 MID N051 MID VCVS_LIM_1_TLV354
+Xi_np N037 MID FEMT_TLV354
+Xi_nn VOS- MID FEMT_TLV354
+.ends TLV354
+*
+.SUBCKT VOS_DRIFT_TLV354 VOS+ VOS-
+.PARAM DC = 645e-6
+.PARAM POL = 1
+.PARAM DRIFT = 4.5E-06
+E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
+.ENDS
+*
+.subckt CLAMP_AMP_HI_TLV354 VC+ VC- VIN COM VO+ VO-
+.param G=10
+GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
+GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
+.ends CLAMP_AMP_HI_TLV354
+*
+.subckt OL_SENSE_TLV354 1   2  3  4
+GSW+ 1 2 Value = {IF((V(3,1)>1e-3 | V(4,1)>1e-3),1,0)}
+.ends OL_SENSE_TLV354
+*
+.subckt FEMT_TLV354 1 2
+.param NVRF=50
+.param RNVF={1.184*PWR(NVRF,2)}
+E1 3 0 5 0 10
+R1 5 0 {RNVF}
+R2 5 0 {RNVF}
+G1 1 2 3 0 1e-6
+.ends FEMT_TLV354
+*
+.subckt VCCS_EXT_LIM_TLV354 VIN+ VIN- IOUT- IOUT+ VP+ VP-
+.param Gain = 1
+G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
+.ends VCCS_EXT_LIM_TLV354
+*
+.subckt VCCS_LIM_1_TLV354 VC+ VC- IOUT+ IOUT-
+.param Gain = 1e-4
+.param Ipos = .5
+.param Ineg = -.5
+G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
+.ends VCCS_LIM_1_TLV354
+*
+.subckt VCCS_LIM_2_TLV354 VC+ VC- IOUT+ IOUT-
+.param Gain = 4.71e-3
+.param Ipos = 99.6e-3
+.param Ineg = -99.6e-3
+G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
+.ends VCCS_LIM_2_TLV354
+*
+.subckt VCCS_LIM_3_TLV354 VC+ VC- IOUT+ IOUT-
+.param Gain = 1
+.param Ipos = 220e-3
+.param Ineg = -240e-3
+G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
+.ends VCCS_LIM_3_TLV354
+*
+.subckt VCCS_LIM_4_TLV354 VC+ VC- IOUT+ IOUT-
+.param Gain = 1
+.param Ipos = 230e-3
+.param Ineg = -250e-3
+G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
+.ends VCCS_LIM_4_TLV354
+*
+.subckt VCCS_LIM_CLAWn_TLV354 VC+ VC- IOUT+ IOUT-
+G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
++(0, 1.0064e-4)
++(10, 1.28e-4)
++(20, 2.16e-4)
++(50, 5.31e-4)
++(90.6, 9.91e-4)
++(120, 1.39e-3)
++(140, 1.7e-3)
++(163.7, 2.16e-3)
+.ends VCCS_LIM_CLAWn_TLV354
+*
+.subckt VCCS_LIM_IQ_TLV354 VC+ VC- IOUT+ IOUT-
+.param Gain = 1e-3
+G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )}
+.ends VCCS_LIM_IQ_TLV354
+*
+.subckt VCVS_LIM_1_TLV354 VC+ VC- VOUT+ VOUT-
+.param Gain = 3.03e2
+.param Vpos = 20.5e3
+.param Vneg = -22.5e3
+E1 VOUT+ VOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Vneg,Vpos)}
+.ends VCVS_LIM_1_TLV354
+*
+.subckt VNSE_TLV354 1 2
+.param FLW=10
+.param NLF=605
+.param NVR=7.3
+.param GLF={PWR(FLW,0.25)*NLF/1164}
+.param RNV={1.184*PWR(NVR,2)}
+.model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
+I1 0 7 10E-3
+I2 0 8 10E-3
+D1 7 0 DVN
+D2 8 0 DVN
+E1 3 6 7 8 {GLF}
+R1 3 0 1E9
+R2 3 0 1E9
+R3 3 6 1E9
+E2 6 4 5 0 10
+R4 5 0 {RNV}
+R5 5 0 {RNV}
+R6 3 4 1E9
+R7 4 0 1E9
+E3 1 2 3 4 1
+.ends VNSE_TLV354
+*
+.subckt CLAMP_AMP_LO_TLV354 VC+ VC- VIN COM VO+ VO-
+.param G=1
+GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
+GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
+.ends CLAMP_AMP_LO_TLV354
+*
+.subckt VCCS_LIM_GR_TLV354 VC+ VC- IOUT+ IOUT-
+.param Gain = 1
+.param Ipos = 0.25
+.param Ineg = -0.25
+G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
+.ends VCCS_LIM_GR_TLV354
+*
+.subckt VCCS_LIM_CLAWp_TLV354 VC+ VC- IOUT+ IOUT-
+G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
++(0, 1.0064e-4)
++(9.82, 1.1e-4)
++(20, 2.31e-4)
++(40.51, 4.34e-4)
++(70, 7.51e-4)
++(100, 1.17e-3)
++(120, 1.52e-3)
++(150, 2.11e-3)
+.ends VCCS_LIM_CLAWp_TLV354
+*

sim/ad8129.cir

@@ -0,0 +1,127 @@
+* AD8129  SPICE Macro-model                 
+* Description: Amplifier
+* Generic Desc:
+* Developed by: CK TRW/ADI
+* Revision History:
+*   1.1 (1/2013) Updated to new header style
+*   1.0 (07/2010)
+* Copyright 2006 by Analog Devices, Inc.
+*
+* Refer to 
+* http://www.analog.com/Analog_Root/static/techSupport/designTools/
+* spiceModels/license/spice_general.html for License Statement.  
+* Use of this model indicates your acceptance with the terms and 
+* provisions in the License Statement.
+*
+* BEGIN Notes:
+* 
+* Not Modeled:
+*    Distortion
+*    Noise
+*
+* Parameters modeled include:
+*    Bandwidth
+*    Slew Rate
+*    Input Bias Current
+*    Offset Voltage
+*  
+* END Notes   
+*  
+* Node assignments
+*                IN+ input
+*                | IN- input
+*                | | REF input
+*                | | | FB input
+*                | | | | V+
+*                | | | | |  V-
+*                | | | | |  |  out
+*                | | | | |  |  |
+.SUBCKT AD8129   1 2 3 4 99 50 45
+*
+* INPUT STAGE
+*
+Q1   17  1   9   QX
+Q2   18  11  10  QX
+R1   9   12  1100
+R2   10  12  1100
+I1   12  50   2E-3
+Dcm1 95 12 dx
+Vcm1 95 50 2.2
+Dcm2 94 16 dx
+Vcm2 94 50 2.2
+		 
+EOS1 2   11  POLY(1) (31,98)  1.5E-3  1
+IOS1 1   2   0.08u
+C1   1   2   3E-12
+RD1  1   2   6E6
+*
+* REF/FB INPUT STAGE
+*
+Q3   17  3   14  QY
+Q4   18  13  15  QY
+R3   14  16  1100
+R4   15  16  1100
+I2   16  50   2E-3
+VOS2 4   13  1.5E-3
+IOS2 3   4   0.08u
+C2   3   4   2E-12
+RD2  3   4   1.93E6
+*
+VC1  32  17  DC  0.5
+VC2  33  18  DC  0.5
+D7   99   32  DX
+D8   99   33  DX
+*
+*
+* TRANSCONDUCTANCE STAGE & DOMINANT POLE AT ?? KHZ
+*
+R7   19  98  6E6
+C3   19  98  .12E-12
+F1   98  19  POLY(2)  VC1  VC2  0   1   -1
+V2   99  20  1.7
+V3   21  50  1.7
+D1   19  20  DX
+D2   21  19  DX
+*
+* POLE AT ?? MHZ
+*
+R6   23  98   100k
+C4   23  98   4f
+G2   98  23   19  98  1e-5
+*
+* COMMON-MODE GAIN NETWORK WITH ZERO AT 100 KHZ
+*
+R10  30  31   1E6
+R11  31  98   1
+C7   30  31   3.18E-12
+E3   98  30   POLY(2)  (1,98) (2,98)  0  5  5
+*
+* OUTPUT STAGE
+*
+
+Eref 98 0 poly(2) 50 0 99 0 0 0.5 0.5
+FSY  99   50   POLY(2) V7 V8 10E-3 1 1
+R15  29  99   12
+R16  29  50   12
+
+L1   29  45   6E-10
+G7   29  99   99  23  83.3e-3
+G8   50  29   23  50  83.3e-3
+V4   25 29   -.332
+V5   29 26   -.3
+D3   23 25  DX
+D4   26 23 DX
+G5   98 70   29 23 2.94E-2
+D5   70 71   DX
+D6   72 70   DX
+V7   71 98   DC 0
+V8   98 72   DC 0
+*
+* MODELS USED
+*
+.MODEL QX NPN(BF=3000)
+.MODEL QY NPN(BF=1500)
+.MODEL DX   D(IS=1E-15)
+.ENDS
+*$
+;$SpiceType=AMBIGUOUS