22 lines
471 B
Coq
22 lines
471 B
Coq
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module top (input clk, input [3:0] sw, output [11:0] led);
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// assign led = {8'b0, ~(&sw), ^sw, &sw, |sw};
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reg clkdiv;
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reg [22:0] ctr;
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always @(posedge clk) {clkdiv, ctr} <= ctr + 1'b1;
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reg [5:0] led_r = 4'b0000;
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always @(posedge clk) begin
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if (clkdiv)
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led_r <= led_r + 1'b1;
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end
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wire [11:0] led_s = led_r[3:0] << (4 * led_r[5:4]);
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assign led = (&(led_r[5:4]) ? {3{led_r[3:0]}} : led_s) ^ {3{sw}};
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endmodule
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