2019-11-12 00:55:52 +08:00
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/*
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* nextpnr -- Next Generation Place and Route
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*
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2021-06-09 20:09:08 +08:00
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* Copyright (C) 2019 gatecat <gatecat@ds0.me>
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2019-11-12 00:55:52 +08:00
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/*
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* Generic Frontend Framework
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*
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* This is designed to make it possible to build frontends for parsing any format isomorphic to Yosys JSON [1]
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* with maximal inlining and minimal need for overhead such as runtime polymorphism or extra wrapper types.
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*
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2021-06-09 20:13:50 +08:00
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* [1] https://yosyshq.net/yosys/cmd_write_json.html
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2019-11-12 00:55:52 +08:00
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*
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* The frontend should implement a class referred to as FrontendType that defines the following type(def)s and
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* functions:
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*
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* Types:
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* ModuleDataType: corresponds to a single entry in "modules"
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* ModulePortDataType: corresponds to a single entry in "ports" of a module
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* CellDataType: corresponds to a single entry in "cells"
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* NetnameDataType: corresponds to a single entry in "netnames"
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* BitVectorDataType: corresponds to a signal/constant bit vector (e.g. a "connections" field)
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*
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* Functions:
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_module(Func) const;
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2019-11-12 00:55:52 +08:00
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* calls Func(const std::string &name, const ModuleDataType &mod);
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* for each module in the netlist
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_port(const ModuleDataType &mod, Func) const;
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2019-11-12 00:55:52 +08:00
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* calls Func(const std::string &name, const ModulePortDataType &port);
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* for each port of mod
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_cell(const ModuleDataType &mod, Func) const;
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* calls Func(const std::string &name, const CellDataType &cell)
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2019-11-12 00:55:52 +08:00
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* for each cell of mod
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_netname(const ModuleDataType &mod, Func) const;
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2019-11-12 00:55:52 +08:00
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* calls Func(const std::string &name, const NetnameDataType &cell);
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* for each netname entry of mod
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*
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2019-11-16 01:55:02 +08:00
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* PortType get_port_dir(const ModulePortDataType &port) const;
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2019-11-12 00:55:52 +08:00
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* gets the PortType direction of a module port
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*
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2019-11-16 01:55:02 +08:00
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* int get_array_offset(const ModulePortDataType &port) const;
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2019-11-14 02:52:13 +08:00
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* gets the start bit number of a port or netname entry
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2019-11-12 00:55:52 +08:00
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*
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2019-11-16 01:55:02 +08:00
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* bool is_array_upto(const ModulePortDataType &port) const;
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2019-11-14 02:52:13 +08:00
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* returns true if a port/net is an "upto" type port or netname entry
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2019-11-12 00:55:52 +08:00
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*
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2019-11-16 01:55:02 +08:00
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* const BitVectorDataType &get_port_bits(const ModulePortDataType &port) const;
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2019-11-12 00:55:52 +08:00
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* gets the bit vector of a module port
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*
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2019-11-16 01:55:02 +08:00
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* const std::string& get_cell_type(const CellDataType &cell) const;
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2019-11-12 00:55:52 +08:00
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* gets the type of a cell
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_attr(const {ModuleDataType|CellDataType|ModulePortDataType|NetnameDataType} &obj, Func) const;
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2019-11-12 00:55:52 +08:00
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* calls Func(const std::string &name, const Property &value);
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* for each attribute on a module, cell, module port or net
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_param(const CellDataType &obj, Func) const;
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2019-11-12 00:55:52 +08:00
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* calls Func(const std::string &name, const Property &value);
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* for each parameter of a cell
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*
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2019-11-23 01:29:45 +08:00
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* void foreach_setting(const ModuleDataType &obj, Func) const;
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* calls Func(const std::string &name, const Property &value);
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* for each module-level setting
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_port_dir(const CellDataType &cell, Func) const;
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2019-11-12 00:55:52 +08:00
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* calls Func(const std::string &name, PortType dir);
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* for each port direction of a cell
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*
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2019-11-16 01:55:02 +08:00
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* void foreach_port_conn(const CellDataType &cell, Func) const;
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2019-11-12 00:55:52 +08:00
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* calls Func(const std::string &name, const BitVectorDataType &conn);
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* for each port connection of a cell
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*
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2019-11-16 01:55:02 +08:00
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* const BitVectorDataType &get_net_bits(const NetnameDataType &net) const;
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2019-11-12 00:55:52 +08:00
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* gets the BitVector corresponding to the bits entry of a netname field
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*
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2019-11-16 01:55:02 +08:00
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* int get_vector_length(const BitVectorDataType &bits) const;
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2019-11-12 00:55:52 +08:00
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* gets the length of a BitVector
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*
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2019-11-16 01:55:02 +08:00
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* bool is_vector_bit_constant(const BitVectorDataType &bits, int i) const;
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2019-11-12 00:55:52 +08:00
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* returns true if bit <i> of bits is constant
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*
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2019-11-16 01:55:02 +08:00
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* char get_vector_bit_constval(const BitVectorDataType &bits, int i) const;
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2019-11-12 00:55:52 +08:00
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* returns a char [01xz] corresponding to the constant value of bit <i>
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*
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2019-11-16 01:55:02 +08:00
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* int get_vector_bit_signal(const BitVectorDataType &bits, int i) const;
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2019-11-12 00:55:52 +08:00
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* returns the signal number of vector bit <i>
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*
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2019-11-12 19:33:49 +08:00
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*/
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2019-11-13 20:11:17 +08:00
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#include "design_utils.h"
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2019-11-12 19:33:49 +08:00
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#include "log.h"
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#include "nextpnr.h"
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2019-11-16 02:04:02 +08:00
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#include "util.h"
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2019-11-12 19:33:49 +08:00
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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2019-11-14 02:52:13 +08:00
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// Used for hierarchy resolution
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struct ModuleInfo
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{
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bool is_top = false, is_blackbox = false, is_whitebox = false;
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inline bool is_box() const { return is_blackbox || is_whitebox; }
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2021-06-02 18:44:57 +08:00
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pool<IdString> instantiated_celltypes;
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2019-11-14 02:52:13 +08:00
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};
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2019-11-12 19:33:49 +08:00
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template <typename FrontendType> struct GenericFrontend
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{
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2021-02-12 05:33:55 +08:00
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GenericFrontend(Context *ctx, const FrontendType &impl, bool split_io) : ctx(ctx), impl(impl), split_io(split_io) {}
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2019-11-16 01:43:32 +08:00
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void operator()()
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{
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2019-11-16 01:55:02 +08:00
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// Find which module is top
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2019-11-16 01:43:32 +08:00
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find_top_module();
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HierModuleState m;
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m.is_toplevel = true;
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m.prefix = "";
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2019-11-29 23:58:02 +08:00
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m.path = top;
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ctx->top_module = top;
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2019-11-16 01:55:02 +08:00
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// Do the actual import, starting from the top level module
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2021-06-02 19:09:40 +08:00
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import_module(m, top.str(ctx), top.str(ctx), mod_refs.at(top.str(ctx)));
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2021-02-12 05:41:13 +08:00
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ctx->design_loaded = true;
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2019-11-16 01:43:32 +08:00
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}
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2019-11-16 01:55:02 +08:00
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2019-11-12 19:33:49 +08:00
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Context *ctx;
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const FrontendType &impl;
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2021-02-12 05:33:55 +08:00
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const bool split_io;
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2019-11-12 19:33:49 +08:00
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using mod_dat_t = typename FrontendType::ModuleDataType;
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using mod_port_dat_t = typename FrontendType::ModulePortDataType;
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using cell_dat_t = typename FrontendType::CellDataType;
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using netname_dat_t = typename FrontendType::NetnameDataType;
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using bitvector_t = typename FrontendType::BitVectorDataType;
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2021-06-02 18:44:57 +08:00
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dict<IdString, ModuleInfo> mods;
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2021-06-02 19:09:40 +08:00
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std::unordered_map<std::string, const mod_dat_t> mod_refs;
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2019-11-12 19:33:49 +08:00
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IdString top;
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// Process the list of modules and determine
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// the top module
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void find_top_module()
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{
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impl.foreach_module([&](const std::string &name, const mod_dat_t &mod) {
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IdString mod_id = ctx->id(name);
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auto &mi = mods[mod_id];
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2021-06-02 19:09:40 +08:00
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mod_refs.emplace(name, mod);
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2019-11-12 19:33:49 +08:00
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impl.foreach_attr(mod, [&](const std::string &name, const Property &value) {
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if (name == "top")
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mi.is_top = (value.intval != 0);
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else if (name == "blackbox")
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mi.is_blackbox = (value.intval != 0);
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else if (name == "whitebox")
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mi.is_whitebox = (value.intval != 0);
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});
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impl.foreach_cell(mod, [&](const std::string &name, const cell_dat_t &cell) {
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2019-11-14 02:52:13 +08:00
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mi.instantiated_celltypes.insert(ctx->id(impl.get_cell_type(cell)));
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2019-11-12 19:33:49 +08:00
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});
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});
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// First of all, see if a top module has been manually specified
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if (ctx->settings.count(ctx->id("frontend/top"))) {
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IdString user_top = ctx->id(ctx->settings.at(ctx->id("frontend/top")).as_string());
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if (!mods.count(user_top))
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log_error("Top module '%s' not found!\n", ctx->nameOf(user_top));
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top = user_top;
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return;
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}
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// If not, look for a module with the top attribute set
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IdString top_by_attr;
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for (auto &mod : mods) {
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if (mod.second.is_top && !mod.second.is_box()) {
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if (top_by_attr != IdString())
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log_error("Found multiple modules with (* top *) set (including %s and %s).\n",
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ctx->nameOf(top_by_attr), ctx->nameOf(mod.first));
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top_by_attr = mod.first;
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}
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}
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if (top_by_attr != IdString()) {
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top = top_by_attr;
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return;
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}
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// Finally, attempt to autodetect the top module using hierarchy
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// (a module that is not a box and is not used as a cell by any other module)
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2021-06-02 18:44:57 +08:00
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pool<IdString> candidate_top;
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2019-11-12 19:33:49 +08:00
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for (auto &mod : mods)
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if (!mod.second.is_box())
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candidate_top.insert(mod.first);
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for (auto &mod : mods)
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for (auto &c : mod.second.instantiated_celltypes)
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candidate_top.erase(c);
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2019-11-16 02:04:02 +08:00
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if (candidate_top.size() != 1) {
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if (candidate_top.size() == 0)
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log_info("No candidate top level modules.\n");
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else
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2021-06-02 18:44:57 +08:00
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for (auto ctp : candidate_top)
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2019-11-16 02:04:02 +08:00
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log_info("Candidate top module: '%s'\n", ctx->nameOf(ctp));
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2019-11-12 19:33:49 +08:00
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log_error("Failed to autodetect top module, please specify using --top.\n");
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2019-11-16 02:04:02 +08:00
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}
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2019-11-12 19:33:49 +08:00
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top = *(candidate_top.begin());
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}
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2019-11-13 20:11:17 +08:00
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// Create a unique name (guaranteed collision free) for a net or a cell; based on
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// a base name and suffix. __unique__i will be be appended with increasing i
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// if a collision is found until no collision
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IdString unique_name(const std::string &base, const std::string &suffix, bool is_net)
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{
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IdString name;
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int incr = 0;
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do {
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std::string comb = base + suffix;
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if (incr > 0) {
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comb += "__unique__";
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comb += std::to_string(incr);
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}
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name = ctx->id(comb);
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incr++;
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2021-12-17 22:51:00 +08:00
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} while (is_net ? (ctx->nets.count(name) || ctx->net_aliases.count(name)) : ctx->cells.count(name));
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2019-11-13 20:11:17 +08:00
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return name;
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}
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2019-11-13 21:51:28 +08:00
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// A flat index of map; designed to cope with merging nets where pointers to nets would go stale
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2019-11-13 20:11:17 +08:00
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// A net's udata points into this index
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std::vector<NetInfo *> net_flatindex;
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2019-11-13 21:51:28 +08:00
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std::vector<std::vector<int>> net_old_indices; // the other indices of a net in net_flatindex for merging
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2019-11-13 20:11:17 +08:00
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// This structure contains some structures specific to the import of a module at
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// a certain point in the hierarchy
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struct HierModuleState
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{
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bool is_toplevel;
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std::string prefix;
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2019-11-29 23:58:02 +08:00
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IdString parent_path, path;
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2019-11-13 20:11:17 +08:00
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// Map from index in module to "flat" index of nets
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2019-11-13 21:51:28 +08:00
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std::vector<int> index_to_net_flatindex;
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2019-11-13 20:11:17 +08:00
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// Get a reference to index_to_net; resizing if
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// appropriate
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2019-11-13 21:51:28 +08:00
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int &net_by_idx(int idx)
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2019-11-13 20:11:17 +08:00
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{
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NPNR_ASSERT(idx >= 0);
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if (idx >= int(index_to_net_flatindex.size()))
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2019-11-13 21:51:28 +08:00
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index_to_net_flatindex.resize(idx + 1, -1);
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2019-11-13 20:11:17 +08:00
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return index_to_net_flatindex.at(idx);
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}
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2021-06-02 18:44:57 +08:00
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dict<IdString, std::vector<int>> port_to_bus;
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2019-11-15 03:07:38 +08:00
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// All of the names given to a net
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std::vector<std::vector<std::string>> net_names;
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2019-11-13 20:11:17 +08:00
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};
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2019-11-29 23:58:02 +08:00
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void import_module(HierModuleState &m, const std::string &name, const std::string &type, const mod_dat_t &data)
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2019-11-13 20:11:17 +08:00
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{
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2019-11-29 23:58:02 +08:00
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NPNR_ASSERT(!ctx->hierarchy.count(m.path));
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ctx->hierarchy[m.path].name = ctx->id(name);
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ctx->hierarchy[m.path].type = ctx->id(type);
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ctx->hierarchy[m.path].parent = m.parent_path;
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ctx->hierarchy[m.path].fullpath = m.path;
|
|
|
|
|
2019-11-13 20:11:17 +08:00
|
|
|
std::vector<NetInfo *> index_to_net;
|
|
|
|
if (!m.is_toplevel) {
|
2019-11-16 01:43:32 +08:00
|
|
|
// Import port connections; for submodules only
|
2019-11-13 20:11:17 +08:00
|
|
|
import_port_connections(m, data);
|
2019-11-16 01:43:32 +08:00
|
|
|
} else {
|
|
|
|
// Just create a list of ports for netname resolution
|
2019-11-16 01:55:02 +08:00
|
|
|
impl.foreach_port(data,
|
2019-11-16 01:43:32 +08:00
|
|
|
[&](const std::string &name, const mod_port_dat_t &) { m.port_to_bus[ctx->id(name)]; });
|
2019-11-23 01:29:45 +08:00
|
|
|
// Import module-level attributes
|
|
|
|
impl.foreach_attr(
|
|
|
|
data, [&](const std::string &name, const Property &value) { ctx->attrs[ctx->id(name)] = value; });
|
|
|
|
// Import settings
|
|
|
|
impl.foreach_setting(data, [&](const std::string &name, const Property &value) {
|
|
|
|
ctx->settings[ctx->id(name)] = value;
|
|
|
|
});
|
2019-11-13 20:11:17 +08:00
|
|
|
}
|
2019-11-16 01:43:32 +08:00
|
|
|
import_module_netnames(m, data);
|
|
|
|
import_module_cells(m, data);
|
2020-01-18 23:37:13 +08:00
|
|
|
import_net_attrs(m, data);
|
2019-11-23 01:29:45 +08:00
|
|
|
if (m.is_toplevel) {
|
2019-11-16 01:43:32 +08:00
|
|
|
import_toplevel_ports(m, data);
|
2019-11-23 01:29:45 +08:00
|
|
|
// Mark design as loaded through nextpnr
|
|
|
|
ctx->settings[ctx->id("synth")] = 1;
|
|
|
|
// Process nextpnr-specific attributes
|
|
|
|
ctx->attributesToArchInfo();
|
|
|
|
}
|
2019-11-13 20:11:17 +08:00
|
|
|
}
|
|
|
|
|
2019-11-15 03:07:38 +08:00
|
|
|
// Multiple labels might refer to the same net. Resolve conflicts for the primary name thus:
|
|
|
|
// - (toplevel) ports are always preferred
|
|
|
|
// - names with fewer $ are always prefered
|
|
|
|
// - between equal $ counts, fewer .s are prefered
|
|
|
|
// - ties are resolved alphabetically
|
|
|
|
bool prefer_netlabel(HierModuleState &m, const std::string &a, const std::string &b)
|
|
|
|
{
|
|
|
|
if (m.port_to_bus.count(ctx->id(a)))
|
|
|
|
return true;
|
|
|
|
if (m.port_to_bus.count(ctx->id(b)))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (b.empty())
|
|
|
|
return true;
|
|
|
|
long a_dollars = std::count(a.begin(), a.end(), '$'), b_dollars = std::count(b.begin(), b.end(), '$');
|
|
|
|
if (a_dollars < b_dollars)
|
|
|
|
return true;
|
|
|
|
else if (a_dollars > b_dollars)
|
|
|
|
return false;
|
|
|
|
long a_dots = std::count(a.begin(), a.end(), '.'), b_dots = std::count(b.begin(), b.end(), '.');
|
|
|
|
if (a_dots < b_dots)
|
|
|
|
return true;
|
|
|
|
else if (a_dots > b_dots)
|
|
|
|
return false;
|
|
|
|
return a < b;
|
|
|
|
};
|
|
|
|
|
|
|
|
// Get a net by index in modulestate (not flatindex); creating it if it doesn't already exist
|
|
|
|
NetInfo *create_or_get_net(HierModuleState &m, int idx)
|
|
|
|
{
|
|
|
|
auto &midx = m.net_by_idx(idx);
|
2019-11-16 02:08:27 +08:00
|
|
|
if (midx != -1) {
|
|
|
|
return net_flatindex.at(midx);
|
2019-11-15 03:07:38 +08:00
|
|
|
} else {
|
2019-11-16 02:08:27 +08:00
|
|
|
std::string name;
|
|
|
|
if (idx < int(m.net_names.size()) && !m.net_names.at(idx).empty()) {
|
|
|
|
// Use the rule above to find the preferred name for a net
|
|
|
|
name = m.net_names.at(idx).at(0);
|
|
|
|
for (size_t j = 1; j < m.net_names.at(idx).size(); j++)
|
|
|
|
if (prefer_netlabel(m, m.net_names.at(idx).at(j), name))
|
|
|
|
name = m.net_names.at(idx).at(j);
|
|
|
|
} else {
|
|
|
|
name = "$frontend$" + std::to_string(idx);
|
|
|
|
}
|
|
|
|
NetInfo *net = ctx->createNet(unique_name(m.prefix, name, true));
|
|
|
|
// Add to the flat index of nets
|
|
|
|
net->udata = int(net_flatindex.size());
|
|
|
|
net_flatindex.push_back(net);
|
2020-03-06 23:21:28 +08:00
|
|
|
net_old_indices.emplace_back();
|
2019-11-16 02:08:27 +08:00
|
|
|
// Add to the module-level index of netsd
|
|
|
|
midx = net->udata;
|
|
|
|
// Create aliases for all possible names
|
|
|
|
if (idx < int(m.net_names.size()) && !m.net_names.at(idx).empty()) {
|
|
|
|
for (const auto &name : m.net_names.at(idx)) {
|
|
|
|
IdString name_id = ctx->id(name);
|
|
|
|
net->aliases.push_back(name_id);
|
|
|
|
ctx->net_aliases[name_id] = net->name;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
net->aliases.push_back(net->name);
|
|
|
|
ctx->net_aliases[net->name] = net->name;
|
|
|
|
}
|
|
|
|
return net;
|
2019-11-15 03:07:38 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get the name of a vector bit given basename; settings and index
|
|
|
|
std::string get_bit_name(const std::string &base, int index, int length, int offset = 0, bool upto = false)
|
|
|
|
{
|
|
|
|
std::string port = base;
|
|
|
|
if (length == 1 && offset == 0)
|
|
|
|
return port;
|
|
|
|
int real_index;
|
|
|
|
if (upto)
|
|
|
|
real_index = offset + length - index - 1; // reversed ports like [0:7]
|
|
|
|
else
|
|
|
|
real_index = offset + index; // normal 'downto' ports like [7:0]
|
|
|
|
port += '[';
|
|
|
|
port += std::to_string(real_index);
|
|
|
|
port += ']';
|
|
|
|
return port;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Import the netnames section of a module
|
|
|
|
void import_module_netnames(HierModuleState &m, const mod_dat_t &data)
|
|
|
|
{
|
|
|
|
impl.foreach_netname(data, [&](const std::string &basename, const netname_dat_t &nn) {
|
|
|
|
bool upto = impl.is_array_upto(nn);
|
|
|
|
int offset = impl.get_array_offset(nn);
|
|
|
|
const auto &bits = impl.get_net_bits(nn);
|
|
|
|
int width = impl.get_vector_length(bits);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
|
|
if (impl.is_vector_bit_constant(bits, i))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
std::string bit_name = get_bit_name(basename, i, width, offset, upto);
|
|
|
|
|
2019-11-16 01:55:02 +08:00
|
|
|
int net_bit = impl.get_vector_bit_signal(bits, i);
|
2019-11-15 03:07:38 +08:00
|
|
|
int mapped_bit = m.net_by_idx(net_bit);
|
|
|
|
if (mapped_bit == -1) {
|
|
|
|
// Net doesn't exist yet. Add the name here to the list of candidate names so we have that for when
|
|
|
|
// we create it later
|
|
|
|
if (net_bit >= int(m.net_names.size()))
|
|
|
|
m.net_names.resize(net_bit + 1);
|
|
|
|
m.net_names.at(net_bit).push_back(bit_name);
|
|
|
|
} else {
|
|
|
|
// Net already exists; add this name as an alias
|
|
|
|
NetInfo *ni = net_flatindex.at(mapped_bit);
|
|
|
|
IdString alias_name = ctx->id(m.prefix + bit_name);
|
|
|
|
if (ctx->net_aliases.count(alias_name))
|
|
|
|
continue; // don't add duplicate aliases
|
|
|
|
ctx->net_aliases[alias_name] = ni->name;
|
|
|
|
ni->aliases.push_back(alias_name);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
2020-01-18 23:37:13 +08:00
|
|
|
void import_net_attrs(HierModuleState &m, const mod_dat_t &data)
|
|
|
|
{
|
|
|
|
impl.foreach_netname(data, [&](const std::string &basename, const netname_dat_t &nn) {
|
|
|
|
const auto &bits = impl.get_net_bits(nn);
|
|
|
|
int width = impl.get_vector_length(bits);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
|
|
if (impl.is_vector_bit_constant(bits, i))
|
|
|
|
continue;
|
|
|
|
int net_bit = impl.get_vector_bit_signal(bits, i);
|
|
|
|
int mapped_bit = m.net_by_idx(net_bit);
|
|
|
|
if (mapped_bit != -1) {
|
|
|
|
NetInfo *ni = net_flatindex.at(mapped_bit);
|
|
|
|
impl.foreach_attr(nn, [&](const std::string &name, const Property &value) {
|
|
|
|
ni->attrs[ctx->id(name)] = value;
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
2019-11-16 01:55:02 +08:00
|
|
|
// Create a new constant net; given a hint for what the name should be and its value
|
|
|
|
NetInfo *create_constant_net(HierModuleState &m, const std::string &name_hint, char constval)
|
2019-11-16 01:43:32 +08:00
|
|
|
{
|
2019-11-16 01:55:02 +08:00
|
|
|
IdString name = unique_name(m.prefix, name_hint, true);
|
2019-11-15 04:01:45 +08:00
|
|
|
NetInfo *ni = ctx->createNet(name);
|
|
|
|
add_constant_driver(m, ni, constval);
|
2019-11-16 01:55:02 +08:00
|
|
|
return ni;
|
2019-11-15 04:01:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Import a leaf cell - (white|black)box
|
2019-11-16 01:43:32 +08:00
|
|
|
void import_leaf_cell(HierModuleState &m, const std::string &name, const cell_dat_t &cd)
|
|
|
|
{
|
2024-01-11 22:48:47 +08:00
|
|
|
auto cell_type = impl.get_cell_type(cd);
|
2024-01-23 19:16:14 +08:00
|
|
|
if (cell_type == "$scopeinfo" || cell_type == "$print" || cell_type == "$check")
|
2024-01-11 22:48:47 +08:00
|
|
|
return;
|
2019-11-16 01:55:02 +08:00
|
|
|
IdString inst_name = unique_name(m.prefix, name, false);
|
2019-12-01 22:03:23 +08:00
|
|
|
ctx->hierarchy[m.path].leaf_cells_by_gname[inst_name] = ctx->id(name);
|
2019-11-29 23:58:02 +08:00
|
|
|
ctx->hierarchy[m.path].leaf_cells[ctx->id(name)] = inst_name;
|
2024-01-11 22:48:47 +08:00
|
|
|
CellInfo *ci = ctx->createCell(inst_name, ctx->id(cell_type));
|
2019-12-01 22:03:23 +08:00
|
|
|
ci->hierpath = m.path;
|
2019-11-15 04:01:45 +08:00
|
|
|
// Import port directions
|
2021-06-02 18:44:57 +08:00
|
|
|
dict<IdString, PortType> port_dirs;
|
2019-11-16 01:43:32 +08:00
|
|
|
impl.foreach_port_dir(cd, [&](const std::string &port, PortType dir) { port_dirs[ctx->id(port)] = dir; });
|
2019-11-15 04:01:45 +08:00
|
|
|
// Import port connectivity
|
|
|
|
impl.foreach_port_conn(cd, [&](const std::string &name, const bitvector_t &bits) {
|
2019-11-16 01:43:32 +08:00
|
|
|
if (!port_dirs.count(ctx->id(name)))
|
|
|
|
log_error("Failed to get direction for port '%s' of cell '%s'\n", name.c_str(), inst_name.c_str(ctx));
|
|
|
|
PortType dir = port_dirs.at(ctx->id(name));
|
|
|
|
int width = impl.get_vector_length(bits);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
|
|
std::string port_bit_name = get_bit_name(name, i, width);
|
|
|
|
IdString port_bit_ids = ctx->id(port_bit_name);
|
|
|
|
// Create cell port
|
|
|
|
ci->ports[port_bit_ids].name = port_bit_ids;
|
|
|
|
ci->ports[port_bit_ids].type = dir;
|
|
|
|
// Resolve connectivity
|
|
|
|
NetInfo *net;
|
|
|
|
if (impl.is_vector_bit_constant(bits, i)) {
|
|
|
|
// Create a constant driver if one is needed
|
2020-01-16 20:15:16 +08:00
|
|
|
net = create_constant_net(m, inst_name.str(ctx) + "." + port_bit_name + "$const",
|
2019-11-16 01:43:32 +08:00
|
|
|
impl.get_vector_bit_constval(bits, i));
|
|
|
|
} else {
|
|
|
|
// Otherwise, lookup (creating if needed) the net with this index
|
|
|
|
net = create_or_get_net(m, impl.get_vector_bit_signal(bits, i));
|
|
|
|
}
|
|
|
|
NPNR_ASSERT(net != nullptr);
|
|
|
|
|
|
|
|
// Check for multiple drivers
|
|
|
|
if (dir == PORT_OUT && net->driver.cell != nullptr)
|
|
|
|
log_error("Net '%s' is multiply driven by cell ports %s.%s and %s.%s\n", ctx->nameOf(net),
|
|
|
|
ctx->nameOf(net->driver.cell), ctx->nameOf(net->driver.port), ctx->nameOf(inst_name),
|
|
|
|
port_bit_name.c_str());
|
2022-02-18 18:52:37 +08:00
|
|
|
ci->connectPort(port_bit_ids, net);
|
2019-11-16 01:43:32 +08:00
|
|
|
}
|
2019-11-15 04:13:57 +08:00
|
|
|
});
|
|
|
|
// Import attributes and parameters
|
2019-11-16 01:43:32 +08:00
|
|
|
impl.foreach_attr(cd,
|
|
|
|
[&](const std::string &name, const Property &value) { ci->attrs[ctx->id(name)] = value; });
|
|
|
|
impl.foreach_param(cd,
|
|
|
|
[&](const std::string &name, const Property &value) { ci->params[ctx->id(name)] = value; });
|
2019-11-15 04:13:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Import a submodule cell
|
2019-11-16 01:43:32 +08:00
|
|
|
void import_submodule_cell(HierModuleState &m, const std::string &name, const cell_dat_t &cd)
|
|
|
|
{
|
2019-11-15 04:13:57 +08:00
|
|
|
HierModuleState submod;
|
|
|
|
submod.is_toplevel = false;
|
|
|
|
// Create mapping from submodule port to nets (referenced by index in flatindex)
|
|
|
|
impl.foreach_port_conn(cd, [&](const std::string &name, const bitvector_t &bits) {
|
2019-11-15 04:01:45 +08:00
|
|
|
int width = impl.get_vector_length(bits);
|
|
|
|
for (int i = 0; i < width; i++) {
|
2019-11-15 04:13:57 +08:00
|
|
|
// Index of port net in flatindex
|
|
|
|
int net_ref = -1;
|
2019-11-15 04:01:45 +08:00
|
|
|
if (impl.is_vector_bit_constant(bits, i)) {
|
|
|
|
// Create a constant driver if one is needed
|
2019-11-15 04:13:57 +08:00
|
|
|
std::string port_bit_name = get_bit_name(name, i, width);
|
2019-11-16 01:43:32 +08:00
|
|
|
NetInfo *cnet = create_constant_net(m, name + "." + port_bit_name + "$const",
|
|
|
|
impl.get_vector_bit_constval(bits, i));
|
2019-11-15 04:13:57 +08:00
|
|
|
cnet->udata = int(net_flatindex.size());
|
|
|
|
net_flatindex.push_back(cnet);
|
2020-03-06 23:21:28 +08:00
|
|
|
net_old_indices.emplace_back();
|
2019-11-15 04:13:57 +08:00
|
|
|
net_ref = cnet->udata;
|
2019-11-15 04:01:45 +08:00
|
|
|
} else {
|
2019-11-15 04:13:57 +08:00
|
|
|
// Otherwise, lookup (creating if needed) the net with given in-module index
|
|
|
|
net_ref = create_or_get_net(m, impl.get_vector_bit_signal(bits, i))->udata;
|
2019-11-15 04:01:45 +08:00
|
|
|
}
|
2019-11-15 04:13:57 +08:00
|
|
|
NPNR_ASSERT(net_ref != -1);
|
|
|
|
submod.port_to_bus[ctx->id(name)].push_back(net_ref);
|
2019-11-15 04:01:45 +08:00
|
|
|
}
|
|
|
|
});
|
2019-11-15 04:13:57 +08:00
|
|
|
// Create prefix for submodule
|
|
|
|
submod.prefix = m.prefix;
|
|
|
|
submod.prefix += name;
|
|
|
|
submod.prefix += '.';
|
2019-11-29 23:58:02 +08:00
|
|
|
submod.parent_path = m.path;
|
|
|
|
submod.path = ctx->id(m.path.str(ctx) + "/" + name);
|
2019-11-30 00:25:11 +08:00
|
|
|
ctx->hierarchy[m.path].hier_cells[ctx->id(name)] = submod.path;
|
2019-11-15 04:13:57 +08:00
|
|
|
// Do the submodule import
|
2019-11-29 23:58:02 +08:00
|
|
|
auto type = impl.get_cell_type(cd);
|
2021-06-02 19:09:40 +08:00
|
|
|
import_module(submod, name, type, mod_refs.at(type));
|
2024-12-17 18:30:39 +08:00
|
|
|
// Add current cell attributes to the imported module
|
|
|
|
impl.foreach_attr( cd, [&](const std::string &name, const Property &value)
|
|
|
|
{ ctx->hierarchy[submod.path].attrs[ctx->id(name)] = value; } );
|
2019-11-15 04:01:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Import the cells section of a module
|
2019-11-16 01:43:32 +08:00
|
|
|
void import_module_cells(HierModuleState &m, const mod_dat_t &data)
|
|
|
|
{
|
2019-11-16 01:55:02 +08:00
|
|
|
impl.foreach_cell(data, [&](const std::string &cellname, const cell_dat_t &cd) {
|
|
|
|
IdString type = ctx->id(impl.get_cell_type(cd));
|
2019-11-16 01:43:32 +08:00
|
|
|
if (mods.count(type) && !mods.at(type).is_box()) {
|
|
|
|
// Module type is known; and not boxed. Import as a submodule by flattening hierarchy
|
|
|
|
import_submodule_cell(m, cellname, cd);
|
|
|
|
} else {
|
|
|
|
// Module type is unknown or boxes. Import as a leaf cell (nextpnr CellInfo)
|
|
|
|
import_leaf_cell(m, cellname, cd);
|
|
|
|
}
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create a top level input/output buffer
|
|
|
|
CellInfo *create_iobuf(NetInfo *net, PortType dir, const std::string &name)
|
|
|
|
{
|
|
|
|
// Skip IOBUF insertion if this is a design checkpoint (where they will already exist)
|
|
|
|
if (ctx->settings.count(ctx->id("synth")))
|
|
|
|
return nullptr;
|
|
|
|
IdString name_id = ctx->id(name);
|
|
|
|
if (ctx->cells.count(name_id))
|
|
|
|
log_error("Cell '%s' of type '%s' with the same name as a top-level IO is not allowed.\n", name.c_str(),
|
|
|
|
ctx->cells.at(name_id)->type.c_str(ctx));
|
|
|
|
CellInfo *iobuf = ctx->createCell(name_id, ctx->id("unknown_iob"));
|
|
|
|
// Copy attributes from net to IOB
|
|
|
|
for (auto &attr : net->attrs)
|
|
|
|
iobuf->attrs[attr.first] = attr.second;
|
|
|
|
// What we do now depends on port type
|
|
|
|
if (dir == PORT_IN) {
|
|
|
|
iobuf->type = ctx->id("$nextpnr_ibuf");
|
|
|
|
iobuf->addOutput(ctx->id("O"));
|
|
|
|
if (net->driver.cell != nullptr) {
|
|
|
|
CellInfo *drv = net->driver.cell;
|
|
|
|
if (drv->type != ctx->id("$nextpnr_iobuf"))
|
|
|
|
log_error("Net '%s' is multiply driven by cell port %s.%s and top level input '%s'.\n",
|
|
|
|
ctx->nameOf(net), ctx->nameOf(drv), ctx->nameOf(net->driver.port), name.c_str());
|
|
|
|
// Special case: input, etc, directly drives inout
|
|
|
|
// Use the input net of the inout instead
|
|
|
|
net = drv->ports.at(ctx->id("I")).net;
|
|
|
|
}
|
|
|
|
NPNR_ASSERT(net->driver.cell == nullptr);
|
|
|
|
// Connect IBUF output and net
|
2022-02-18 18:52:37 +08:00
|
|
|
iobuf->connectPort(ctx->id("O"), net);
|
2019-11-16 01:43:32 +08:00
|
|
|
} else if (dir == PORT_OUT) {
|
|
|
|
iobuf->type = ctx->id("$nextpnr_obuf");
|
|
|
|
iobuf->addInput(ctx->id("I"));
|
|
|
|
// Connect IBUF input and net
|
2022-02-18 18:52:37 +08:00
|
|
|
iobuf->connectPort(ctx->id("I"), net);
|
2019-11-16 01:43:32 +08:00
|
|
|
} else if (dir == PORT_INOUT) {
|
|
|
|
iobuf->type = ctx->id("$nextpnr_iobuf");
|
2021-02-12 05:33:55 +08:00
|
|
|
|
|
|
|
if (split_io) {
|
|
|
|
iobuf->addInput(ctx->id("I"));
|
|
|
|
iobuf->addOutput(ctx->id("O"));
|
|
|
|
// Need to bifurcate the net to avoid multiple drivers and split
|
|
|
|
// the input/output parts of an inout
|
|
|
|
// Create a new net connecting only the current net's driver and the IOBUF input
|
|
|
|
// Then use the IOBUF output to drive all of the current net's users
|
|
|
|
NetInfo *split_iobuf_i = ctx->createNet(unique_name("", "$" + name + "$iobuf_i", true));
|
|
|
|
auto drv = net->driver;
|
|
|
|
if (drv.cell != nullptr) {
|
2022-02-18 18:52:37 +08:00
|
|
|
drv.cell->disconnectPort(drv.port);
|
2021-02-12 05:33:55 +08:00
|
|
|
drv.cell->ports[drv.port].net = nullptr;
|
2022-02-18 18:52:37 +08:00
|
|
|
drv.cell->connectPort(drv.port, split_iobuf_i);
|
2021-02-12 05:33:55 +08:00
|
|
|
}
|
2022-02-18 18:52:37 +08:00
|
|
|
iobuf->connectPort(ctx->id("I"), split_iobuf_i);
|
2021-02-12 05:33:55 +08:00
|
|
|
NPNR_ASSERT(net->driver.cell == nullptr);
|
2022-02-18 18:52:37 +08:00
|
|
|
iobuf->connectPort(ctx->id("O"), net);
|
2021-02-12 05:33:55 +08:00
|
|
|
} else {
|
|
|
|
iobuf->addInout(ctx->id("IO"));
|
2022-02-18 18:52:37 +08:00
|
|
|
iobuf->connectPort(ctx->id("IO"), net);
|
2019-11-16 01:43:32 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
PortInfo pinfo;
|
|
|
|
pinfo.name = name_id;
|
|
|
|
pinfo.net = net;
|
|
|
|
pinfo.type = dir;
|
|
|
|
ctx->ports[pinfo.name] = pinfo;
|
2021-02-12 05:33:55 +08:00
|
|
|
ctx->port_cells[pinfo.name] = iobuf;
|
2019-11-16 01:43:32 +08:00
|
|
|
|
|
|
|
return iobuf;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Import ports of the top level module
|
|
|
|
void import_toplevel_ports(HierModuleState &m, const mod_dat_t &data)
|
|
|
|
{
|
2019-11-18 23:07:19 +08:00
|
|
|
// For correct handling of inout ports driving other ports
|
|
|
|
// first import non-inouts then import inouts so that they bifurcate correctly
|
|
|
|
for (bool inout : {false, true}) {
|
|
|
|
impl.foreach_port(data, [&](const std::string &portname, const mod_port_dat_t &pd) {
|
|
|
|
const auto &port_bv = impl.get_port_bits(pd);
|
|
|
|
int offset = impl.get_array_offset(pd);
|
|
|
|
bool is_upto = impl.is_array_upto(pd);
|
|
|
|
int width = impl.get_vector_length(port_bv);
|
|
|
|
PortType dir = impl.get_port_dir(pd);
|
|
|
|
if ((dir == PORT_INOUT) != inout)
|
|
|
|
return;
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
|
|
std::string pbit_name = get_bit_name(portname, i, width, offset, is_upto);
|
|
|
|
NetInfo *port_net = nullptr;
|
|
|
|
if (impl.is_vector_bit_constant(port_bv, i)) {
|
|
|
|
// Port bit is constant. Need to create a new constant net.
|
|
|
|
port_net =
|
|
|
|
create_constant_net(m, pbit_name + "$const", impl.get_vector_bit_constval(port_bv, i));
|
|
|
|
} else {
|
|
|
|
// Port bit is a signal. Need to create/get the associated net
|
|
|
|
port_net = create_or_get_net(m, impl.get_vector_bit_signal(port_bv, i));
|
|
|
|
}
|
|
|
|
create_iobuf(port_net, dir, pbit_name);
|
2019-11-16 01:43:32 +08:00
|
|
|
}
|
2019-11-18 23:07:19 +08:00
|
|
|
});
|
|
|
|
}
|
2019-11-15 04:01:45 +08:00
|
|
|
}
|
|
|
|
|
2019-11-13 20:11:17 +08:00
|
|
|
// Add a constant-driving VCC or GND cell to make a net constant
|
|
|
|
// (constval can be [01xz], x and z or no-ops)
|
|
|
|
int const_autoidx = 0;
|
|
|
|
void add_constant_driver(HierModuleState &m, NetInfo *net, char constval)
|
|
|
|
{
|
|
|
|
|
|
|
|
if (constval == 'x' || constval == 'z')
|
|
|
|
return; // 'x' or 'z' is the same as undriven
|
|
|
|
NPNR_ASSERT(constval == '0' || constval == '1');
|
|
|
|
IdString cell_name = unique_name(
|
|
|
|
m.prefix, net->name.str(ctx) + (constval == '1' ? "$VCC$" : "$GND$") + std::to_string(const_autoidx++),
|
|
|
|
false);
|
|
|
|
CellInfo *cc = ctx->createCell(cell_name, ctx->id(constval == '1' ? "VCC" : "GND"));
|
|
|
|
cc->ports[ctx->id("Y")].name = ctx->id("Y");
|
|
|
|
cc->ports[ctx->id("Y")].type = PORT_OUT;
|
|
|
|
if (net->driver.cell != nullptr)
|
|
|
|
log_error("Net '%s' is multiply driven by port %s.%s and constant '%c'\n", ctx->nameOf(net),
|
|
|
|
ctx->nameOf(net->driver.cell), ctx->nameOf(net->driver.port), constval);
|
2022-02-18 18:52:37 +08:00
|
|
|
cc->connectPort(ctx->id("Y"), net);
|
2019-11-13 20:11:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Merge two nets - e.g. if one net in a submodule bifurcates to two output bits and therefore two different
|
|
|
|
// parent nets
|
|
|
|
void merge_nets(NetInfo *base, NetInfo *mergee)
|
|
|
|
{
|
|
|
|
// Resolve drivers
|
|
|
|
if (mergee->driver.cell != nullptr) {
|
|
|
|
if (base->driver.cell != nullptr)
|
|
|
|
log_error("Attempting to merge nets '%s' and '%s' due to port connectivity; but this would result in a "
|
|
|
|
"multiply driven net\n",
|
|
|
|
ctx->nameOf(base), ctx->nameOf(mergee));
|
|
|
|
else {
|
|
|
|
mergee->driver.cell->ports[mergee->driver.port].net = base;
|
|
|
|
base->driver = mergee->driver;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Combine users
|
|
|
|
for (auto &usr : mergee->users) {
|
|
|
|
usr.cell->ports[usr.port].net = base;
|
2022-02-26 23:17:46 +08:00
|
|
|
usr.cell->ports[usr.port].user_idx = base->users.add(usr);
|
2019-11-13 20:11:17 +08:00
|
|
|
}
|
|
|
|
// Point aliases to the new net
|
|
|
|
for (IdString alias : mergee->aliases) {
|
|
|
|
ctx->net_aliases[alias] = base->name;
|
|
|
|
base->aliases.push_back(alias);
|
|
|
|
}
|
|
|
|
// Create a new alias from mergee's name to new base name
|
|
|
|
ctx->net_aliases[mergee->name] = base->name;
|
|
|
|
// Update flat index of nets
|
2019-11-13 21:51:28 +08:00
|
|
|
for (auto old_idx : net_old_indices.at(mergee->udata)) {
|
2019-11-14 02:52:13 +08:00
|
|
|
net_old_indices.at(base->udata).push_back(old_idx);
|
2019-11-13 21:51:28 +08:00
|
|
|
net_flatindex.at(old_idx) = base;
|
|
|
|
}
|
2019-11-14 02:52:13 +08:00
|
|
|
net_old_indices.at(base->udata).push_back(mergee->udata);
|
2019-11-13 20:11:17 +08:00
|
|
|
net_flatindex.at(mergee->udata) = base;
|
2019-11-13 21:51:28 +08:00
|
|
|
net_old_indices.at(mergee->udata).clear();
|
2019-11-13 20:11:17 +08:00
|
|
|
// Remove merged net from context
|
|
|
|
ctx->nets.erase(mergee->name);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Import connections between a submodule and its parent
|
|
|
|
void import_port_connections(HierModuleState &m, const mod_dat_t &data)
|
|
|
|
{
|
|
|
|
impl.foreach_port(data, [&](const std::string &name, const mod_port_dat_t &port) {
|
|
|
|
// CHECK: should disconnected module inputs really just be skipped; or is it better
|
|
|
|
// to insert a ground driver?
|
|
|
|
if (!m.port_to_bus.count(ctx->id(name)))
|
|
|
|
return;
|
|
|
|
auto &p2b = m.port_to_bus.at(ctx->id(name));
|
|
|
|
// Get direction and vector of port bits
|
|
|
|
PortType dir = impl.get_port_dir(port);
|
|
|
|
const auto &bv = impl.get_port_bits(port);
|
|
|
|
int bv_size = impl.get_vector_length(bv);
|
|
|
|
// Iterate over bits of port; making connections
|
|
|
|
for (int i = 0; i < std::min<int>(bv_size, p2b.size()); i++) {
|
2019-11-13 21:51:28 +08:00
|
|
|
int conn_net = p2b.at(i);
|
|
|
|
if (conn_net == -1)
|
2019-11-13 20:11:17 +08:00
|
|
|
continue;
|
2019-11-13 21:51:28 +08:00
|
|
|
NetInfo *conn_ni = net_flatindex.at(conn_net);
|
|
|
|
NPNR_ASSERT(conn_ni != nullptr);
|
2019-11-13 20:11:17 +08:00
|
|
|
if (impl.is_vector_bit_constant(bv, i)) {
|
|
|
|
// It is a constant, we might need to insert a constant driver here to drive the corresponding
|
|
|
|
// net in the parent
|
|
|
|
char constval = impl.get_vector_bit_constval(bv, i);
|
|
|
|
// Inputs cannot be driving a constant back to the parent
|
|
|
|
if (dir == PORT_IN)
|
|
|
|
log_error("Input port %s%s[%d] cannot be driving a constant '%c'.\n", m.prefix.c_str(),
|
2019-11-16 01:55:02 +08:00
|
|
|
name.c_str(), i, constval);
|
2019-11-13 20:11:17 +08:00
|
|
|
// Insert the constant driver
|
2019-11-13 21:51:28 +08:00
|
|
|
add_constant_driver(m, conn_ni, constval);
|
2019-11-13 20:11:17 +08:00
|
|
|
} else {
|
|
|
|
// If not driving a constant; simply make the port bit net index in the submodule correspond
|
|
|
|
// to connected net in the parent module
|
2019-11-13 21:51:28 +08:00
|
|
|
int &submod_net = m.net_by_idx(impl.get_vector_bit_signal(bv, i));
|
|
|
|
if (submod_net == -1) {
|
|
|
|
// A net at this index doesn't yet exist
|
|
|
|
// We can simply set this index to point to the net in the parent
|
|
|
|
submod_net = conn_net;
|
|
|
|
} else {
|
|
|
|
// A net at this index already exists (this would usually be a submodule net
|
|
|
|
// connected to more than one I/O port)
|
|
|
|
merge_nets(net_flatindex.at(submod_net), net_flatindex.at(conn_net));
|
|
|
|
}
|
2019-11-13 20:11:17 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
});
|
|
|
|
}
|
2019-11-12 19:33:49 +08:00
|
|
|
};
|
|
|
|
} // namespace
|
|
|
|
|
2019-11-18 23:07:19 +08:00
|
|
|
NEXTPNR_NAMESPACE_END
|