351 lines
13 KiB
C++
351 lines
13 KiB
C++
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2019-2023 Myrtle Shah <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <boost/optional.hpp>
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#include <iterator>
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#include <queue>
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#include <unordered_set>
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#include "chain_utils.h"
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#include "design_utils.h"
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#include "extra_data.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "pack.h"
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#include "pins.h"
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#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
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#include "himbaechel_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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BelId XilinxPacker::find_bel_with_short_route(WireId source, IdString beltype, IdString belpin)
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{
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if (source == WireId())
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return BelId();
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const size_t max_visit = 50000; // effort/runtime tradeoff
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pool<WireId> visited;
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std::queue<WireId> visit;
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visit.push(source);
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while (!visit.empty() && visited.size() < max_visit) {
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WireId cursor = visit.front();
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visit.pop();
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for (auto bp : ctx->getWireBelPins(cursor))
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if (bp.pin == belpin && ctx->getBelType(bp.bel) == beltype && ctx->checkBelAvail(bp.bel))
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return bp.bel;
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for (auto pip : ctx->getPipsDownhill(cursor)) {
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WireId dst = ctx->getPipDstWire(pip);
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if (visited.count(dst))
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continue;
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visit.push(dst);
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visited.insert(dst);
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}
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}
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return BelId();
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}
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void XilinxPacker::try_preplace(CellInfo *cell, IdString port)
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{
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if (cell->attrs.count(id_BEL) || cell->bel != BelId())
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return;
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NetInfo *n = cell->getPort(port);
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if (n == nullptr || n->driver.cell == nullptr)
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return;
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CellInfo *drv = n->driver.cell;
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BelId drv_bel = drv->bel;
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if (drv_bel == BelId())
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return;
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WireId drv_wire = ctx->getBelPinWire(drv_bel, n->driver.port);
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if (drv_wire == WireId())
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return;
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BelId tgt = find_bel_with_short_route(drv_wire, cell->type, port);
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if (tgt != BelId()) {
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ctx->bindBel(tgt, cell, STRENGTH_LOCKED);
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log_info(" Constrained %s '%s' to bel '%s' based on dedicated routing\n", cell->type.c_str(ctx),
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ctx->nameOf(cell), ctx->nameOfBel(tgt));
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}
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}
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void XilinxPacker::preplace_unique(CellInfo *cell)
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{
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if (cell->attrs.count(id_BEL) || cell->bel != BelId())
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return;
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for (auto bel : ctx->getBels()) {
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if (ctx->checkBelAvail(bel) && ctx->getBelType(bel) == cell->type) {
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ctx->bindBel(bel, cell, STRENGTH_LOCKED);
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return;
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}
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}
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}
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void XC7Packer::prepare_clocking()
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{
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log_info("Preparing clocking...\n");
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dict<IdString, IdString> upgrade;
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upgrade[id_MMCME2_BASE] = id_MMCME2_ADV;
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upgrade[id_PLLE2_BASE] = id_PLLE2_ADV;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (upgrade.count(ci->type)) {
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IdString new_type = upgrade.at(ci->type);
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ci->type = new_type;
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} else if (ci->type == id_BUFG) {
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ci->type = id_BUFGCTRL;
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ci->renamePort(id_I, id_I0);
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tie_port(ci, "CE0", true, true);
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tie_port(ci, "S0", true, true);
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tie_port(ci, "S1", false, true);
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tie_port(ci, "IGNORE0", true, true);
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} else if (ci->type == id_BUFGCE) {
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ci->type = id_BUFGCTRL;
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ci->renamePort(id_I, id_I0);
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ci->renamePort(id_CE, id_CE0);
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tie_port(ci, "S0", true, true);
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tie_port(ci, "S1", false, true);
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tie_port(ci, "IGNORE0", true, true);
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}
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}
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}
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void XC7Packer::pack_plls()
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{
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log_info("Packing PLLs...\n");
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auto set_default = [](CellInfo *ci, IdString param, const Property &value) {
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if (!ci->params.count(param))
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ci->params[param] = value;
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};
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dict<IdString, XFormRule> pll_rules;
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pll_rules[id_MMCME2_ADV].new_type = id_MMCME2_ADV_MMCME2_ADV;
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pll_rules[id_PLLE2_ADV].new_type = id_PLLE2_ADV_PLLE2_ADV;
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generic_xform(pll_rules);
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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// Preplace PLLs to make use of dedicated/short routing paths
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if (ci->type.in(id_MMCM_MMCM_TOP, id_PLL_PLL_TOP))
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try_preplace(ci, id_CLKIN1);
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if (ci->type == id_MMCM_MMCM_TOP) {
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// Fixup parameters
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for (int i = 1; i <= 2; i++)
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set_default(ci, ctx->idf("CLKIN%d_PERIOD", i), Property("0.0"));
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for (int i = 0; i <= 6; i++) {
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set_default(ci, ctx->idf("CLKOUT%d_CASCADE", i), Property("FALSE"));
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set_default(ci, ctx->idf("CLKOUT%d_DIVIDE", i), Property(1));
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set_default(ci, ctx->idf("CLKOUT%d_DUTY_CYCLE", i), Property("0.5"));
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set_default(ci, ctx->idf("CLKOUT%d_PHASE", i), Property(0));
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set_default(ci, ctx->idf("CLKOUT%d_USE_FINE_PS", i), Property("FALSE"));
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}
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set_default(ci, id_COMPENSATION, Property("INTERNAL"));
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// Fixup routing
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if (str_or_default(ci->params, id_COMPENSATION, "INTERNAL") == "INTERNAL") {
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ci->disconnectPort(id_CLKFBIN);
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ci->connectPort(id_CLKFBIN, ctx->nets.at(ctx->id("$PACKER_VCC_NET")).get());
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}
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}
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}
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}
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void XC7Packer::pack_gbs()
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{
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log_info("Packing global buffers...\n");
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dict<IdString, XFormRule> gb_rules;
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gb_rules[id_BUFGCTRL].new_type = id_BUFGCTRL;
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gb_rules[id_BUFGCTRL].new_type = id_BUFGCTRL;
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generic_xform(gb_rules);
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// Make sure prerequisites are set up first
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type == id_PS7_PS7)
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preplace_unique(ci);
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if (ci->type.in(id_PSEUDO_GND, id_PSEUDO_VCC))
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preplace_unique(ci);
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}
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// Preplace global buffers to make use of dedicated/short routing
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type == id_BUFGCTRL)
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try_preplace(ci, id_I0);
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if (ci->type == id_BUFG_BUFG)
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try_preplace(ci, id_I);
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}
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}
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void XC7Packer::pack_clocking()
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{
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pack_plls();
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pack_gbs();
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}
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void XilinxImpl::route_clocks()
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{
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log_info("Routing global clocks...\n");
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// Special pass for faster routing of global clock psuedo-net
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for (auto &net : ctx->nets) {
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NetInfo *clk_net = net.second.get();
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if (!clk_net->driver.cell)
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continue;
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// check if we have a global clock net, skip otherwise
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bool is_global = false;
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if ((clk_net->driver.cell->type.in(id_BUFGCTRL, id_BUFCE_BUFG_PS, id_BUFCE_BUFCE, id_BUFGCE_DIV_BUFGCE_DIV)) &&
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clk_net->driver.port == id_O)
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is_global = true;
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else if (clk_net->driver.cell->type == id_PLLE2_ADV_PLLE2_ADV && clk_net->users.entries() == 1 &&
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((*clk_net->users.begin()).cell->type.in(id_BUFGCTRL, id_BUFCE_BUFCE, id_BUFGCE_DIV_BUFGCE_DIV)))
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is_global = true;
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else if (clk_net->users.entries() == 1 && (*clk_net->users.begin()).cell->type == id_PLLE2_ADV_PLLE2_ADV &&
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(*clk_net->users.begin()).port == id_CLKIN1)
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is_global = true;
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if (!is_global)
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continue;
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log_info(" routing clock '%s'\n", clk_net->name.c_str(ctx));
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ctx->bindWire(ctx->getNetinfoSourceWire(clk_net), clk_net, STRENGTH_LOCKED);
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for (auto &usr : clk_net->users) {
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std::queue<WireId> visit;
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dict<WireId, PipId> backtrace;
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WireId dest = WireId();
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auto sink_wire = ctx->getNetinfoSinkWire(clk_net, usr, 0);
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if (ctx->debug) {
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auto sink_wire_name = "(uninitialized)";
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if (sink_wire != WireId())
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sink_wire_name = ctx->nameOfWire(sink_wire);
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log_info(" routing arc to %s.%s (wire %s):\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx),
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sink_wire_name);
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}
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visit.push(sink_wire);
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while (!visit.empty()) {
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WireId curr = visit.front();
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visit.pop();
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if (ctx->getBoundWireNet(curr) == clk_net) {
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dest = curr;
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break;
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}
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for (auto uh : ctx->getPipsUphill(curr)) {
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if (!ctx->checkPipAvail(uh))
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continue;
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WireId src = ctx->getPipSrcWire(uh);
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if (backtrace.count(src))
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continue;
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IdString intent = ctx->getWireType(src);
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if (intent.in(id_NODE_DOUBLE, id_NODE_HLONG, id_NODE_HQUAD, id_NODE_VLONG, id_NODE_VQUAD,
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id_NODE_SINGLE, id_NODE_CLE_OUTPUT, id_NODE_OPTDELAY, id_BENTQUAD, id_DOUBLE,
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id_HLONG, id_HQUAD, id_OPTDELAY, id_SINGLE, id_VLONG, id_VLONG12, id_VQUAD,
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id_PINBOUNCE))
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continue;
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if (!ctx->checkWireAvail(src) && ctx->getBoundWireNet(src) != clk_net)
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continue;
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backtrace[src] = uh;
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visit.push(src);
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}
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}
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if (dest == WireId()) {
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log_info(" failed to find a route using dedicated resources.\n");
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if (clk_net->users.entries() == 1 && (*clk_net->users.begin()).cell->type == id_PLLE2_ADV_PLLE2_ADV &&
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(*clk_net->users.begin()).port == id_CLKIN1) {
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// Due to some missing pips, currently special case more lenient solution
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std::queue<WireId> empty;
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std::swap(visit, empty);
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backtrace.clear();
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visit.push(sink_wire);
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while (!visit.empty()) {
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WireId curr = visit.front();
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visit.pop();
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if (ctx->getBoundWireNet(curr) == clk_net) {
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dest = curr;
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break;
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}
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for (auto uh : ctx->getPipsUphill(curr)) {
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if (!ctx->checkPipAvail(uh))
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continue;
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WireId src = ctx->getPipSrcWire(uh);
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if (backtrace.count(src))
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continue;
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if (!ctx->checkWireAvail(src) && ctx->getBoundWireNet(src) != clk_net)
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continue;
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backtrace[src] = uh;
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visit.push(src);
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}
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}
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if (dest == WireId())
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continue;
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} else {
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continue;
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}
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}
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while (backtrace.count(dest)) {
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auto uh = backtrace[dest];
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dest = ctx->getPipDstWire(uh);
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if (ctx->getBoundWireNet(dest) == clk_net) {
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NPNR_ASSERT(clk_net->wires.at(dest).pip == uh);
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break;
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}
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if (ctx->debug)
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log_info(" bind pip %s --> %s\n", ctx->nameOfPip(uh), ctx->nameOfWire(dest));
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ctx->bindPip(uh, clk_net, STRENGTH_LOCKED);
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}
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}
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}
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#if 0
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for (auto& net : nets) {
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NetInfo *ni = net.second.get();
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for (auto &usr : ni->users) {
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if (usr.cell->type != id_BUFGCTRL || usr.port != id_I0)
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continue;
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WireId dst = getCtx()->getNetinfoSinkWire(ni, usr, 0);
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std::queue<WireId> visit;
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visit.push(dst);
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int i = 0;
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while(!visit.empty() && i < 5000) {
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WireId curr = visit.front();
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visit.pop();
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log(" %s\n", nameOfWire(curr));
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for (auto pip : getPipsUphill(curr)) {
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auto &pd = locInfo(pip).pip_data[pip.index];
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log_info(" p %s sr %s (t %d s %d sv %d)\n", nameOfPip(pip), nameOfWire(getPipSrcWire(pip)), pd.flags, pd.site, pd.site_variant);
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if (!checkPipAvail(pip)) {
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log(" p unavail\n");
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continue;
|
||
|
|
}
|
||
|
|
WireId src = getPipSrcWire(pip);
|
||
|
|
if (!checkWireAvail(src)) {
|
||
|
|
log(" w unavail (%s)\n", nameOf(getBoundWireNet(src)));
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
log_info(" p %s s %s\n", nameOfPip(pip), nameOfWire(src));
|
||
|
|
visit.push(src);
|
||
|
|
}
|
||
|
|
++i;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
NEXTPNR_NAMESPACE_END
|