90 lines
3.0 KiB
C++
90 lines
3.0 KiB
C++
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "arch_place.h"
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static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
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{
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bool dffs_exist = false, dffs_neg = false;
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const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
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std::unordered_set<const NetInfo *> locals;
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for (auto cell : cells) {
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if (std::stoi(cell->params.at("DFF_ENABLE"))) {
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if (!dffs_exist) {
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dffs_exist = true;
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cen = cell->ports.at("CEN").net;
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clk = cell->ports.at("CLK").net;
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sr = cell->ports.at("SR").net;
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locals.insert(cen);
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locals.insert(clk);
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locals.insert(sr);
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if (std::stoi(cell->params.at("NEG_CLK"))) {
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dffs_neg = true;
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}
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} else {
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if (cen != cell->ports.at("CEN").net)
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return false;
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if (clk == cell->ports.at("CLK").net)
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return false;
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if (sr != cell->ports.at("SR").net)
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return false;
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if (dffs_neg != bool(std::stoi(cell->params.at("NEG_CLK"))))
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return false;
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}
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}
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locals.insert(cell->ports.at("I0").net);
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locals.insert(cell->ports.at("I1").net);
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locals.insert(cell->ports.at("I2").net);
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locals.insert(cell->ports.at("I3").net);
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}
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locals.erase(nullptr); // disconnected signals don't use local tracks
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return locals.size() <= 32;
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}
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bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
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{
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const Chip &chip = design->chip;
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if (cell->type == "ICESTORM_LC") {
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assert(chip.getBelType(bel) == TYPE_ICESTORM_LC);
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std::vector<const CellInfo *> cells;
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for (auto bel_other : chip.getBelsAtSameTile(bel)) {
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IdString cell_other = chip.getBelCell(bel_other, false);
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if (cell_other != IdString()) {
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const CellInfo *ci_other = design->cells[cell_other];
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cells.push_back(ci_other);
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}
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}
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cells.push_back(cell);
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return logicCellsCompatible(cells);
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} else {
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// TODO: IO cell clock checks
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return true;
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}
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}
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