2023-06-28 08:16:29 +08:00
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X(C0)
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X(D0)
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X(A1)
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X(A3)
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X(D3)
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X(D4)
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X(A5)
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X(D6)
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X(A7)
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X(C7)
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X(D7)
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X(F0)
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X(F1)
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X(F3)
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X(F4)
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X(F5)
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X(F6)
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X(F7)
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X(Q0)
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X(Q5)
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X(Q6)
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X(Q7)
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X(OF0)
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X(OF1)
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X(OF2)
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X(OF3)
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X(OF4)
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X(OF5)
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X(OF6)
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X(OF7)
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X(X01)
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X(X02)
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X(X03)
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X(X04)
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X(X05)
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X(X06)
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X(X07)
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X(X08)
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X(N100)
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X(SN10)
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X(SN20)
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X(N130)
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X(S100)
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X(S130)
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X(E100)
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X(EW10)
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X(EW20)
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X(E130)
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X(W100)
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X(W130)
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X(N200)
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X(N210)
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X(N220)
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X(N230)
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X(N240)
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X(N250)
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X(N260)
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X(N270)
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X(S200)
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X(S210)
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X(S220)
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X(S230)
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X(S240)
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X(S250)
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X(S260)
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X(S270)
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X(E200)
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X(E210)
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X(E220)
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X(E230)
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X(E240)
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X(E250)
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X(E260)
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X(E270)
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X(W200)
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X(W210)
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X(W220)
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X(W230)
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X(W240)
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X(W250)
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X(W260)
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X(W270)
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X(N800)
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X(N810)
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X(N820)
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X(N830)
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X(S800)
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X(S810)
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X(S820)
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X(S830)
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X(E800)
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X(E810)
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X(E820)
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X(E830)
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X(W800)
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X(W810)
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X(W820)
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X(W830)
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2024-11-27 16:57:34 +08:00
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X(MCLK)
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2023-06-28 08:16:29 +08:00
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X(CLK0)
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X(CLK1)
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X(CLK2)
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X(LSR0)
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X(LSR1)
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X(LSR2)
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X(CE0)
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X(CE1)
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X(CE2)
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X(SEL0)
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X(SEL1)
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X(SEL2)
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X(SEL3)
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X(SEL4)
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X(SEL5)
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X(SEL6)
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X(SEL7)
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X(N101)
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X(N131)
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X(S101)
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X(S131)
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X(E101)
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X(E131)
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X(W101)
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X(W131)
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X(N201)
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X(N211)
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X(N221)
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X(N231)
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X(N241)
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X(N251)
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X(N261)
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X(N271)
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X(S201)
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X(S211)
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X(S221)
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X(S231)
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X(S241)
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X(S251)
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X(S261)
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X(S271)
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X(E201)
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X(E211)
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X(E221)
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X(E231)
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X(E241)
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X(E251)
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X(E261)
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X(E271)
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X(W201)
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X(W211)
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X(W221)
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X(W231)
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X(W241)
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X(W251)
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X(W261)
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X(W271)
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X(N202)
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X(N212)
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X(N222)
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X(N232)
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X(N242)
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X(N252)
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X(N262)
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X(N272)
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X(S202)
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X(S212)
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X(S222)
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X(S232)
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X(S242)
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X(S252)
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X(S262)
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X(S272)
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X(E202)
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X(E212)
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X(E222)
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X(E232)
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X(E242)
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X(E252)
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X(E262)
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X(E272)
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X(W202)
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X(W212)
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X(W222)
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X(W232)
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X(W242)
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X(W252)
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X(W262)
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X(W272)
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X(N804)
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X(N814)
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X(N824)
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X(N834)
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X(S804)
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X(S814)
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X(S824)
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X(S834)
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X(E804)
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X(E814)
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X(E824)
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X(E834)
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X(W804)
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X(W814)
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X(W824)
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X(W834)
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X(N808)
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X(N818)
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X(N828)
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X(N838)
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X(S808)
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X(S818)
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X(S828)
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X(S838)
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X(E808)
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X(E818)
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X(E828)
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X(E838)
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X(W808)
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X(W818)
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X(W828)
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X(W838)
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X(E110)
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X(W110)
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X(E120)
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X(W120)
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X(S110)
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X(N110)
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X(S120)
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X(N120)
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X(E111)
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X(W111)
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X(E121)
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X(W121)
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X(S111)
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X(N111)
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X(S121)
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X(N121)
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X(LB01)
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X(LB11)
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X(LB21)
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X(LB31)
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X(LB41)
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X(LB51)
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X(LB61)
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X(LB71)
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X(GB00)
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X(GB10)
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X(GB20)
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X(GB30)
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X(GB40)
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X(GB50)
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X(GB60)
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X(GB70)
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X(VCC)
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X(VSS)
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X(LT00)
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X(LT10)
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X(LT20)
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X(LT30)
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X(LT02)
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X(LT13)
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X(LT01)
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X(LT04)
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X(LBO0)
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X(LBO1)
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X(SS00)
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X(SS40)
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X(GT00)
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X(GT10)
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X(GBO0)
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X(GBO1)
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X(DI0)
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X(DI1)
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X(DI2)
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X(DI3)
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X(DI4)
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X(DI5)
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X(DI6)
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X(DI7)
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X(CIN0)
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X(CIN1)
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X(CIN2)
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X(CIN3)
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X(CIN4)
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X(CIN5)
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X(COUT0)
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X(COUT1)
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X(COUT2)
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X(COUT3)
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X(COUT4)
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X(COUT5)
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X(VREN)
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// wires
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// SN
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X(S10)
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X(S10_loop0)
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X(S13)
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X(S13_loop0)
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X(N10)
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X(N10_loop0)
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X(N13)
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X(N13_loop0)
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X(SN10_loop_n)
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X(SN10_loop_s)
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X(SN20_loop_n)
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X(SN20_loop_s)
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X(S20)
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X(S20_loop0)
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X(S20_loop1)
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X(S21)
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X(S21_loop0)
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X(S21_loop1)
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X(S22)
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X(S22_loop0)
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X(S22_loop1)
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X(S23)
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X(S23_loop0)
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X(S23_loop1)
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X(S24)
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X(S24_loop0)
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X(S24_loop1)
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X(S25)
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X(S25_loop0)
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X(S25_loop1)
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X(S26)
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X(S26_loop0)
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X(S26_loop1)
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X(S27)
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X(S27_loop0)
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X(S27_loop1)
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X(N20)
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X(N20_loop0)
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X(N20_loop1)
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X(N21)
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X(N21_loop0)
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X(N21_loop1)
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X(N22)
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X(N22_loop0)
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X(N22_loop1)
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|
|
X(N23)
|
|
|
|
|
X(N23_loop0)
|
|
|
|
|
X(N23_loop1)
|
|
|
|
|
X(N24)
|
|
|
|
|
X(N24_loop0)
|
|
|
|
|
X(N24_loop1)
|
|
|
|
|
X(N25)
|
|
|
|
|
X(N25_loop0)
|
|
|
|
|
X(N25_loop1)
|
|
|
|
|
X(N26)
|
|
|
|
|
X(N26_loop0)
|
|
|
|
|
X(N26_loop1)
|
|
|
|
|
X(N27)
|
|
|
|
|
X(N27_loop0)
|
|
|
|
|
X(N27_loop1)
|
|
|
|
|
X(S80)
|
|
|
|
|
X(S80_loop0)
|
|
|
|
|
X(S80_loop1)
|
|
|
|
|
X(S80_loop2)
|
|
|
|
|
X(S80_loop3)
|
|
|
|
|
X(S80_loop4)
|
|
|
|
|
X(S80_loop5)
|
|
|
|
|
X(S80_loop6)
|
|
|
|
|
X(S80_loop7)
|
|
|
|
|
X(N80)
|
|
|
|
|
X(N80_loop0)
|
|
|
|
|
X(N80_loop1)
|
|
|
|
|
X(N80_loop2)
|
|
|
|
|
X(N80_loop3)
|
|
|
|
|
X(N80_loop4)
|
|
|
|
|
X(N80_loop5)
|
|
|
|
|
X(N80_loop6)
|
|
|
|
|
X(N80_loop7)
|
|
|
|
|
X(S81)
|
|
|
|
|
X(S81_loop0)
|
|
|
|
|
X(S81_loop1)
|
|
|
|
|
X(S81_loop2)
|
|
|
|
|
X(S81_loop3)
|
|
|
|
|
X(S81_loop4)
|
|
|
|
|
X(S81_loop5)
|
|
|
|
|
X(S81_loop6)
|
|
|
|
|
X(S81_loop7)
|
|
|
|
|
X(N81)
|
|
|
|
|
X(N81_loop0)
|
|
|
|
|
X(N81_loop1)
|
|
|
|
|
X(N81_loop2)
|
|
|
|
|
X(N81_loop3)
|
|
|
|
|
X(N81_loop4)
|
|
|
|
|
X(N81_loop5)
|
|
|
|
|
X(N81_loop6)
|
|
|
|
|
X(N81_loop7)
|
|
|
|
|
X(S82)
|
|
|
|
|
X(S82_loop0)
|
|
|
|
|
X(S82_loop1)
|
|
|
|
|
X(S82_loop2)
|
|
|
|
|
X(S82_loop3)
|
|
|
|
|
X(S82_loop4)
|
|
|
|
|
X(S82_loop5)
|
|
|
|
|
X(S82_loop6)
|
|
|
|
|
X(S82_loop7)
|
|
|
|
|
X(N82)
|
|
|
|
|
X(N82_loop0)
|
|
|
|
|
X(N82_loop1)
|
|
|
|
|
X(N82_loop2)
|
|
|
|
|
X(N82_loop3)
|
|
|
|
|
X(N82_loop4)
|
|
|
|
|
X(N82_loop5)
|
|
|
|
|
X(N82_loop6)
|
|
|
|
|
X(N82_loop7)
|
|
|
|
|
X(S83)
|
|
|
|
|
X(S83_loop0)
|
|
|
|
|
X(S83_loop1)
|
|
|
|
|
X(S83_loop2)
|
|
|
|
|
X(S83_loop3)
|
|
|
|
|
X(S83_loop4)
|
|
|
|
|
X(S83_loop5)
|
|
|
|
|
X(S83_loop6)
|
|
|
|
|
X(S83_loop7)
|
|
|
|
|
X(N83)
|
|
|
|
|
X(N83_loop0)
|
|
|
|
|
X(N83_loop1)
|
|
|
|
|
X(N83_loop2)
|
|
|
|
|
X(N83_loop3)
|
|
|
|
|
X(N83_loop4)
|
|
|
|
|
X(N83_loop5)
|
|
|
|
|
X(N83_loop6)
|
|
|
|
|
X(N83_loop7)
|
|
|
|
|
|
|
|
|
|
// WE
|
|
|
|
|
X(E10)
|
|
|
|
|
X(E10_loop0)
|
|
|
|
|
X(E13)
|
|
|
|
|
X(E13_loop0)
|
|
|
|
|
X(W10)
|
|
|
|
|
X(W10_loop0)
|
|
|
|
|
X(W13)
|
|
|
|
|
X(W13_loop0)
|
|
|
|
|
X(EW10_loop_w)
|
|
|
|
|
X(EW10_loop_e)
|
|
|
|
|
X(EW20_loop_w)
|
|
|
|
|
X(EW20_loop_e)
|
|
|
|
|
//
|
|
|
|
|
X(E20)
|
|
|
|
|
X(E20_loop0)
|
|
|
|
|
X(E20_loop1)
|
|
|
|
|
X(E21)
|
|
|
|
|
X(E21_loop0)
|
|
|
|
|
X(E21_loop1)
|
|
|
|
|
X(E22)
|
|
|
|
|
X(E22_loop0)
|
|
|
|
|
X(E22_loop1)
|
|
|
|
|
X(E23)
|
|
|
|
|
X(E23_loop0)
|
|
|
|
|
X(E23_loop1)
|
|
|
|
|
X(E24)
|
|
|
|
|
X(E24_loop0)
|
|
|
|
|
X(E24_loop1)
|
|
|
|
|
X(E25)
|
|
|
|
|
X(E25_loop0)
|
|
|
|
|
X(E25_loop1)
|
|
|
|
|
X(E26)
|
|
|
|
|
X(E26_loop0)
|
|
|
|
|
X(E26_loop1)
|
|
|
|
|
X(E27)
|
|
|
|
|
X(E27_loop0)
|
|
|
|
|
X(E27_loop1)
|
|
|
|
|
X(W20)
|
|
|
|
|
X(W20_loop0)
|
|
|
|
|
X(W20_loop1)
|
|
|
|
|
X(W21)
|
|
|
|
|
X(W21_loop0)
|
|
|
|
|
X(W21_loop1)
|
|
|
|
|
X(W22)
|
|
|
|
|
X(W22_loop0)
|
|
|
|
|
X(W22_loop1)
|
|
|
|
|
X(W23)
|
|
|
|
|
X(W23_loop0)
|
|
|
|
|
X(W23_loop1)
|
|
|
|
|
X(W24)
|
|
|
|
|
X(W24_loop0)
|
|
|
|
|
X(W24_loop1)
|
|
|
|
|
X(W25)
|
|
|
|
|
X(W25_loop0)
|
|
|
|
|
X(W25_loop1)
|
|
|
|
|
X(W26)
|
|
|
|
|
X(W26_loop0)
|
|
|
|
|
X(W26_loop1)
|
|
|
|
|
X(W27)
|
|
|
|
|
X(W27_loop0)
|
|
|
|
|
X(W27_loop1)
|
|
|
|
|
//
|
|
|
|
|
X(E80)
|
|
|
|
|
X(E80_loop0)
|
|
|
|
|
X(E80_loop1)
|
|
|
|
|
X(E80_loop2)
|
|
|
|
|
X(E80_loop3)
|
|
|
|
|
X(E80_loop4)
|
|
|
|
|
X(E80_loop5)
|
|
|
|
|
X(E80_loop6)
|
|
|
|
|
X(E80_loop7)
|
|
|
|
|
X(W80)
|
|
|
|
|
X(W80_loop0)
|
|
|
|
|
X(W80_loop1)
|
|
|
|
|
X(W80_loop2)
|
|
|
|
|
X(W80_loop3)
|
|
|
|
|
X(W80_loop4)
|
|
|
|
|
X(W80_loop5)
|
|
|
|
|
X(W80_loop6)
|
|
|
|
|
X(W80_loop7)
|
|
|
|
|
X(E81)
|
|
|
|
|
X(E81_loop0)
|
|
|
|
|
X(E81_loop1)
|
|
|
|
|
X(E81_loop2)
|
|
|
|
|
X(E81_loop3)
|
|
|
|
|
X(E81_loop4)
|
|
|
|
|
X(E81_loop5)
|
|
|
|
|
X(E81_loop6)
|
|
|
|
|
X(E81_loop7)
|
|
|
|
|
X(W81)
|
|
|
|
|
X(W81_loop0)
|
|
|
|
|
X(W81_loop1)
|
|
|
|
|
X(W81_loop2)
|
|
|
|
|
X(W81_loop3)
|
|
|
|
|
X(W81_loop4)
|
|
|
|
|
X(W81_loop5)
|
|
|
|
|
X(W81_loop6)
|
|
|
|
|
X(W81_loop7)
|
|
|
|
|
X(E82)
|
|
|
|
|
X(E82_loop0)
|
|
|
|
|
X(E82_loop1)
|
|
|
|
|
X(E82_loop2)
|
|
|
|
|
X(E82_loop3)
|
|
|
|
|
X(E82_loop4)
|
|
|
|
|
X(E82_loop5)
|
|
|
|
|
X(E82_loop6)
|
|
|
|
|
X(E82_loop7)
|
|
|
|
|
X(W82)
|
|
|
|
|
X(W82_loop0)
|
|
|
|
|
X(W82_loop1)
|
|
|
|
|
X(W82_loop2)
|
|
|
|
|
X(W82_loop3)
|
|
|
|
|
X(W82_loop4)
|
|
|
|
|
X(W82_loop5)
|
|
|
|
|
X(W82_loop6)
|
|
|
|
|
X(W82_loop7)
|
|
|
|
|
X(E83)
|
|
|
|
|
X(E83_loop0)
|
|
|
|
|
X(E83_loop1)
|
|
|
|
|
X(E83_loop2)
|
|
|
|
|
X(E83_loop3)
|
|
|
|
|
X(E83_loop4)
|
|
|
|
|
X(E83_loop5)
|
|
|
|
|
X(E83_loop6)
|
|
|
|
|
X(E83_loop7)
|
|
|
|
|
X(W83)
|
|
|
|
|
X(W83_loop0)
|
|
|
|
|
X(W83_loop1)
|
|
|
|
|
X(W83_loop2)
|
|
|
|
|
X(W83_loop3)
|
|
|
|
|
X(W83_loop4)
|
|
|
|
|
X(W83_loop5)
|
|
|
|
|
X(W83_loop6)
|
|
|
|
|
X(W83_loop7)
|
|
|
|
|
|
|
|
|
|
// spines
|
|
|
|
|
X(SPINE0)
|
|
|
|
|
X(SPINE1)
|
|
|
|
|
X(SPINE2)
|
|
|
|
|
X(SPINE3)
|
|
|
|
|
X(SPINE4)
|
|
|
|
|
X(SPINE5)
|
|
|
|
|
X(SPINE6)
|
|
|
|
|
X(SPINE7)
|
|
|
|
|
X(SPINE8)
|
|
|
|
|
X(SPINE9)
|
|
|
|
|
X(SPINE10)
|
|
|
|
|
X(SPINE11)
|
|
|
|
|
X(SPINE12)
|
|
|
|
|
X(SPINE13)
|
|
|
|
|
X(SPINE14)
|
|
|
|
|
X(SPINE15)
|
|
|
|
|
X(SPINE16)
|
|
|
|
|
X(SPINE17)
|
|
|
|
|
X(SPINE18)
|
|
|
|
|
X(SPINE19)
|
|
|
|
|
X(SPINE20)
|
|
|
|
|
X(SPINE21)
|
|
|
|
|
X(SPINE22)
|
|
|
|
|
X(SPINE23)
|
|
|
|
|
X(SPINE24)
|
|
|
|
|
X(SPINE25)
|
|
|
|
|
X(SPINE26)
|
|
|
|
|
X(SPINE27)
|
|
|
|
|
X(SPINE28)
|
|
|
|
|
X(SPINE29)
|
|
|
|
|
X(SPINE30)
|
|
|
|
|
X(SPINE31)
|
|
|
|
|
|
|
|
|
|
// slice items
|
|
|
|
|
X(SLICE)
|
|
|
|
|
X(CLK)
|
|
|
|
|
X(LSR)
|
|
|
|
|
X(CE)
|
|
|
|
|
X(Q)
|
|
|
|
|
X(F)
|
|
|
|
|
X(A)
|
|
|
|
|
X(B)
|
|
|
|
|
X(C)
|
|
|
|
|
X(D)
|
|
|
|
|
// iob items
|
|
|
|
|
X(IOB)
|
|
|
|
|
X(I)
|
|
|
|
|
X(O)
|
|
|
|
|
X(IO)
|
|
|
|
|
X(OE)
|
|
|
|
|
X(OB)
|
|
|
|
|
X(IB)
|
|
|
|
|
|
|
|
|
|
// bels
|
|
|
|
|
X(DFF0)
|
|
|
|
|
X(DFF1)
|
|
|
|
|
X(DFF2)
|
|
|
|
|
X(DFF3)
|
|
|
|
|
X(DFF4)
|
|
|
|
|
X(DFF5)
|
|
|
|
|
|
|
|
|
|
X(LUT0)
|
|
|
|
|
X(LUT1)
|
|
|
|
|
X(LUT2)
|
|
|
|
|
X(LUT3)
|
|
|
|
|
X(LUT4)
|
|
|
|
|
X(LUT5)
|
|
|
|
|
X(LUT6)
|
|
|
|
|
X(LUT7)
|
|
|
|
|
|
|
|
|
|
X(IOBA)
|
|
|
|
|
X(IOBB)
|
|
|
|
|
X(IOBC)
|
|
|
|
|
X(IOBD)
|
|
|
|
|
X(IOBE)
|
|
|
|
|
X(IOBF)
|
|
|
|
|
X(IOBG)
|
|
|
|
|
X(IOBH)
|
|
|
|
|
X(IOBI)
|
|
|
|
|
X(IOBJ)
|
|
|
|
|
|
|
|
|
|
// misc
|
|
|
|
|
X(DUMMY_CELL)
|
|
|
|
|
|
|
|
|
|
// simplified iobs
|
|
|
|
|
X(IOBS)
|
|
|
|
|
X(IOBAS)
|
|
|
|
|
X(IOBBS)
|
|
|
|
|
X(IOBCS)
|
|
|
|
|
X(IOBDS)
|
|
|
|
|
X(IOBES)
|
|
|
|
|
X(IOBFS)
|
|
|
|
|
X(IOBGS)
|
|
|
|
|
X(IOBHS)
|
|
|
|
|
X(IOBIS)
|
|
|
|
|
X(IOBJS)
|
|
|
|
|
|
|
|
|
|
// long wires
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(LONGWIRE)
|
2023-06-28 08:16:29 +08:00
|
|
|
X(BUFS)
|
|
|
|
|
X(BUFS0)
|
|
|
|
|
X(BUFS1)
|
|
|
|
|
X(BUFS2)
|
|
|
|
|
X(BUFS3)
|
|
|
|
|
X(BUFS4)
|
|
|
|
|
X(BUFS5)
|
|
|
|
|
X(BUFS6)
|
|
|
|
|
X(BUFS7)
|
|
|
|
|
X(LWT0)
|
|
|
|
|
X(LWB0)
|
|
|
|
|
X(LWT1)
|
|
|
|
|
X(LWB1)
|
|
|
|
|
X(LWT2)
|
|
|
|
|
X(LWB2)
|
|
|
|
|
X(LWT3)
|
|
|
|
|
X(LWB3)
|
|
|
|
|
X(LWT4)
|
|
|
|
|
X(LWB4)
|
|
|
|
|
X(LWT5)
|
|
|
|
|
X(LWB5)
|
|
|
|
|
X(LWT6)
|
|
|
|
|
X(LWB6)
|
|
|
|
|
X(LWT7)
|
|
|
|
|
X(LWB7)
|
|
|
|
|
X(LWSPINETL0)
|
|
|
|
|
X(LWSPINETL1)
|
|
|
|
|
X(LWSPINETL2)
|
|
|
|
|
X(LWSPINETL3)
|
|
|
|
|
X(LWSPINETL4)
|
|
|
|
|
X(LWSPINETL5)
|
|
|
|
|
X(LWSPINETL6)
|
|
|
|
|
X(LWSPINETL7)
|
|
|
|
|
X(LWSPINETR0)
|
|
|
|
|
X(LWSPINETR1)
|
|
|
|
|
X(LWSPINETR2)
|
|
|
|
|
X(LWSPINETR3)
|
|
|
|
|
X(LWSPINETR4)
|
|
|
|
|
X(LWSPINETR5)
|
|
|
|
|
X(LWSPINETR6)
|
|
|
|
|
X(LWSPINETR7)
|
|
|
|
|
X(LWSPINEBL0)
|
|
|
|
|
X(LWSPINEBL1)
|
|
|
|
|
X(LWSPINEBL2)
|
|
|
|
|
X(LWSPINEBL3)
|
|
|
|
|
X(LWSPINEBL4)
|
|
|
|
|
X(LWSPINEBL5)
|
|
|
|
|
X(LWSPINEBL6)
|
|
|
|
|
X(LWSPINEBL7)
|
|
|
|
|
X(LWSPINEBR0)
|
|
|
|
|
X(LWSPINEBR1)
|
|
|
|
|
X(LWSPINEBR2)
|
|
|
|
|
X(LWSPINEBR3)
|
|
|
|
|
X(LWSPINEBR4)
|
|
|
|
|
X(LWSPINEBR5)
|
|
|
|
|
X(LWSPINEBR6)
|
|
|
|
|
X(LWSPINEBR7)
|
|
|
|
|
X(LWI0)
|
|
|
|
|
X(LWI1)
|
|
|
|
|
X(LWI2)
|
|
|
|
|
X(LWI3)
|
|
|
|
|
X(LWI4)
|
|
|
|
|
X(LWI5)
|
|
|
|
|
X(LWI6)
|
|
|
|
|
X(LWI7)
|
|
|
|
|
X(LWO0)
|
|
|
|
|
X(LWO1)
|
|
|
|
|
X(LWO2)
|
|
|
|
|
X(LWO3)
|
|
|
|
|
X(LWO4)
|
|
|
|
|
X(LWO5)
|
|
|
|
|
X(LWO6)
|
|
|
|
|
X(LWO7)
|
|
|
|
|
|
|
|
|
|
// IOLOGIC
|
2024-11-30 16:24:59 +08:00
|
|
|
X(C_STATIC_DLY)
|
|
|
|
|
X(IODELAY)
|
|
|
|
|
X(SDTAP)
|
|
|
|
|
X(SETN)
|
|
|
|
|
X(VALUE)
|
|
|
|
|
X(DF)
|
2024-11-27 16:57:34 +08:00
|
|
|
X(IEM)
|
|
|
|
|
X(WINSIZE)
|
|
|
|
|
X(WINSIZE0)
|
|
|
|
|
X(WINSIZE1)
|
|
|
|
|
X(SMALL)
|
|
|
|
|
X(MIDSMALL)
|
|
|
|
|
X(MIDLARGE)
|
|
|
|
|
X(LARGE)
|
|
|
|
|
X(LAG)
|
|
|
|
|
X(LEAD)
|
2023-06-28 08:16:29 +08:00
|
|
|
X(TX)
|
|
|
|
|
X(TX0)
|
|
|
|
|
X(TX1)
|
|
|
|
|
X(TX2)
|
|
|
|
|
X(TX3)
|
|
|
|
|
X(FCLK)
|
|
|
|
|
X(PCLK)
|
|
|
|
|
X(CALIB)
|
|
|
|
|
X(DAADJ0)
|
|
|
|
|
X(DAADJ1)
|
|
|
|
|
X(GW9_ALWAYS_LOW0)
|
|
|
|
|
X(GW9_ALWAYS_LOW1)
|
|
|
|
|
X(GW9C_ALWAYS_LOW0)
|
|
|
|
|
X(GW9C_ALWAYS_LOW1)
|
|
|
|
|
X(OBUF_TYPE)
|
|
|
|
|
X(IBUF_TYPE)
|
|
|
|
|
X(SBUF)
|
|
|
|
|
X(DBUF)
|
|
|
|
|
X(ODDR)
|
|
|
|
|
X(IDDR)
|
|
|
|
|
X(ODDRC)
|
|
|
|
|
X(IDDRC)
|
|
|
|
|
X(ODDRA)
|
|
|
|
|
X(ODDRB)
|
|
|
|
|
X(ODDRCA)
|
|
|
|
|
X(ODDRCB)
|
|
|
|
|
X(OSER4)
|
|
|
|
|
X(OSER8)
|
|
|
|
|
X(OSER10)
|
|
|
|
|
X(OVIDEO)
|
|
|
|
|
X(OSER16)
|
|
|
|
|
X(IDES4)
|
|
|
|
|
X(IDES8)
|
|
|
|
|
X(IDES10)
|
|
|
|
|
X(IVIDEO)
|
|
|
|
|
X(IDES16)
|
2024-11-27 16:57:34 +08:00
|
|
|
X(IOLOGICI_EMPTY)
|
2024-11-30 16:24:59 +08:00
|
|
|
X(IOLOGICO_EMPTY)
|
2024-02-10 12:16:52 +08:00
|
|
|
X(IOLOGIC)
|
2024-02-09 15:44:57 +08:00
|
|
|
X(IOLOGICI)
|
|
|
|
|
X(IOLOGICO)
|
2023-06-28 08:16:29 +08:00
|
|
|
X(IOLOGICA)
|
|
|
|
|
X(IOLOGICB)
|
|
|
|
|
X(IOLOGIC_TYPE)
|
|
|
|
|
X(IOLOGIC_FCLK)
|
|
|
|
|
X(IOLOGIC_MASTER_CELL)
|
|
|
|
|
X(IOLOGIC_AUX_CELL)
|
|
|
|
|
X(D8)
|
|
|
|
|
X(D9)
|
|
|
|
|
X(D10)
|
|
|
|
|
X(D11)
|
|
|
|
|
X(D12)
|
|
|
|
|
X(D13)
|
|
|
|
|
X(D14)
|
|
|
|
|
X(D15)
|
|
|
|
|
X(Q8)
|
|
|
|
|
X(Q9)
|
|
|
|
|
X(Q10)
|
|
|
|
|
X(Q11)
|
|
|
|
|
X(Q12)
|
|
|
|
|
X(Q13)
|
|
|
|
|
X(Q14)
|
|
|
|
|
X(Q15)
|
|
|
|
|
|
|
|
|
|
// Wide LUTs
|
|
|
|
|
X(MUX2_LUT5)
|
|
|
|
|
X(MUX2_LUT6)
|
|
|
|
|
X(MUX2_LUT7)
|
|
|
|
|
X(MUX2_LUT8)
|
|
|
|
|
X(I0MUX0)
|
|
|
|
|
X(I1MUX0)
|
|
|
|
|
X(I0MUX1)
|
|
|
|
|
X(I1MUX1)
|
|
|
|
|
X(I0MUX2)
|
|
|
|
|
X(I1MUX2)
|
|
|
|
|
X(I0MUX3)
|
|
|
|
|
X(I1MUX3)
|
|
|
|
|
X(I0MUX4)
|
|
|
|
|
X(I1MUX4)
|
|
|
|
|
X(I0MUX5)
|
|
|
|
|
X(I1MUX5)
|
|
|
|
|
X(I0MUX6)
|
|
|
|
|
X(I1MUX6)
|
|
|
|
|
X(I0MUX7)
|
|
|
|
|
X(I1MUX7)
|
|
|
|
|
|
|
|
|
|
// ALU
|
|
|
|
|
X(ALU)
|
|
|
|
|
X(GND)
|
|
|
|
|
X(ALU_MODE)
|
|
|
|
|
|
|
|
|
|
// DFF types
|
|
|
|
|
X(DFF)
|
|
|
|
|
X(DFFE)
|
|
|
|
|
X(DFFS)
|
|
|
|
|
X(DFFSE)
|
|
|
|
|
X(DFFR)
|
|
|
|
|
X(DFFRE)
|
|
|
|
|
X(DFFP)
|
|
|
|
|
X(DFFPE)
|
|
|
|
|
X(DFFC)
|
|
|
|
|
X(DFFCE)
|
|
|
|
|
X(DFFN)
|
|
|
|
|
X(DFFNE)
|
|
|
|
|
X(DFFNS)
|
|
|
|
|
X(DFFNSE)
|
|
|
|
|
X(DFFNR)
|
|
|
|
|
X(DFFNRE)
|
|
|
|
|
X(DFFNP)
|
|
|
|
|
X(DFFNPE)
|
|
|
|
|
X(DFFNC)
|
|
|
|
|
X(DFFNCE)
|
|
|
|
|
|
|
|
|
|
// Shadow RAM
|
|
|
|
|
X(RAM16)
|
|
|
|
|
X(RAMW)
|
|
|
|
|
X(RAM16SDP4)
|
2023-07-06 12:48:44 +08:00
|
|
|
X(RAM16SDP2)
|
|
|
|
|
X(RAM16SDP1)
|
2023-06-28 08:16:29 +08:00
|
|
|
X(WADA)
|
|
|
|
|
X(WADB)
|
|
|
|
|
X(WADC)
|
|
|
|
|
X(WADD)
|
|
|
|
|
X(DIA)
|
|
|
|
|
X(DIB)
|
|
|
|
|
X(DIC)
|
|
|
|
|
X(DID)
|
|
|
|
|
X(WRE)
|
|
|
|
|
|
2023-10-03 19:11:40 +08:00
|
|
|
// BSRAM
|
2024-06-28 06:15:50 +08:00
|
|
|
X(BLK_SEL)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(BSRAM_SUBTYPE)
|
2024-06-23 18:26:50 +08:00
|
|
|
X(WRITE_MODE)
|
|
|
|
|
X(READ_MODE)
|
2024-06-25 16:27:00 +08:00
|
|
|
X(RESET_MODE)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(BIT_WIDTH)
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(BIT_WIDTH_0)
|
|
|
|
|
X(BIT_WIDTH_1)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(ROM)
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(DP)
|
|
|
|
|
X(DPB)
|
|
|
|
|
X(DPX9B)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(SP)
|
|
|
|
|
X(SPX9)
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(SDP)
|
|
|
|
|
X(SDPB)
|
|
|
|
|
X(SDPX9B)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(pROM)
|
|
|
|
|
X(pROMX9)
|
|
|
|
|
X(BSRAM)
|
|
|
|
|
X(OCE)
|
|
|
|
|
X(OCEA)
|
|
|
|
|
X(OCEB)
|
|
|
|
|
X(CEA)
|
|
|
|
|
X(CEB)
|
|
|
|
|
X(RESETA)
|
|
|
|
|
X(RESETB)
|
|
|
|
|
X(WREA)
|
|
|
|
|
X(WREB)
|
|
|
|
|
X(CLKA)
|
|
|
|
|
X(CLKB)
|
|
|
|
|
|
2024-03-18 20:08:52 +08:00
|
|
|
// DSP
|
|
|
|
|
X(ALU54D)
|
|
|
|
|
X(MULTADDALU18X18)
|
|
|
|
|
X(MULTALU18X18)
|
|
|
|
|
X(MULTALU36X18)
|
|
|
|
|
X(MULT36X36)
|
|
|
|
|
X(MULT18X18)
|
|
|
|
|
X(MULT9X9)
|
|
|
|
|
X(PADD18)
|
|
|
|
|
X(PADD9)
|
|
|
|
|
X(ASIGN)
|
|
|
|
|
X(BSIGN)
|
|
|
|
|
X(ASIGN0)
|
|
|
|
|
X(BSIGN0)
|
|
|
|
|
X(ASIGN1)
|
|
|
|
|
X(BSIGN1)
|
2024-04-17 12:52:34 +08:00
|
|
|
X(ZERO_SIGN)
|
|
|
|
|
X(ZERO_ASIGN0)
|
|
|
|
|
X(ZERO_BSIGN0)
|
|
|
|
|
X(ZERO_ASIGN1)
|
|
|
|
|
X(ZERO_BSIGN1)
|
2024-03-18 20:08:52 +08:00
|
|
|
X(ASEL)
|
|
|
|
|
X(ASEL0)
|
|
|
|
|
X(ASEL1)
|
|
|
|
|
X(BSEL)
|
|
|
|
|
X(BSEL0)
|
|
|
|
|
X(BSEL1)
|
|
|
|
|
X(SOA_REG)
|
|
|
|
|
X(DSIGN)
|
|
|
|
|
X(ACCLOAD)
|
|
|
|
|
X(ACCLOAD0)
|
|
|
|
|
X(ACCLOAD1)
|
|
|
|
|
X(NET_ACCLOAD)
|
|
|
|
|
X(ALUSEL0)
|
|
|
|
|
X(ALUSEL1)
|
|
|
|
|
X(ALUSEL2)
|
|
|
|
|
X(ALUSEL3)
|
|
|
|
|
X(ALUSEL4)
|
|
|
|
|
X(ALUSEL5)
|
|
|
|
|
X(ALUSEL6)
|
|
|
|
|
X(USE_CASCADE_OUT)
|
|
|
|
|
X(USE_CASCADE_IN)
|
|
|
|
|
X(LAST_IN_CHAIN)
|
|
|
|
|
X(MULTALU18X18_MODE)
|
|
|
|
|
X(MULTADDALU18X18_MODE)
|
|
|
|
|
X(MULTALU36X18_MODE)
|
|
|
|
|
|
2023-06-28 08:16:29 +08:00
|
|
|
// IOB types
|
|
|
|
|
X(IBUF)
|
|
|
|
|
X(OBUF)
|
|
|
|
|
X(IOBUF)
|
|
|
|
|
X(TBUF)
|
|
|
|
|
X(TLVDS_OBUF)
|
|
|
|
|
X(TLVDS_TBUF)
|
|
|
|
|
X(TLVDS_IBUF)
|
|
|
|
|
X(TLVDS_IOBUF)
|
|
|
|
|
X(ELVDS_OBUF)
|
|
|
|
|
X(ELVDS_TBUF)
|
|
|
|
|
X(ELVDS_IBUF)
|
|
|
|
|
X(ELVDS_IOBUF)
|
|
|
|
|
|
|
|
|
|
// global set/reset
|
|
|
|
|
X(GSR)
|
|
|
|
|
X(GSR0)
|
|
|
|
|
X(GSRI)
|
|
|
|
|
|
2024-07-06 17:14:43 +08:00
|
|
|
// power saving
|
|
|
|
|
X(BANDGAP)
|
|
|
|
|
X(BGEN)
|
|
|
|
|
|
2024-01-23 12:50:36 +08:00
|
|
|
// inverter
|
|
|
|
|
X(INV)
|
|
|
|
|
|
2023-06-28 08:16:29 +08:00
|
|
|
// Oscillators
|
|
|
|
|
X(OSC)
|
|
|
|
|
X(OSCZ)
|
|
|
|
|
X(OSCH)
|
|
|
|
|
X(OSCF)
|
|
|
|
|
X(OSCW)
|
|
|
|
|
X(OSCO)
|
|
|
|
|
|
|
|
|
|
// PLLs
|
|
|
|
|
X(rPLL)
|
|
|
|
|
X(RPLLA)
|
|
|
|
|
X(PLLVR)
|
|
|
|
|
|
|
|
|
|
// primitive attributes
|
|
|
|
|
X(INIT)
|
|
|
|
|
X(FF_USED)
|
|
|
|
|
X(FF_TYPE)
|
|
|
|
|
X(INPUT_USED)
|
|
|
|
|
X(OUTPUT_USED)
|
|
|
|
|
X(ENABLE_USED)
|
|
|
|
|
X(BEL)
|
|
|
|
|
X(DIFF)
|
|
|
|
|
X(DIFF_TYPE)
|
|
|
|
|
X(DEVICE)
|
|
|
|
|
X(IOLOGIC_IOB)
|
|
|
|
|
|
|
|
|
|
// ports
|
|
|
|
|
X(EN)
|
|
|
|
|
X(E)
|
|
|
|
|
X(Y)
|
|
|
|
|
X(PAD)
|
|
|
|
|
X(RESET)
|
|
|
|
|
X(SET)
|
|
|
|
|
X(PRESET)
|
|
|
|
|
X(CLEAR)
|
|
|
|
|
X(I0)
|
|
|
|
|
X(I1)
|
|
|
|
|
X(I2)
|
|
|
|
|
X(I3)
|
|
|
|
|
X(OEN)
|
|
|
|
|
X(S0)
|
|
|
|
|
X(SEL)
|
|
|
|
|
X(SUM)
|
|
|
|
|
X(CIN)
|
|
|
|
|
X(COUT)
|
|
|
|
|
X(OF)
|
|
|
|
|
X(V)
|
|
|
|
|
X(G)
|
|
|
|
|
X(OSCOUT)
|
|
|
|
|
X(OSCEN)
|
|
|
|
|
X(RESET_P)
|
|
|
|
|
X(CLKFB)
|
|
|
|
|
X(FBDSEL0)
|
|
|
|
|
X(FBDSEL1)
|
|
|
|
|
X(FBDSEL2)
|
|
|
|
|
X(FBDSEL3)
|
|
|
|
|
X(FBDSEL4)
|
|
|
|
|
X(FBDSEL5)
|
|
|
|
|
X(IDSEL0)
|
|
|
|
|
X(IDSEL1)
|
|
|
|
|
X(IDSEL2)
|
|
|
|
|
X(IDSEL3)
|
|
|
|
|
X(IDSEL4)
|
|
|
|
|
X(IDSEL5)
|
|
|
|
|
X(ODSEL0)
|
|
|
|
|
X(ODSEL1)
|
|
|
|
|
X(ODSEL2)
|
|
|
|
|
X(ODSEL3)
|
|
|
|
|
X(ODSEL4)
|
|
|
|
|
X(ODSEL5)
|
|
|
|
|
X(PSDA0)
|
|
|
|
|
X(PSDA1)
|
|
|
|
|
X(PSDA2)
|
|
|
|
|
X(PSDA3)
|
|
|
|
|
X(DUTYDA0)
|
|
|
|
|
X(DUTYDA1)
|
|
|
|
|
X(DUTYDA2)
|
|
|
|
|
X(DUTYDA3)
|
|
|
|
|
X(FDLY0)
|
|
|
|
|
X(FDLY1)
|
|
|
|
|
X(FDLY2)
|
|
|
|
|
X(FDLY3)
|
|
|
|
|
X(CLKIN)
|
|
|
|
|
X(CLKOUT)
|
|
|
|
|
X(CLKOUTP)
|
|
|
|
|
X(CLKOUTD)
|
|
|
|
|
X(CLKOUTD3)
|
|
|
|
|
X(LOCK)
|
gowin: Himbaechel. Add BSRAM for all chips.
The following primitives are implemented for the GW1N-1, GW2A-18,
GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
of 32/36 bits are implemented using a pair of 16-bit wide
primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-26 18:51:16 +08:00
|
|
|
X(AD)
|
|
|
|
|
X(DI)
|
|
|
|
|
X(DO)
|
2024-07-14 16:57:07 +08:00
|
|
|
X(P16A)
|
|
|
|
|
X(P16B)
|
|
|
|
|
X(P16C)
|
|
|
|
|
X(P16D)
|
|
|
|
|
X(P17A)
|
|
|
|
|
X(P17B)
|
|
|
|
|
X(P17C)
|
|
|
|
|
X(P17D)
|
|
|
|
|
X(P26A)
|
|
|
|
|
X(P26B)
|
|
|
|
|
X(P26C)
|
|
|
|
|
X(P26D)
|
|
|
|
|
X(P27A)
|
|
|
|
|
X(P27B)
|
|
|
|
|
X(P27C)
|
|
|
|
|
X(P27D)
|
|
|
|
|
X(P36A)
|
|
|
|
|
X(P36B)
|
|
|
|
|
X(P36C)
|
|
|
|
|
X(P36D)
|
|
|
|
|
X(P37A)
|
|
|
|
|
X(P37B)
|
|
|
|
|
X(P37C)
|
|
|
|
|
X(P37D)
|
|
|
|
|
X(P46A)
|
|
|
|
|
X(P46B)
|
|
|
|
|
X(P46C)
|
|
|
|
|
X(P46D)
|
|
|
|
|
X(P47A)
|
|
|
|
|
X(P47B)
|
|
|
|
|
X(P47C)
|
|
|
|
|
X(P47D)
|
2023-06-28 08:16:29 +08:00
|
|
|
|
|
|
|
|
// PLL parameters
|
|
|
|
|
X(CLKOUTPS)
|
|
|
|
|
X(CLKOUTDIV)
|
|
|
|
|
X(CLKOUTDIV3)
|
|
|
|
|
X(PWDEN)
|
|
|
|
|
X(RSTEN)
|
|
|
|
|
X(FLOCK)
|
|
|
|
|
X(INSEL)
|
|
|
|
|
X(FBSEL)
|
|
|
|
|
X(CLKFB_SEL)
|
|
|
|
|
|
|
|
|
|
// timing
|
|
|
|
|
X(X0)
|
|
|
|
|
X(FX1)
|
|
|
|
|
X(X2)
|
|
|
|
|
X(X8)
|
|
|
|
|
X(PIO_CENT_PCLK)
|
|
|
|
|
X(CENT_SPINE_PCLK)
|
|
|
|
|
X(SPINE_TAP_PCLK)
|
|
|
|
|
X(TAP_BRANCH_PCLK)
|
|
|
|
|
X(BRANCH_PCLK)
|
|
|
|
|
X(CENT_SPINE_SCLK)
|
|
|
|
|
X(SPINE_TAP_SCLK_0)
|
|
|
|
|
X(SPINE_TAP_SCLK_1)
|
|
|
|
|
X(TAP_BRANCH_SCLK)
|
|
|
|
|
X(BRANCH_SCLK)
|
|
|
|
|
X(clksetpos)
|
|
|
|
|
X(clkholdpos)
|
|
|
|
|
X(clk_qpos)
|
|
|
|
|
X(a_f)
|
|
|
|
|
X(b_f)
|
|
|
|
|
X(c_f)
|
|
|
|
|
X(d_f)
|
|
|
|
|
X(fx_ofx1)
|
|
|
|
|
X(I01)
|
|
|
|
|
|
|
|
|
|
// GUI
|
|
|
|
|
X(DECAL_LUT_ACTIVE)
|
|
|
|
|
X(DECAL_LUT_INACTIVE)
|
|
|
|
|
X(DECAL_LUTDFF_ACTIVE)
|
|
|
|
|
X(DECAL_LUTDFF_INACTIVE)
|
|
|
|
|
X(DECAL_LUT_UNUSED_DFF_ACTIVE)
|
|
|
|
|
X(DECAL_GRP_LUT)
|
|
|
|
|
X(DECAL_CRU)
|
|
|
|
|
X(DECAL_MUXUPPER_INACTIVE)
|
|
|
|
|
X(DECAL_MUXUPPER_ACTIVE)
|
|
|
|
|
X(DECAL_MUXLOWER_INACTIVE)
|
|
|
|
|
X(DECAL_MUXLOWER_ACTIVE)
|
|
|
|
|
X(DECAL_IOB_INACTIVE)
|
|
|
|
|
X(DECAL_IOB_ACTIVE)
|
|
|
|
|
X(DECAL_IOBS_INACTIVE)
|
|
|
|
|
X(DECAL_IOBS_ACTIVE)
|
|
|
|
|
X(DECAL_ALU_ACTIVE)
|
|
|
|
|
|
|
|
|
|
X(SINGLE_INPUT_MUX)
|
|
|
|
|
X(cst)
|
|
|
|
|
X(none)
|
|
|
|
|
X(pack)
|
|
|
|
|
X(place)
|
|
|
|
|
X(placer)
|
|
|
|
|
X(route)
|
|
|
|
|
X(router)
|
2023-06-29 04:50:16 +08:00
|
|
|
|
2023-06-30 15:18:14 +08:00
|
|
|
// misc
|
|
|
|
|
X(GOWIN_GND)
|
|
|
|
|
X(GOWIN_VCC)
|
2023-07-22 08:01:35 +08:00
|
|
|
X(PLL)
|
2024-04-07 19:47:23 +08:00
|
|
|
X(CLKIN_T)
|
|
|
|
|
X(CLKIN_C)
|
|
|
|
|
X(FB_T)
|
|
|
|
|
X(FB_C)
|
2023-07-23 14:46:04 +08:00
|
|
|
X(BOTTOM_IO_PORT_A)
|
|
|
|
|
X(BOTTOM_IO_PORT_B)
|
2023-08-07 16:20:08 +08:00
|
|
|
X(IOLOGIC_DUMMY)
|
2023-06-30 15:18:14 +08:00
|
|
|
|
2024-09-04 18:55:35 +08:00
|
|
|
// User Flash
|
|
|
|
|
X(INUSEN)
|
|
|
|
|
X(DIN)
|
|
|
|
|
X(DOUT)
|
|
|
|
|
X(XE)
|
|
|
|
|
X(YE)
|
|
|
|
|
X(SE)
|
|
|
|
|
X(PROG)
|
|
|
|
|
X(ERASE)
|
|
|
|
|
X(NVSTR)
|
|
|
|
|
X(XADR0)
|
|
|
|
|
X(XADR1)
|
|
|
|
|
X(XADR2)
|
|
|
|
|
X(XADR3)
|
|
|
|
|
X(XADR4)
|
|
|
|
|
X(XADR5)
|
|
|
|
|
X(XADR6)
|
|
|
|
|
X(XADR7)
|
|
|
|
|
X(XADR8)
|
|
|
|
|
X(YADR)
|
|
|
|
|
X(RA)
|
|
|
|
|
X(CA)
|
|
|
|
|
X(PA)
|
|
|
|
|
X(MODE)
|
|
|
|
|
X(SEQ)
|
|
|
|
|
X(RMODE)
|
|
|
|
|
X(WMODE)
|
|
|
|
|
X(RBYTESEL)
|
|
|
|
|
X(WBYTESEL)
|
|
|
|
|
X(FLASH96K)
|
|
|
|
|
X(FLASH256K)
|
|
|
|
|
X(FLASH608K)
|
|
|
|
|
X(FLASH128K)
|
|
|
|
|
X(FLASH64K)
|
|
|
|
|
X(FLASH64KZ)
|
|
|
|
|
X(FLASH96KA)
|
2023-10-03 19:11:40 +08:00
|
|
|
|
2023-07-12 09:25:28 +08:00
|
|
|
// wire types
|
|
|
|
|
X(GLOBAL_CLK)
|
|
|
|
|
X(TILE_CLK)
|
|
|
|
|
X(TILE_LSR)
|
|
|
|
|
X(TILE_CE)
|
|
|
|
|
X(IO_I)
|
|
|
|
|
X(IO_O)
|
|
|
|
|
X(LUT_INPUT)
|
|
|
|
|
X(LUT_OUT)
|
|
|
|
|
X(FF_INPUT)
|
|
|
|
|
X(FF_OUT)
|
|
|
|
|
X(MUX_OUT)
|
|
|
|
|
X(MUX_SEL)
|
|
|
|
|
X(ALU_CIN)
|
|
|
|
|
X(ALU_COUT)
|
2023-07-22 08:01:35 +08:00
|
|
|
X(PLL_O)
|
|
|
|
|
X(PLL_I)
|
2023-07-12 09:25:28 +08:00
|
|
|
|
2023-07-19 11:29:18 +08:00
|
|
|
// fake dff inputs
|
|
|
|
|
X(XD0)
|
|
|
|
|
X(XD1)
|
|
|
|
|
X(XD2)
|
|
|
|
|
X(XD3)
|
|
|
|
|
X(XD4)
|
|
|
|
|
X(XD5)
|
|
|
|
|
|
2023-08-06 18:56:08 +08:00
|
|
|
// HCLK wires
|
2023-08-08 08:57:45 +08:00
|
|
|
X(HCLK)
|
2023-08-06 18:56:08 +08:00
|
|
|
X(HCLK_OUT0)
|
|
|
|
|
X(HCLK_OUT1)
|
|
|
|
|
X(HCLK_OUT2)
|
|
|
|
|
X(HCLK_OUT3)
|
|
|
|
|
|
2023-09-04 20:20:08 +08:00
|
|
|
// BUFG, clock buffers stuff
|
2024-07-14 14:53:26 +08:00
|
|
|
X(CLKSEL)
|
2023-09-04 20:20:08 +08:00
|
|
|
X(BUFG)
|
|
|
|
|
X(CLOCK)
|
2024-07-14 14:53:26 +08:00
|
|
|
X(DQCE)
|
|
|
|
|
X(DCS)
|
|
|
|
|
X(DQCE_PIP)
|
2024-09-11 17:18:26 +08:00
|
|
|
X(DHCEN_USED)
|
2024-07-14 14:53:26 +08:00
|
|
|
X(DCS_USED)
|
|
|
|
|
X(SELFORCE)
|
2024-09-11 17:18:26 +08:00
|
|
|
X(DHCEN)
|
|
|
|
|
X(DCS_MODE)
|
gowin: Himbaechel. Add BSRAM for all chips.
The following primitives are implemented for the GW1N-1, GW2A-18,
GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
of 32/36 bits are implemented using a pair of 16-bit wide
primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-26 18:51:16 +08:00
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2024-08-03 21:57:22 +08:00
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//HCLK Bels
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X(CLKDIV)
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X(CLKDIV2)
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//HCLK Ports
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X(HCLKIN)
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X(RESETN)
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// X(CALIB)
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// X(CLKOUT)
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//HCLK Parameters
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X(DIV_MODE)
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X(GSREN)
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2024-11-27 16:57:34 +08:00
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X(LSREN)
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2024-09-12 15:53:39 +08:00
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// EMCU
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X(EMCU)
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Gowin. Add the ability to place registers in IOB (#1403)
* Gowin. Add the ability to place registers in IOB
IO blocks have registers: for input, for output and for OutputEnable
signal - IREG, OREG and TREG respectively.
Each of the registers has one implicit non-switched wire, which one
depends on the type of register (IREG has a Q wire, OREG has a D wire).
Although the registers can be activated independently of each other they
share the CLK, ClockEnable and LocalSetReset wires and this places
restrictions on the possible combinations of register types in a single
IO.
Register placement in IO blocks is enabled by specifying the command
line keys --vopt ireg_in_iob, --vopt oreg_in_iob, or --vopt ioreg_in_iob.
It should be noted that specifying these keys leads to attempts to place
registers in IO blocks, but no errors are generated in case of failure.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Registers in IO
Check for unconnected ports.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. IO regs. Verbose warnings.
If an attempt to place an FF in an IO block fails, issue a warning
detailing the reason for the failure, whether it is a register type
conflict, a network requirement violation, or a control signal conflict.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. BUGFIX. Fix FFs compatibility.
Flipflops with a fixed ClockEnable input cannot coexist with flipflops
with a variable one.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. FFs in IO. Changing diagnostic messages.
Placement modes are still specified by the command line keys
ireg_in_iob/oreg_in_iob/ioreg_in_iob, but also introduces more granular
control in the form of attributes at I/O ports:
(* NOIOBFF *) - registers are never placed in this IO,
(* IOBFF *) - registers must be placed in this IO, in case of failure
a warning (not an error) with the reason for nonplacement is issued,
_attribute_absence_ - no diagnostics will be issued: managed to place - good, failed - not bad either.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Registers in IO.
Change the logic for handling command line keys and attributes -
attributes allow routines to be placed in IO regardless of global mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Registers in IO. Fix style.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-01-01 20:11:57 +08:00
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// Register placement options
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X(IREG_IN_IOB)
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X(OREG_IN_IOB)
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X(IOREG_IN_IOB)
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X(HAS_REG)
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X(IREG_TYPE)
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X(OREG_TYPE)
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X(TREG_TYPE)
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X(IREG_CLK_NET)
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X(IREG_CE_NET)
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X(IREG_LSR_NET)
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X(OREG_CLK_NET)
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X(OREG_CE_NET)
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X(OREG_LSR_NET)
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X(TREG_CLK_NET)
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X(TREG_CE_NET)
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X(TREG_LSR_NET)
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X(NOIOBFF)
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X(IOBFF)
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