2018-05-26 20:27:21 +08:00
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/*
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* nextpnr -- Next Generation Place and Route
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*
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2021-06-09 20:09:08 +08:00
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* Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 Miodrag Milanovic <micko@yosyshq.com>
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2018-05-26 20:27:21 +08:00
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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2018-06-08 17:17:04 +08:00
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2018-06-07 19:10:53 +08:00
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#include <fstream>
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2018-06-10 17:56:07 +08:00
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#include "bitstream.h"
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2018-08-05 22:13:34 +08:00
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#include "command.h"
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2018-06-17 18:53:39 +08:00
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#include "design_utils.h"
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2018-06-07 20:36:35 +08:00
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#include "log.h"
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2018-06-13 18:30:15 +08:00
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#include "pcf.h"
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2018-06-20 19:01:22 +08:00
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#include "timing.h"
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2018-05-26 20:27:21 +08:00
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2018-06-22 19:10:27 +08:00
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USING_NEXTPNR_NAMESPACE
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2018-08-05 22:13:34 +08:00
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class Ice40CommandHandler : public CommandHandler
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2018-07-20 20:06:53 +08:00
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{
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2018-08-05 22:13:34 +08:00
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public:
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Ice40CommandHandler(int argc, char **argv);
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2024-09-30 20:51:33 +08:00
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virtual ~Ice40CommandHandler() {};
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2021-06-02 18:36:56 +08:00
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std::unique_ptr<Context> createContext(dict<std::string, Property> &values) override;
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2018-08-05 22:13:34 +08:00
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void setupArchContext(Context *ctx) override;
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void validate() override;
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void customAfterLoad(Context *ctx) override;
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void customBitstream(Context *ctx) override;
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protected:
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2018-11-13 21:03:48 +08:00
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po::options_description getArchOptions() override;
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2018-08-05 22:13:34 +08:00
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};
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Ice40CommandHandler::Ice40CommandHandler(int argc, char **argv) : CommandHandler(argc, argv) {}
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po::options_description Ice40CommandHandler::getArchOptions()
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2018-05-26 20:27:21 +08:00
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{
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2018-08-05 22:13:34 +08:00
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po::options_description specific("Architecture specific options");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::LP384))
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2020-06-25 23:11:47 +08:00
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specific.add_options()("lp384", "set device type to iCE40LP384");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::LP1K))
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2020-06-25 23:11:47 +08:00
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specific.add_options()("lp1k", "set device type to iCE40LP1K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::LP4K))
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2020-07-08 19:45:34 +08:00
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specific.add_options()("lp4k", "set device type to iCE40LP4K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::LP8K))
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2020-06-25 23:11:47 +08:00
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specific.add_options()("lp8k", "set device type to iCE40LP8K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::HX1K))
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2020-06-25 23:11:47 +08:00
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specific.add_options()("hx1k", "set device type to iCE40HX1K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::HX8K))
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2020-07-08 19:22:59 +08:00
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specific.add_options()("hx4k", "set device type to iCE40HX4K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::HX4K))
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2020-06-25 23:11:47 +08:00
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specific.add_options()("hx8k", "set device type to iCE40HX8K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::UP3K))
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2020-07-08 20:09:44 +08:00
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specific.add_options()("up3k", "set device type to iCE40UP3K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::UP5K))
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2020-06-25 23:11:47 +08:00
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specific.add_options()("up5k", "set device type to iCE40UP5K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::U1K))
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2020-07-08 20:09:44 +08:00
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specific.add_options()("u1k", "set device type to iCE5LP1K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::U2K))
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2020-07-08 20:09:44 +08:00
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specific.add_options()("u2k", "set device type to iCE5LP2K");
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2021-02-03 18:21:45 +08:00
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if (Arch::is_available(ArchArgs::U4K))
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2020-06-25 23:11:47 +08:00
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specific.add_options()("u4k", "set device type to iCE5LP4K");
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2018-08-05 22:13:34 +08:00
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specific.add_options()("package", po::value<std::string>(), "set device package");
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specific.add_options()("pcf", po::value<std::string>(), "PCF constraints file to ingest");
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specific.add_options()("asc", po::value<std::string>(), "asc bitstream file to write");
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specific.add_options()("read", po::value<std::string>(), "asc bitstream file to read");
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2018-11-28 03:06:55 +08:00
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specific.add_options()("promote-logic",
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"enable promotion of 'logic' globals (in addition to clk/ce/sr by default)");
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specific.add_options()("no-promote-globals", "disable all global promotion");
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2018-12-02 22:08:11 +08:00
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specific.add_options()("opt-timing", "run post-placement timing optimisation pass (experimental)");
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2018-08-05 22:13:34 +08:00
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specific.add_options()("tmfuzz", "run path delay estimate fuzzer");
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2018-12-27 00:00:19 +08:00
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specific.add_options()("pcf-allow-unconstrained", "don't require PCF to constrain all IO");
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2018-08-05 22:13:34 +08:00
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return specific;
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}
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void Ice40CommandHandler::validate()
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{
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conflicting_options(vm, "read", "json");
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2020-07-08 20:09:44 +08:00
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if ((vm.count("lp384") + vm.count("lp1k") + vm.count("lp4k") + vm.count("lp8k") + vm.count("hx1k") +
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vm.count("hx4k") + vm.count("hx8k") + vm.count("up3k") + vm.count("up5k") + vm.count("u1k") + vm.count("u2k") +
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vm.count("u4k")) > 1)
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2018-08-05 22:13:34 +08:00
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log_error("Only one device type can be set\n");
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}
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2018-06-24 20:38:45 +08:00
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2018-08-05 22:13:34 +08:00
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void Ice40CommandHandler::customAfterLoad(Context *ctx)
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{
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if (vm.count("pcf")) {
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2018-08-09 02:14:18 +08:00
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std::string filename = vm["pcf"].as<std::string>();
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std::ifstream pcf(filename);
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if (!apply_pcf(ctx, filename, pcf))
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2018-08-05 22:13:34 +08:00
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log_error("Loading PCF failed.\n");
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2018-12-27 00:00:19 +08:00
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} else {
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log_warning("No PCF file specified; IO pins will be placed automatically\n");
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2018-08-05 22:13:34 +08:00
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}
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}
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void Ice40CommandHandler::customBitstream(Context *ctx)
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{
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if (vm.count("asc")) {
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std::string filename = vm["asc"].as<std::string>();
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std::ofstream f(filename);
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write_asc(ctx, f);
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}
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}
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2018-06-24 20:38:45 +08:00
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2018-08-05 22:13:34 +08:00
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void Ice40CommandHandler::setupArchContext(Context *ctx)
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{
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if (vm.count("tmfuzz"))
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ice40DelayFuzzerMain(ctx);
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if (vm.count("read")) {
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std::string filename = vm["read"].as<std::string>();
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std::ifstream f(filename);
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if (!read_asc(ctx, f))
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log_error("Loading ASC failed.\n");
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}
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}
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2018-06-07 19:10:53 +08:00
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2021-06-02 18:36:56 +08:00
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std::unique_ptr<Context> Ice40CommandHandler::createContext(dict<std::string, Property> &values)
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2018-08-05 22:13:34 +08:00
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{
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2019-06-14 21:18:35 +08:00
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ArchArgs chipArgs;
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chipArgs.type = ArchArgs::NONE;
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2018-08-05 22:13:34 +08:00
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if (vm.count("lp384")) {
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chipArgs.type = ArchArgs::LP384;
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chipArgs.package = "qn32";
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}
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2018-06-07 19:10:53 +08:00
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2018-08-05 22:13:34 +08:00
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if (vm.count("lp1k")) {
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chipArgs.type = ArchArgs::LP1K;
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chipArgs.package = "tq144";
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}
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2018-06-07 19:10:53 +08:00
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2020-07-08 19:44:13 +08:00
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if (vm.count("lp4k")) {
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chipArgs.type = ArchArgs::LP4K;
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chipArgs.package = "tq144";
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}
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2018-08-05 22:13:34 +08:00
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if (vm.count("lp8k")) {
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chipArgs.type = ArchArgs::LP8K;
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chipArgs.package = "ct256";
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}
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2018-06-07 19:10:53 +08:00
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2018-08-05 22:13:34 +08:00
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if (vm.count("hx1k")) {
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chipArgs.type = ArchArgs::HX1K;
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chipArgs.package = "tq144";
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}
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2018-06-07 19:10:53 +08:00
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2020-07-08 19:22:59 +08:00
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if (vm.count("hx4k")) {
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chipArgs.type = ArchArgs::HX4K;
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chipArgs.package = "tq144";
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}
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2018-08-05 22:13:34 +08:00
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if (vm.count("hx8k")) {
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chipArgs.type = ArchArgs::HX8K;
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chipArgs.package = "ct256";
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}
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2018-06-07 19:10:53 +08:00
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2020-07-08 20:09:44 +08:00
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if (vm.count("up3k")) {
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chipArgs.type = ArchArgs::UP3K;
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chipArgs.package = "sg48";
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}
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2018-08-05 22:13:34 +08:00
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if (vm.count("up5k")) {
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chipArgs.type = ArchArgs::UP5K;
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chipArgs.package = "sg48";
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}
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2018-06-07 19:10:53 +08:00
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2020-07-08 20:09:44 +08:00
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if (vm.count("u1k")) {
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chipArgs.type = ArchArgs::U1K;
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chipArgs.package = "sg48";
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}
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if (vm.count("u2k")) {
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chipArgs.type = ArchArgs::U2K;
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chipArgs.package = "sg48";
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}
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2019-02-23 05:36:19 +08:00
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if (vm.count("u4k")) {
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chipArgs.type = ArchArgs::U4K;
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chipArgs.package = "sg48";
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}
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2019-06-14 14:13:59 +08:00
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if (vm.count("package"))
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chipArgs.package = vm["package"].as<std::string>();
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2019-08-10 22:22:04 +08:00
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else
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log_warning("Use of default value for --package is deprecated. Please add '--package %s' to arguments.\n",
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chipArgs.package.c_str());
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2019-06-26 00:19:25 +08:00
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if (values.find("arch.name") != values.end()) {
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2019-08-01 21:28:21 +08:00
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std::string arch_name = values["arch.name"].as_string();
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2019-06-14 14:13:59 +08:00
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if (arch_name != "ice40")
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2020-05-14 11:00:09 +08:00
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log_error("Unsupported architecture '%s'.\n", arch_name.c_str());
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2019-06-14 14:13:59 +08:00
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}
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2019-06-26 00:19:25 +08:00
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if (values.find("arch.type") != values.end()) {
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2019-08-01 21:28:21 +08:00
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std::string arch_type = values["arch.type"].as_string();
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2019-06-14 14:13:59 +08:00
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if (chipArgs.type != ArchArgs::NONE)
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2020-05-14 11:00:09 +08:00
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log_error("Overriding architecture is unsupported.\n");
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2019-06-14 14:13:59 +08:00
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if (arch_type == "lp384") {
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chipArgs.type = ArchArgs::LP384;
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}
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if (arch_type == "lp1k") {
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chipArgs.type = ArchArgs::LP1K;
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}
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2020-07-08 19:44:13 +08:00
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if (arch_type == "lp4k") {
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chipArgs.type = ArchArgs::LP4K;
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}
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2019-06-14 14:13:59 +08:00
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if (arch_type == "lp8k") {
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chipArgs.type = ArchArgs::LP8K;
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}
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if (arch_type == "hx1k") {
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chipArgs.type = ArchArgs::HX1K;
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}
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2020-07-08 19:22:59 +08:00
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if (arch_type == "hx4k") {
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chipArgs.type = ArchArgs::HX4K;
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}
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2019-06-14 14:13:59 +08:00
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if (arch_type == "hx8k") {
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chipArgs.type = ArchArgs::HX8K;
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}
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2020-07-08 20:09:44 +08:00
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if (arch_type == "up3k") {
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chipArgs.type = ArchArgs::UP3K;
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}
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2019-06-14 14:13:59 +08:00
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if (arch_type == "up5k") {
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chipArgs.type = ArchArgs::UP5K;
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}
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2020-07-08 20:09:44 +08:00
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if (arch_type == "u1k") {
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chipArgs.type = ArchArgs::U1K;
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}
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if (arch_type == "u2k") {
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chipArgs.type = ArchArgs::U2K;
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}
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2019-06-14 14:13:59 +08:00
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if (arch_type == "u4k") {
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chipArgs.type = ArchArgs::U4K;
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}
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if (chipArgs.type == ArchArgs::NONE)
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2020-05-14 11:00:09 +08:00
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log_error("Unsupported FPGA type '%s'.\n", arch_type.c_str());
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2019-06-14 14:13:59 +08:00
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}
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2019-06-26 00:19:25 +08:00
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if (values.find("arch.package") != values.end()) {
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2019-06-14 14:13:59 +08:00
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if (vm.count("package"))
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2020-05-14 11:00:09 +08:00
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log_error("Overriding architecture is unsupported.\n");
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2019-08-01 21:28:21 +08:00
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chipArgs.package = values["arch.package"].as_string();
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2019-06-14 14:13:59 +08:00
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}
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2019-06-26 00:19:25 +08:00
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2018-08-05 22:13:34 +08:00
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if (chipArgs.type == ArchArgs::NONE) {
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chipArgs.type = ArchArgs::HX1K;
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chipArgs.package = "tq144";
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}
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2018-06-13 18:30:15 +08:00
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2018-11-28 03:06:55 +08:00
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auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
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2019-06-26 00:19:25 +08:00
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for (auto &val : values)
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2019-06-14 14:55:11 +08:00
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ctx->settings[ctx->id(val.first)] = val.second;
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2019-06-14 00:39:16 +08:00
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ctx->settings[ctx->id("arch.package")] = ctx->archArgs().package;
|
2018-11-28 03:06:55 +08:00
|
|
|
if (vm.count("promote-logic"))
|
2022-02-17 01:09:54 +08:00
|
|
|
ctx->settings[id_promote_logic] = Property::State::S1;
|
2018-11-28 03:06:55 +08:00
|
|
|
if (vm.count("no-promote-globals"))
|
2022-02-17 01:09:54 +08:00
|
|
|
ctx->settings[id_no_promote_globals] = Property::State::S1;
|
2018-12-02 22:08:11 +08:00
|
|
|
if (vm.count("opt-timing"))
|
2022-02-17 01:09:54 +08:00
|
|
|
ctx->settings[id_opt_timing] = Property::State::S1;
|
2018-12-27 00:00:19 +08:00
|
|
|
if (vm.count("pcf-allow-unconstrained"))
|
2022-02-17 01:09:54 +08:00
|
|
|
ctx->settings[id_pcf_allow_unconstrained] = Property::State::S1;
|
2018-11-28 03:06:55 +08:00
|
|
|
return ctx;
|
2018-08-05 22:13:34 +08:00
|
|
|
}
|
2018-06-27 18:18:52 +08:00
|
|
|
|
2018-08-05 22:13:34 +08:00
|
|
|
int main(int argc, char *argv[])
|
|
|
|
{
|
|
|
|
Ice40CommandHandler handler(argc, argv);
|
|
|
|
return handler.exec();
|
2018-05-26 20:27:21 +08:00
|
|
|
}
|