2020-01-07 19:55:55 +08:00
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2020 David Shah <dave@ds0.me>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <boost/algorithm/string.hpp>
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#include "log.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "placer_heap.h"
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#include "router1.h"
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#include "timing.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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2020-01-07 20:17:09 +08:00
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namespace {
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static std::tuple<int, int, std::string> split_identifier_name(const std::string &name)
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{
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size_t first_slash = name.find('/');
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NPNR_ASSERT(first_slash != std::string::npos);
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size_t second_slash = name.find('/', first_slash + 1);
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NPNR_ASSERT(second_slash != std::string::npos);
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return std::make_tuple(std::stoi(name.substr(1, first_slash)),
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std::stoi(name.substr(first_slash + 2, second_slash - first_slash)),
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name.substr(second_slash + 1));
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};
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static const DatabasePOD *get_chipdb(const RelPtr<DatabasePOD> *ptr) { return ptr->get(); }
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} // namespace
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2020-01-07 19:55:55 +08:00
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, ID_##t);
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#include "constids.inc"
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#undef X
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}
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// -----------------------------------------------------------------------
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Arch::Arch(ArchArgs args) : args(args)
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{
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// Parse device string
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if (boost::starts_with(args.device, "LIFCL")) {
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family = "LIFCL";
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} else {
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log_error("Unknown device string '%s' (expected device name like 'LIFCL-40-8SG72C')\n", args.device.c_str());
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}
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auto last_sep = args.device.rfind('-');
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if (last_sep == std::string::npos)
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log_error("Unknown device string '%s' (expected device name like 'LIFCL-40-8SG72C')\n", args.device.c_str());
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device = args.device.substr(0, last_sep);
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speed = args.device.substr(last_sep + 1, 1);
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auto package_end = args.device.find_last_of("0123456789");
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if (package_end == std::string::npos || package_end < last_sep)
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log_error("Unknown device string '%s' (expected device name like 'LIFCL-40-8SG72C')\n", args.device.c_str());
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package = args.device.substr(last_sep + 2, (package_end - (last_sep + 2)) + 1);
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rating = args.device.substr(package_end + 1);
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// Load database (FIXME: baked-in databases too)
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try {
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blob_file.open(args.chipdb);
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if (!blob_file.is_open())
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log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
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const char *blob = reinterpret_cast<const char *>(blob_file.data());
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db = get_chipdb(reinterpret_cast<const RelPtr<DatabasePOD> *>(blob));
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} catch (...) {
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log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
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}
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// Check database version and family
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if (db->version != bba_version) {
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log_error("Provided database version %d is %s than nextpnr version %d, please rebuild database/nextpnr.\n",
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db->version, (db->version > bba_version) ? "newer" : "older", bba_version);
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}
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if (db->family.get() != family) {
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log_error("Database is for family '%s' but provided device is family '%s'.\n", db->family.get(),
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family.c_str());
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}
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// Set up chip_info
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chip_info = nullptr;
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for (size_t i = 0; i < db->num_chips; i++) {
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auto &chip = db->chips[i];
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if (chip.device_name.get() == device) {
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chip_info = &chip;
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break;
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}
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}
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if (!chip_info)
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log_error("Unknown device '%s'.\n", device.c_str());
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// Set up bba IdStrings
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for (size_t i = 0; i < db->ids->num_bba_ids; i++) {
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IdString::initialize_add(this, db->ids->bba_id_strs[i].get(), uint32_t(i) + db->ids->num_file_ids);
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}
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// Set up validity structures
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tileStatus.resize(chip_info->num_tiles);
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for (size_t i = 0; i < chip_info->num_tiles; i++) {
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tileStatus[i].boundcells.resize(db->loctypes[chip_info->grid[i].loc_type].num_bels);
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}
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}
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2020-01-07 20:17:09 +08:00
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// -----------------------------------------------------------------------
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std::string Arch::getChipName() const { return args.device; }
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IdString Arch::archArgsToId(ArchArgs args) const { return id(args.device); }
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// -----------------------------------------------------------------------
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BelId Arch::getBelByName(IdString name) const
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{
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int x, y;
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std::string belname;
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std::tie(x, y, belname) = split_identifier_name(name.str(this));
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NPNR_ASSERT(x >= 0 && x < chip_info->width);
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NPNR_ASSERT(y >= 0 && y < chip_info->height);
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auto &tile = db->loctypes[chip_info->grid[y * chip_info->width + x].loc_type];
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IdString bn = id(belname);
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for (size_t i = 0; i < tile.num_bels; i++) {
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if (tile.bels[i].name == bn.index) {
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BelId ret;
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ret.tile = y * chip_info->width + x;
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ret.index = i;
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return ret;
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}
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}
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return BelId();
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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NPNR_ASSERT(x >= 0 && x < chip_info->width);
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NPNR_ASSERT(y >= 0 && y < chip_info->height);
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br.b.cursor_tile = y * chip_info->width + x;
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br.e.cursor_tile = y * chip_info->width + x;
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br.b.cursor_index = 0;
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br.e.cursor_index = db->loctypes[chip_info->grid[br.b.cursor_tile].loc_type].num_bels;
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br.b.chip = chip_info;
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br.b.db = db;
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br.e.chip = chip_info;
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br.e.db = db;
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if (br.e.cursor_index == -1)
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++br.e.cursor_index;
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else
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++br.e;
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return br;
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}
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WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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// Binary search on wire IdString, by ID
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int num_bel_wires = bel_data(bel).num_ports;
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const BelWirePOD *bel_ports = bel_data(bel).ports.get();
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if (num_bel_wires < 7) {
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for (int i = 0; i < num_bel_wires; i++) {
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if (int(bel_ports[i].port) == pin.index) {
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return canonical_wire(bel.tile, bel_ports[i].wire_index);
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}
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}
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} else {
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int b = 0, e = num_bel_wires - 1;
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while (b <= e) {
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int i = (b + e) / 2;
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if (int(bel_ports[i].port) == pin.index) {
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return canonical_wire(bel.tile, bel_ports[i].wire_index);
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}
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if (int(bel_ports[i].port) > pin.index)
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e = i - 1;
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else
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b = i + 1;
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}
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}
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return WireId();
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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// Binary search on wire IdString, by ID
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int num_bel_wires = bel_data(bel).num_ports;
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const BelWirePOD *bel_ports = bel_data(bel).ports.get();
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if (num_bel_wires < 7) {
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for (int i = 0; i < num_bel_wires; i++) {
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if (int(bel_ports[i].port) == pin.index) {
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return PortType(bel_ports[i].type);
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}
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}
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} else {
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int b = 0, e = num_bel_wires - 1;
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while (b <= e) {
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int i = (b + e) / 2;
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if (int(bel_ports[i].port) == pin.index) {
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return PortType(bel_ports[i].type);
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}
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if (int(bel_ports[i].port) > pin.index)
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e = i - 1;
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else
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b = i + 1;
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}
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}
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NPNR_ASSERT_FALSE("unknown bel pin");
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}
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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int num_bel_wires = bel_data(bel).num_ports;
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const BelWirePOD *bel_ports = bel_data(bel).ports.get();
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for (int i = 0; i < num_bel_wires; i++)
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ret.push_back(IdString(bel_ports[i].port));
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return ret;
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}
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// -----------------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const
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{
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int x, y;
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std::string wirename;
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std::tie(x, y, wirename) = split_identifier_name(name.str(this));
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NPNR_ASSERT(x >= 0 && x < chip_info->width);
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NPNR_ASSERT(y >= 0 && y < chip_info->height);
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auto &tile = db->loctypes[chip_info->grid[y * chip_info->width + x].loc_type];
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IdString wn = id(wirename);
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for (size_t i = 0; i < tile.num_wires; i++) {
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if (tile.wires[i].name == wn.index) {
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WireId ret;
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ret.tile = y * chip_info->width + x;
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ret.index = i;
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return ret;
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}
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}
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return WireId();
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}
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IdString Arch::getWireType(WireId wire) const { return id("WIRE"); }
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std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
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{
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std::vector<std::pair<IdString, std::string>> ret;
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ret.emplace_back(id("INDEX"), stringf("%d", wire.index));
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ret.emplace_back(id("GRID_X"), stringf("%d", wire.tile % chip_info->width));
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ret.emplace_back(id("GRID_Y"), stringf("%d", wire.tile / chip_info->width));
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ret.emplace_back(id("FLAGS"), stringf("%u", wire_data(wire).flags));
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return ret;
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}
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// -----------------------------------------------------------------------
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PipId Arch::getPipByName(IdString name) const
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{
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int x, y;
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std::string pipname;
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std::tie(x, y, pipname) = split_identifier_name(name.str(this));
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NPNR_ASSERT(x >= 0 && x < chip_info->width);
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NPNR_ASSERT(y >= 0 && y < chip_info->height);
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PipId ret;
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ret.tile = y * chip_info->width + x;
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auto sep_pos = pipname.find(':');
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ret.index = std::stoi(pipname.substr(0, sep_pos));
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return ret;
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}
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IdString Arch::getPipName(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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return id(stringf("X%d/Y%d/%d:%s->%s", pip.tile % chip_info->width, pip.tile / chip_info->width, pip.index,
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nameOf(loc_data(pip).wires[pip_data(pip).from_wire].name),
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nameOf(loc_data(pip).wires[pip_data(pip).to_wire].name)));
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}
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IdString Arch::getPipType(PipId pip) const { return IdString(); }
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std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
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{
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std::vector<std::pair<IdString, std::string>> ret;
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ret.emplace_back(id("INDEX"), stringf("%d", pip.index));
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ret.emplace_back(id("GRID_X"), stringf("%d", pip.tile % chip_info->width));
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ret.emplace_back(id("GRID_Y"), stringf("%d", pip.tile / chip_info->width));
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ret.emplace_back(id("FROM_TILE_WIRE"), nameOf(loc_data(pip).wires[pip_data(pip).from_wire].name));
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ret.emplace_back(id("TO_TILE_WIRE"), nameOf(loc_data(pip).wires[pip_data(pip).to_wire].name));
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return ret;
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}
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2020-01-07 21:06:37 +08:00
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// -----------------------------------------------------------------------
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std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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{
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std::vector<GraphicElement> ret;
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return ret;
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}
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DecalXY Arch::getBelDecal(BelId bel) const
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{
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DecalXY decalxy;
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decalxy.decal.index = -1;
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decalxy.x = 0;
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decalxy.y = 0;
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return decalxy;
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}
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DecalXY Arch::getWireDecal(WireId wire) const { return {}; }
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DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
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DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
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// -----------------------------------------------------------------------
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bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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{
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return false;
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}
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TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
|
|
|
|
{
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|
|
|
return TMG_IGNORE;
|
|
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|
}
|
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|
|
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TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const { return {}; }
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// -----------------------------------------------------------------------
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|
delay_t Arch::estimateDelay(WireId src, WireId dst) const
|
|
|
|
{
|
|
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|
int src_x = src.tile % chip_info->width, src_y = src.tile / chip_info->width;
|
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|
int dst_x = dst.tile % chip_info->width, dst_y = dst.tile / chip_info->width;
|
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|
|
int dist_x = std::abs(src_x - dst_x);
|
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|
int dist_y = std::abs(src_y - dst_y);
|
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|
|
return 100 * dist_x + 100 * dist_y;
|
|
|
|
}
|
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|
|
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
|
|
|
|
{
|
|
|
|
if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId() || sink.cell->bel == BelId())
|
|
|
|
return 0;
|
|
|
|
int src_x = net_info->driver.cell->bel.tile % chip_info->width,
|
|
|
|
src_y = net_info->driver.cell->bel.tile / chip_info->width;
|
|
|
|
|
|
|
|
int dst_x = sink.cell->bel.tile % chip_info->width, dst_y = sink.cell->bel.tile / chip_info->width;
|
|
|
|
int dist_x = std::abs(src_x - dst_x);
|
|
|
|
int dist_y = std::abs(src_y - dst_y);
|
|
|
|
return 100 * dist_x + 100 * dist_y;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
|
|
|
|
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
|
|
|
|
bool Arch::pack()
|
|
|
|
{
|
|
|
|
// FIXME
|
|
|
|
getCtx()->attrs[getCtx()->id("step")] = std::string("pack");
|
|
|
|
archInfoToAttributes();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Arch::place()
|
|
|
|
{
|
|
|
|
std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
|
|
|
|
|
|
|
|
if (placer == "heap") {
|
|
|
|
PlacerHeapCfg cfg(getCtx());
|
|
|
|
cfg.criticalityExponent = 7;
|
|
|
|
if (!placer_heap(getCtx(), cfg))
|
|
|
|
return false;
|
|
|
|
} else if (placer == "sa") {
|
|
|
|
if (!placer1(getCtx(), Placer1Cfg(getCtx())))
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
log_error("Nexus architecture does not support placer '%s'\n", placer.c_str());
|
|
|
|
}
|
|
|
|
getCtx()->attrs[getCtx()->id("step")] = std::string("place");
|
|
|
|
archInfoToAttributes();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Arch::route()
|
|
|
|
{
|
|
|
|
assign_budget(getCtx(), true);
|
|
|
|
bool result = router1(getCtx(), Router1Cfg(getCtx()));
|
|
|
|
getCtx()->attrs[getCtx()->id("step")] = std::string("route");
|
|
|
|
archInfoToAttributes();
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
|
|
|
|
void Arch::assignArchInfo() {}
|
|
|
|
|
|
|
|
void assignCellInfo(CellInfo *cell) {}
|
|
|
|
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
|
|
|
|
#ifdef WITH_HEAP
|
|
|
|
const std::string Arch::defaultPlacer = "heap";
|
|
|
|
#else
|
|
|
|
const std::string Arch::defaultPlacer = "sa";
|
|
|
|
#endif
|
|
|
|
|
|
|
|
const std::vector<std::string> Arch::availablePlacers = {"sa",
|
|
|
|
#ifdef WITH_HEAP
|
|
|
|
"heap"
|
|
|
|
#endif
|
|
|
|
};
|
2020-01-07 19:55:55 +08:00
|
|
|
NEXTPNR_NAMESPACE_END
|