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nextpnr/gowin/constids.inc

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Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
X(A0)
X(B0)
X(C0)
X(D0)
X(A1)
X(B1)
X(C1)
X(D1)
X(A2)
X(B2)
X(C2)
X(D2)
X(A3)
X(B3)
X(C3)
X(D3)
X(A4)
X(B4)
X(C4)
X(D4)
X(A5)
X(B5)
X(C5)
X(D5)
X(A6)
X(B6)
X(C6)
X(D6)
X(A7)
X(B7)
X(C7)
X(D7)
X(F0)
X(F1)
X(F2)
X(F3)
X(F4)
X(F5)
X(F6)
X(F7)
X(Q0)
X(Q1)
X(Q2)
X(Q3)
X(Q4)
X(Q5)
X(Q6)
X(Q7)
X(OF0)
X(OF1)
X(OF2)
X(OF3)
X(OF4)
X(OF5)
X(OF6)
X(OF7)
X(X01)
X(X02)
X(X03)
X(X04)
X(X05)
X(X06)
X(X07)
X(X08)
X(N100)
X(SN10)
X(SN20)
X(N130)
X(S100)
X(S130)
X(E100)
X(EW10)
X(EW20)
X(E130)
X(W100)
X(W130)
X(N200)
X(N210)
X(N220)
X(N230)
X(N240)
X(N250)
X(N260)
X(N270)
X(S200)
X(S210)
X(S220)
X(S230)
X(S240)
X(S250)
X(S260)
X(S270)
X(E200)
X(E210)
X(E220)
X(E230)
X(E240)
X(E250)
X(E260)
X(E270)
X(W200)
X(W210)
X(W220)
X(W230)
X(W240)
X(W250)
X(W260)
X(W270)
X(N800)
X(N810)
X(N820)
X(N830)
X(S800)
X(S810)
X(S820)
X(S830)
X(E800)
X(E810)
X(E820)
X(E830)
X(W800)
X(W810)
X(W820)
X(W830)
X(CLK0)
X(CLK1)
X(CLK2)
X(LSR0)
X(LSR1)
X(LSR2)
X(CE0)
X(CE1)
X(CE2)
X(SEL0)
X(SEL1)
X(SEL2)
X(SEL3)
X(SEL4)
X(SEL5)
X(SEL6)
X(SEL7)
X(N101)
X(N131)
X(S101)
X(S131)
X(E101)
X(E131)
X(W101)
X(W131)
X(N201)
X(N211)
X(N221)
X(N231)
X(N241)
X(N251)
X(N261)
X(N271)
X(S201)
X(S211)
X(S221)
X(S231)
X(S241)
X(S251)
X(S261)
X(S271)
X(E201)
X(E211)
X(E221)
X(E231)
X(E241)
X(E251)
X(E261)
X(E271)
X(W201)
X(W211)
X(W221)
X(W231)
X(W241)
X(W251)
X(W261)
X(W271)
X(N202)
X(N212)
X(N222)
X(N232)
X(N242)
X(N252)
X(N262)
X(N272)
X(S202)
X(S212)
X(S222)
X(S232)
X(S242)
X(S252)
X(S262)
X(S272)
X(E202)
X(E212)
X(E222)
X(E232)
X(E242)
X(E252)
X(E262)
X(E272)
X(W202)
X(W212)
X(W222)
X(W232)
X(W242)
X(W252)
X(W262)
X(W272)
X(N804)
X(N814)
X(N824)
X(N834)
X(S804)
X(S814)
X(S824)
X(S834)
X(E804)
X(E814)
X(E824)
X(E834)
X(W804)
X(W814)
X(W824)
X(W834)
X(N808)
X(N818)
X(N828)
X(N838)
X(S808)
X(S818)
X(S828)
X(S838)
X(E808)
X(E818)
X(E828)
X(E838)
X(W808)
X(W818)
X(W828)
X(W838)
X(E110)
X(W110)
X(E120)
X(W120)
X(S110)
X(N110)
X(S120)
X(N120)
X(E111)
X(W111)
X(E121)
X(W121)
X(S111)
X(N111)
X(S121)
X(N121)
X(LB01)
X(LB11)
X(LB21)
X(LB31)
X(LB41)
X(LB51)
X(LB61)
X(LB71)
X(GB00)
X(GB10)
X(GB20)
X(GB30)
X(GB40)
X(GB50)
X(GB60)
X(GB70)
X(VCC)
X(VSS)
X(LT00)
X(LT10)
X(LT20)
X(LT30)
X(LT02)
X(LT13)
X(LT01)
X(LT04)
X(LBO0)
X(LBO1)
X(SS00)
X(SS40)
X(GT00)
X(GT10)
X(GBO0)
X(GBO1)
X(DI0)
X(DI1)
X(DI2)
X(DI3)
X(DI4)
X(DI5)
X(DI6)
X(DI7)
X(CIN0)
X(CIN1)
X(CIN2)
X(CIN3)
X(CIN4)
X(CIN5)
X(COUT0)
X(COUT1)
X(COUT2)
X(COUT3)
X(COUT4)
X(COUT5)
gowin: Add GUI. * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-01-29 12:45:17 +08:00
// wires
// SN
X(S10)
X(S10_loop0)
X(S13)
X(S13_loop0)
X(N10)
X(N10_loop0)
X(N13)
X(N13_loop0)
X(SN10_loop_n)
X(SN10_loop_s)
X(SN20_loop_n)
X(SN20_loop_s)
X(S20)
X(S20_loop0)
X(S20_loop1)
X(S21)
X(S21_loop0)
X(S21_loop1)
X(S22)
X(S22_loop0)
X(S22_loop1)
X(S23)
X(S23_loop0)
X(S23_loop1)
X(S24)
X(S24_loop0)
X(S24_loop1)
X(S25)
X(S25_loop0)
X(S25_loop1)
X(S26)
X(S26_loop0)
X(S26_loop1)
X(S27)
X(S27_loop0)
X(S27_loop1)
X(N20)
X(N20_loop0)
X(N20_loop1)
X(N21)
X(N21_loop0)
X(N21_loop1)
X(N22)
X(N22_loop0)
X(N22_loop1)
X(N23)
X(N23_loop0)
X(N23_loop1)
X(N24)
X(N24_loop0)
X(N24_loop1)
X(N25)
X(N25_loop0)
X(N25_loop1)
X(N26)
X(N26_loop0)
X(N26_loop1)
X(N27)
X(N27_loop0)
X(N27_loop1)
X(S80)
X(S80_loop0)
X(S80_loop1)
X(S80_loop2)
X(S80_loop3)
X(S80_loop4)
X(S80_loop5)
X(S80_loop6)
X(S80_loop7)
X(N80)
X(N80_loop0)
X(N80_loop1)
X(N80_loop2)
X(N80_loop3)
X(N80_loop4)
X(N80_loop5)
X(N80_loop6)
X(N80_loop7)
X(S81)
X(S81_loop0)
X(S81_loop1)
X(S81_loop2)
X(S81_loop3)
X(S81_loop4)
X(S81_loop5)
X(S81_loop6)
X(S81_loop7)
X(N81)
X(N81_loop0)
X(N81_loop1)
X(N81_loop2)
X(N81_loop3)
X(N81_loop4)
X(N81_loop5)
X(N81_loop6)
X(N81_loop7)
X(S82)
X(S82_loop0)
X(S82_loop1)
X(S82_loop2)
X(S82_loop3)
X(S82_loop4)
X(S82_loop5)
X(S82_loop6)
X(S82_loop7)
X(N82)
X(N82_loop0)
X(N82_loop1)
X(N82_loop2)
X(N82_loop3)
X(N82_loop4)
X(N82_loop5)
X(N82_loop6)
X(N82_loop7)
X(S83)
X(S83_loop0)
X(S83_loop1)
X(S83_loop2)
X(S83_loop3)
X(S83_loop4)
X(S83_loop5)
X(S83_loop6)
X(S83_loop7)
X(N83)
X(N83_loop0)
X(N83_loop1)
X(N83_loop2)
X(N83_loop3)
X(N83_loop4)
X(N83_loop5)
X(N83_loop6)
X(N83_loop7)
// WE
X(E10)
X(E10_loop0)
X(E13)
X(E13_loop0)
X(W10)
X(W10_loop0)
X(W13)
X(W13_loop0)
X(EW10_loop_w)
X(EW10_loop_e)
X(EW20_loop_w)
X(EW20_loop_e)
//
X(E20)
X(E20_loop0)
X(E20_loop1)
X(E21)
X(E21_loop0)
X(E21_loop1)
X(E22)
X(E22_loop0)
X(E22_loop1)
X(E23)
X(E23_loop0)
X(E23_loop1)
X(E24)
X(E24_loop0)
X(E24_loop1)
X(E25)
X(E25_loop0)
X(E25_loop1)
X(E26)
X(E26_loop0)
X(E26_loop1)
X(E27)
X(E27_loop0)
X(E27_loop1)
X(W20)
X(W20_loop0)
X(W20_loop1)
X(W21)
X(W21_loop0)
X(W21_loop1)
X(W22)
X(W22_loop0)
X(W22_loop1)
X(W23)
X(W23_loop0)
X(W23_loop1)
X(W24)
X(W24_loop0)
X(W24_loop1)
X(W25)
X(W25_loop0)
X(W25_loop1)
X(W26)
X(W26_loop0)
X(W26_loop1)
X(W27)
X(W27_loop0)
X(W27_loop1)
//
X(E80)
X(E80_loop0)
X(E80_loop1)
X(E80_loop2)
X(E80_loop3)
X(E80_loop4)
X(E80_loop5)
X(E80_loop6)
X(E80_loop7)
X(W80)
X(W80_loop0)
X(W80_loop1)
X(W80_loop2)
X(W80_loop3)
X(W80_loop4)
X(W80_loop5)
X(W80_loop6)
X(W80_loop7)
X(E81)
X(E81_loop0)
X(E81_loop1)
X(E81_loop2)
X(E81_loop3)
X(E81_loop4)
X(E81_loop5)
X(E81_loop6)
X(E81_loop7)
X(W81)
X(W81_loop0)
X(W81_loop1)
X(W81_loop2)
X(W81_loop3)
X(W81_loop4)
X(W81_loop5)
X(W81_loop6)
X(W81_loop7)
X(E82)
X(E82_loop0)
X(E82_loop1)
X(E82_loop2)
X(E82_loop3)
X(E82_loop4)
X(E82_loop5)
X(E82_loop6)
X(E82_loop7)
X(W82)
X(W82_loop0)
X(W82_loop1)
X(W82_loop2)
X(W82_loop3)
X(W82_loop4)
X(W82_loop5)
X(W82_loop6)
X(W82_loop7)
X(E83)
X(E83_loop0)
X(E83_loop1)
X(E83_loop2)
X(E83_loop3)
X(E83_loop4)
X(E83_loop5)
X(E83_loop6)
X(E83_loop7)
X(W83)
X(W83_loop0)
X(W83_loop1)
X(W83_loop2)
X(W83_loop3)
X(W83_loop4)
X(W83_loop5)
X(W83_loop6)
X(W83_loop7)
// spines
X(SPINE0)
X(SPINE1)
X(SPINE2)
X(SPINE3)
X(SPINE4)
X(SPINE5)
X(SPINE6)
X(SPINE7)
X(SPINE8)
X(SPINE9)
X(SPINE10)
X(SPINE11)
X(SPINE12)
X(SPINE13)
X(SPINE14)
X(SPINE15)
X(SPINE16)
X(SPINE17)
X(SPINE18)
X(SPINE19)
X(SPINE20)
X(SPINE21)
X(SPINE22)
X(SPINE23)
X(SPINE24)
X(SPINE25)
X(SPINE26)
X(SPINE27)
X(SPINE28)
X(SPINE29)
X(SPINE30)
X(SPINE31)
Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
// slice items
X(SLICE)
X(CLK)
X(LSR)
X(CE)
X(Q)
X(F)
X(A)
X(B)
X(C)
X(D)
// iob items
X(IOB)
X(I)
X(O)
X(IO)
X(OE)
gowin: Add support for true differential output The new primitive appears as an amalgamation of two existing OBUF primitives. Compatible with older versions of apicula, although, of course, using TLVDS_OBUF with old databases will not bring the desired result, but no crash. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-23 13:53:04 +08:00
X(OB)
Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
// bels
X(DFF0)
X(DFF1)
X(DFF2)
X(DFF3)
X(DFF4)
X(DFF5)
X(LUT0)
X(LUT1)
X(LUT2)
X(LUT3)
X(LUT4)
X(LUT5)
X(LUT6)
X(LUT7)
X(IOBA)
X(IOBB)
X(IOBC)
X(IOBD)
X(IOBE)
X(IOBF)
X(IOBG)
X(IOBH)
X(IOBI)
X(IOBJ)
gowin: Add simplified IO cells processing Some models have I/O cells that are IOBUFs, and other types (IBUFs and OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done with general-purpose routing so it's best to do it here to avoid conflicts. For this purpose, in the new bases, these special cells are of type IOBS (IOB Simplified). The proposed changes are compatible with bases of previous versions of Apycula and do not require changing .CST constraint files. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-12-20 13:48:38 +08:00
// simplified iobs
X(IOBS)
X(IOBAS)
X(IOBBS)
X(IOBCS)
X(IOBDS)
X(IOBES)
X(IOBFS)
X(IOBGS)
X(IOBHS)
X(IOBIS)
X(IOBJS)
gowin: add support for ODDR primitive Compatible with older versions of apicula bases. Also small fixes and as the number of virtual Bels grows it is necessary to assign them Z coordinate in a centralized way to avoid conflicts and for this purpose introduced the BelZ enum. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-15 09:02:37 +08:00
// IOLOGIC
X(TX)
gowin: Consider the peculiarity of GW1BR-9C The GW1NR-9C chip ODDR implementation differs from all other supported chips by two suspicious inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-26 18:56:30 +08:00
X(XXX_VSS)
X(XXX_VCC)
gowin: add support for ODDR primitive Compatible with older versions of apicula bases. Also small fixes and as the number of virtual Bels grows it is necessary to assign them Z coordinate in a centralized way to avoid conflicts and for this purpose introduced the BelZ enum. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-15 09:02:37 +08:00
X(OBUF_TYPE)
X(SBUF)
X(DBUF)
X(ODDR)
X(ODDRC)
X(ODDRA)
X(ODDRB)
X(ODDRCA)
X(ODDRCB)
gowin: add support for wide LUTs. * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-07 16:38:33 +08:00
// Wide LUTs
X(MUX2_LUT5)
X(MUX2_LUT6)
X(MUX2_LUT7)
X(MUX2_LUT8)
X(GW_MUX2_LUT5)
X(GW_MUX2_LUT6)
X(GW_MUX2_LUT7)
X(GW_MUX2_LUT8)
gowin: Add GUI. * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-01-29 12:45:17 +08:00
X(I0MUX0)
X(I1MUX0)
X(I0MUX1)
X(I1MUX1)
X(I0MUX2)
X(I1MUX2)
X(I0MUX3)
X(I1MUX3)
X(I0MUX4)
X(I1MUX4)
X(I0MUX5)
X(I1MUX5)
X(I0MUX6)
X(I1MUX6)
X(I0MUX7)
X(I1MUX7)
gowin: add support for wide LUTs. * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-07 16:38:33 +08:00
gowin: Add ALU support. - Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-22 12:41:18 +08:00
// ALU
X(ALU)
X(GND)
X(ALU_MODE)
Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
// DFF types
X(DFF)
X(DFFE)
X(DFFS)
X(DFFSE)
X(DFFR)
X(DFFRE)
X(DFFP)
X(DFFPE)
X(DFFC)
X(DFFCE)
X(DFFN)
X(DFFNE)
X(DFFNS)
X(DFFNSE)
X(DFFNR)
X(DFFNRE)
X(DFFNP)
X(DFFNPE)
X(DFFNC)
X(DFFNCE)
// IOB types
X(IBUF)
X(OBUF)
X(IOBUF)
X(TBUF)
gowin: Add support for true differential output The new primitive appears as an amalgamation of two existing OBUF primitives. Compatible with older versions of apicula, although, of course, using TLVDS_OBUF with old databases will not bring the desired result, but no crash. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-23 13:53:04 +08:00
X(TLVDS_OBUF)
Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
gowin: Add the Global Set/Reset primitive GSR is added automatically if it was not instantiated by the user explicitly. Compatible with old apicula bases, the functionality does not work, but the crash does not happen --- just a warning. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-12 21:05:42 +08:00
// global set/reset
X(GSR)
X(GSR0)
X(GSRI)
Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
// primitive attributes
X(INIT)
X(FF_USED)
X(FF_TYPE)
X(INPUT_USED)
X(OUTPUT_USED)
X(ENABLE_USED)
X(BEL)
gowin: Add support for true differential output The new primitive appears as an amalgamation of two existing OBUF primitives. Compatible with older versions of apicula, although, of course, using TLVDS_OBUF with old databases will not bring the desired result, but no crash. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-23 13:53:04 +08:00
X(DIFF)
X(DIFF_TYPE)
Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
// ports
X(EN)
X(E)
X(Y)
X(PAD)
X(RESET)
X(SET)
X(PRESET)
X(CLEAR)
X(I0)
X(I1)
X(I2)
X(I3)
X(OEN)
gowin: add support for wide LUTs. * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-07 16:38:33 +08:00
X(S0)
X(SEL)
gowin: Add ALU support. - Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-22 12:41:18 +08:00
X(SUM)
X(CIN)
X(COUT)
gowin: add support for wide LUTs. * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-07 16:38:33 +08:00
X(OF)
Gowin: use global VCC and VSS nets (#956) * use global VCC and VSS nets * derp * remove init parameter
2022-03-20 02:44:08 +08:00
X(V)
X(G)
Gowin target (#542) * load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
2020-12-30 22:59:55 +08:00
// timing
X(X0)
X(FX1)
X(X2)
X(X8)
X(PIO_CENT_PCLK)
X(CENT_SPINE_PCLK)
X(SPINE_TAP_PCLK)
X(TAP_BRANCH_PCLK)
X(BRANCH_PCLK)
X(clksetpos)
X(clkholdpos)
X(clk_qpos)
X(a_f)
X(b_f)
X(c_f)
X(d_f)
gowin: Replace the zero delays with reasonable values. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-09 18:26:18 +08:00
X(fx_ofx1)
X(I01)
gowin: Add GUI. * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-01-29 12:45:17 +08:00
// GUI
X(DECAL_LUT_ACTIVE)
X(DECAL_LUT_INACTIVE)
X(DECAL_LUTDFF_ACTIVE)
X(DECAL_LUTDFF_INACTIVE)
X(DECAL_LUT_UNUSED_DFF_ACTIVE)
X(DECAL_GRP_LUT)
X(DECAL_CRU)
X(DECAL_MUXUPPER_INACTIVE)
X(DECAL_MUXUPPER_ACTIVE)
X(DECAL_MUXLOWER_INACTIVE)
X(DECAL_MUXLOWER_ACTIVE)
X(DECAL_IOB_INACTIVE)
X(DECAL_IOB_ACTIVE)
X(DECAL_IOBS_INACTIVE)
X(DECAL_IOBS_ACTIVE)
X(DECAL_ALU_ACTIVE)
refactor: Use constids instead of id("..") Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-17 01:09:54 +08:00
X(SINGLE_INPUT_MUX)
X(cst)
X(none)
X(pack)
X(place)
X(placer)
X(route)
X(router)
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