2021-02-26 01:11:32 +08:00
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yosys -import
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2021-03-12 20:53:09 +08:00
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read_verilog $::env(SOURCES)
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2021-02-26 01:11:32 +08:00
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synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
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techmap -map ../remap.v
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# opt_expr -undriven makes sure all nets are driven, if only by the $undef
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# net.
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opt_expr -undriven
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opt_clean
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setundef -zero -params
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2021-03-12 20:53:09 +08:00
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write_json $::env(OUT_JSON)
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