352 lines
13 KiB
C++
352 lines
13 KiB
C++
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Symbiflow Authors
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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#include "log.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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void DedicatedInterconnect::init(const Context *ctx) {
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this->ctx = ctx;
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if(ctx->debug) {
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log_info("Finding dedicated interconnect!\n");
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}
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find_dedicated_interconnect();
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if(ctx->debug) {
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print_dedicated_interconnect();
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}
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}
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bool DedicatedInterconnect::check_routing(
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BelId src_bel, IdString src_bel_pin,
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BelId dst_bel, IdString dst_bel_pin) const {
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// FIXME: Implement.
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return false;
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}
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bool DedicatedInterconnect::isBelLocationValid(BelId bel, const CellInfo* cell) const {
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NPNR_ASSERT(bel != BelId());
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Loc bel_loc = ctx->getBelLocation(bel);
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const auto &bel_data = bel_info(ctx->chip_info, bel);
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for(const auto &port_pair : cell->ports) {
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IdString port_name = port_pair.first;
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NetInfo *net = port_pair.second.net;
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if(net == nullptr) {
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continue;
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}
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// Only check sink BELs.
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if(net->driver.cell == cell && net->driver.port == port_name) {
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continue;
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}
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// This net doesn't have a driver, probably not valid?
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NPNR_ASSERT(net->driver.cell != nullptr);
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BelId driver_bel = net->driver.cell->bel;
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if(driver_bel == BelId()) {
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return true;
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}
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const auto &driver_bel_data = bel_info(ctx->chip_info, driver_bel);
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Loc driver_loc = ctx->getBelLocation(driver_bel);
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DeltaTileTypeBelPin driver_type_bel_pin;
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driver_type_bel_pin.delta_x = driver_loc.x - bel_loc.x;
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driver_type_bel_pin.delta_y = driver_loc.y - bel_loc.y;
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driver_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[driver_bel.tile].type;
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driver_type_bel_pin.type_bel_pin.bel_index = driver_bel.index;
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driver_type_bel_pin.type_bel_pin.bel_pin = get_only_value(ctx->getBelPinsForCellPin(net->driver.cell, net->driver.port));
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for(IdString bel_pin : ctx->getBelPinsForCellPin(cell, port_name)) {
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TileTypeBelPin type_bel_pin;
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type_bel_pin.tile_type = ctx->chip_info->tiles[bel.tile].type;
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type_bel_pin.bel_index = bel.index;
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type_bel_pin.bel_pin = bel_pin;
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auto iter = pins_with_dedicate_interconnect.find(type_bel_pin);
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if(iter == pins_with_dedicate_interconnect.end()) {
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// This BEL pin doesn't have a dedicate interconnect.
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continue;
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}
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if(bel.tile == driver_bel.tile && bel_data.site == driver_bel_data.site) {
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// This is a site local routing, even though this is a sink
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// with a dedicated interconnect.
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continue;
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}
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// Do fast routing check to see if the pair of driver and sink
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// every are valid.
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if(iter->second.count(driver_type_bel_pin) == 0) {
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if(ctx->verbose) {
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log_info("BEL %s is not valid because pin %s cannot be driven by %s/%s\n",
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ctx->nameOfBel(bel),
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bel_pin.c_str(ctx),
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ctx->nameOfBel(driver_bel),
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driver_type_bel_pin.type_bel_pin.bel_pin.c_str(ctx));
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}
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return false;
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}
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// Do detailed routing check to ensure driver can reach sink.
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//
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// FIXME: This might be too slow, but it handles a case on
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// SLICEL.COUT -> SLICEL.CIN has delta_y = {1, 2}, but the
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// delta_y=2 case is rare.
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if(!check_routing(
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driver_bel, driver_type_bel_pin.type_bel_pin.bel_pin,
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bel, bel_pin)) {
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if(ctx->verbose) {
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log_info("BEL %s is not valid because pin %s cannot be driven by %s/%s (via detailed check)\n",
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ctx->nameOfBel(bel),
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bel_pin.c_str(ctx),
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ctx->nameOfBel(driver_bel),
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driver_type_bel_pin.type_bel_pin.bel_pin.c_str(ctx));
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}
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return false;
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}
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}
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}
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return true;
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}
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void DedicatedInterconnect::print_dedicated_interconnect() const {
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log_info("Found %zu sinks with dedicated interconnect\n", pins_with_dedicate_interconnect.size());
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std::vector<TileTypeBelPin> sorted_keys;
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for(const auto & sink_to_srcs : pins_with_dedicate_interconnect) {
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sorted_keys.push_back(sink_to_srcs.first);
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}
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std::sort(sorted_keys.begin(), sorted_keys.end());
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for(const auto & dst : sorted_keys) {
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for(const auto & src : pins_with_dedicate_interconnect.at(dst)) {
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const TileTypeInfoPOD & src_tile_type = ctx->chip_info->tile_types[src.type_bel_pin.tile_type];
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const BelInfoPOD & src_bel_info = src_tile_type.bel_data[src.type_bel_pin.bel_index];
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IdString src_site_type = IdString(src_tile_type.site_types[src_bel_info.site]);
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IdString src_bel_pin = src.type_bel_pin.bel_pin;
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const TileTypeInfoPOD & dst_tile_type = ctx->chip_info->tile_types[dst.tile_type];
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const BelInfoPOD & dst_bel_info = dst_tile_type.bel_data[dst.bel_index];
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IdString dst_site_type = IdString(dst_tile_type.site_types[dst_bel_info.site]);
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IdString dst_bel_pin = dst.bel_pin;
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log_info("%s.%s/%s/%s (%d, %d) -> %s.%s/%s/%s\n",
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IdString(src_tile_type.name).c_str(ctx),
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src_site_type.c_str(ctx),
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IdString(src_bel_info.name).c_str(ctx),
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src_bel_pin.c_str(ctx),
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src.delta_x,
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src.delta_y,
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IdString(dst_tile_type.name).c_str(ctx),
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dst_site_type.c_str(ctx),
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IdString(dst_bel_info.name).c_str(ctx),
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dst_bel_pin.c_str(ctx));
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}
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}
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}
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void DedicatedInterconnect::find_dedicated_interconnect() {
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for(BelId bel : ctx->getBels()) {
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const auto & bel_data = bel_info(ctx->chip_info, bel);
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if(bel_data.category != BEL_CATEGORY_LOGIC) {
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continue;
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}
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if(bel_data.synthetic) {
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continue;
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}
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for(size_t i = 0; i < bel_data.num_bel_wires; ++i) {
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if(bel_data.types[i] != PORT_IN) {
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continue;
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}
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WireId wire;
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wire.tile = bel.tile;
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wire.index = bel_data.wires[i];
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expand_bel(bel, IdString(bel_data.ports[i]), wire);
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}
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}
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}
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// All legal routes involved at most 2 sites, the source site and the sink
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// site. The source site and sink sites may be the same, but that is not
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// dedicated routing, that is intra site routing.
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//
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// Dedicated routing must leave the sink site, traverse some routing and
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// terminate at another site. Routing that "flys" over a site is expressed as
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// a psuedo-pip connected the relevant site pin wires, rather than traversing
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// the site.
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enum WireNodeState {
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IN_SINK_SITE = 0,
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IN_ROUTING = 1,
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IN_SOURCE_SITE = 2
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};
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struct WireNode {
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WireId wire;
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WireNodeState state;
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int depth;
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};
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// Maximum depth that a dedicate interconnect is considered.
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//
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// Routing networks with depth <= kMaxDepth is considers a dedicated
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// interconnect.
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constexpr int kMaxDepth = 20;
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void DedicatedInterconnect::expand_bel(BelId bel, IdString pin, WireId wire) {
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NPNR_ASSERT(bel != BelId());
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std::vector<WireNode> nodes_to_expand;
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const auto & src_wire_data = ctx->wire_info(wire);
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NPNR_ASSERT(src_wire_data.site != -1);
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WireNode wire_node;
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wire_node.wire = wire;
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wire_node.state = IN_SINK_SITE;
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wire_node.depth = 0;
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nodes_to_expand.push_back(wire_node);
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Loc sink_loc = ctx->getBelLocation(bel);
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std::unordered_set<DeltaTileTypeBelPin> srcs;
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while(!nodes_to_expand.empty()) {
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WireNode node_to_expand = nodes_to_expand.back();
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nodes_to_expand.pop_back();
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for(PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
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if(ctx->is_pip_synthetic(pip)) {
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continue;
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}
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WireId wire = ctx->getPipSrcWire(pip);
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if(wire == WireId()) {
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continue;
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}
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WireNode next_node;
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next_node.wire = wire;
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next_node.depth = node_to_expand.depth += 1;
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if(next_node.depth > kMaxDepth) {
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// Dedicated routing should reach sources by kMaxDepth (with
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// tuning).
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//
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// FIXME: Consider removing kMaxDepth and use kMaxSources?
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return;
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}
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auto const & wire_data = ctx->wire_info(wire);
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bool expand_node = true;
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if(ctx->is_site_port(pip)) {
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switch(node_to_expand.state) {
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case IN_SINK_SITE:
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NPNR_ASSERT(wire_data.site == -1);
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next_node.state = IN_ROUTING;
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break;
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case IN_ROUTING:
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NPNR_ASSERT(wire_data.site != -1);
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if(wire_data.site == src_wire_data.site) {
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// Dedicated routing won't have straight loops,
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// general routing looks like that.
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return;
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}
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next_node.state = IN_SOURCE_SITE;
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break;
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case IN_SOURCE_SITE:
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// Once entering a site, do not leave it again.
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// This path is not a legal route!
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expand_node = false;
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break;
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default:
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// Unreachable!!!
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NPNR_ASSERT(false);
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}
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} else {
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next_node.state = node_to_expand.state;
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}
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if(expand_node) {
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nodes_to_expand.push_back(next_node);
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} else {
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continue;
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}
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if(next_node.state == IN_SOURCE_SITE) {
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for(BelPin bel_pin : ctx->getWireBelPins(wire)) {
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BelId src_bel = bel_pin.bel;
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auto const & bel_data = bel_info(ctx->chip_info, src_bel);
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NPNR_ASSERT(bel_data.site != src_wire_data.site);
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if(bel_data.category != BEL_CATEGORY_LOGIC) {
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continue;
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}
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if(bel_data.synthetic) {
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continue;
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}
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if(ctx->getBelPinType(bel_pin.bel, bel_pin.pin) != PORT_OUT) {
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continue;
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}
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Loc src_loc = ctx->getBelLocation(src_bel);
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DeltaTileTypeBelPin delta_type_bel_pin;
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delta_type_bel_pin.delta_x = src_loc.x - sink_loc.x;
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delta_type_bel_pin.delta_x = src_loc.y - sink_loc.y;
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delta_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[src_bel.tile].type;
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delta_type_bel_pin.type_bel_pin.bel_index = src_bel.index;
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delta_type_bel_pin.type_bel_pin.bel_pin = bel_pin.pin;
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srcs.emplace(delta_type_bel_pin);
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}
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}
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}
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}
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TileTypeBelPin type_bel_pin;
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type_bel_pin.tile_type = ctx->chip_info->tiles[bel.tile].type;
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type_bel_pin.bel_index = bel.index;
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type_bel_pin.bel_pin = pin;
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auto result = pins_with_dedicate_interconnect.emplace(type_bel_pin, srcs);
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if(!result.second) {
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// type_bel_pin was already present! Add any new sources from this
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// sink type (if any);
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for(auto src : srcs) {
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result.first->second.emplace(src);
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}
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}
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}
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NEXTPNR_NAMESPACE_END
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