111 lines
3.4 KiB
C++
111 lines
3.4 KiB
C++
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "cells.h"
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#include "design_utils.h"
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#include "log.h"
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static void add_port(CellInfo *cell, IdString name, PortType dir)
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{
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cell->ports[name] = PortInfo{name, nullptr, dir};
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}
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CellInfo *create_ice_cell(Design *design, IdString type, IdString name)
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{
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static int auto_idx = 0;
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CellInfo *new_cell = new CellInfo();
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if (name == IdString()) {
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new_cell->name =
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IdString("$nextpnr_" + type + "_" + std::to_string(auto_idx++));
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} else {
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new_cell->name = name;
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}
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if (type == "ICESTORM_LC") {
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new_cell->params["LUT_INIT"] = "0";
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new_cell->params["NEG_CLK"] = "0";
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new_cell->params["CARRY_ENABLE"] = "0";
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new_cell->params["DFF_ENABLE"] = "0";
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new_cell->params["SET_NORESET"] = "0";
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new_cell->params["ASYNC_SR"] = "0";
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add_port(new_cell, "I0", PORT_IN);
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add_port(new_cell, "I1", PORT_IN);
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add_port(new_cell, "I2", PORT_IN);
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add_port(new_cell, "I3", PORT_IN);
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add_port(new_cell, "CIN", PORT_IN);
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add_port(new_cell, "CLK", PORT_IN);
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add_port(new_cell, "CEN", PORT_IN);
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add_port(new_cell, "SR", PORT_IN);
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add_port(new_cell, "LO", PORT_OUT);
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add_port(new_cell, "O", PORT_OUT);
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add_port(new_cell, "OUT", PORT_OUT);
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} else {
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log_error("unable to create iCE40 cell of type %s", type.c_str());
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}
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design->cells[new_cell->name] = new_cell;
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return new_cell;
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}
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void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
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{
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lc->params["DFF_ENABLE"] = "1";
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std::string config = std::string(dff->type).substr(6);
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auto citer = config.begin();
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replace_port(dff, "C", lc, "CLK");
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if (citer != config.end() && *citer == 'N') {
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lc->params["NEG_CLK"] = "1";
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++citer;
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} else {
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lc->params["NEG_CLK"] = "0";
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}
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if (citer != config.end() && *citer == 'E') {
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replace_port(dff, "E", lc, "CEN");
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++citer;
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}
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if (citer != config.end()) {
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if ((config.end() - citer) >= 2) {
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assert(*(citer++) == 'S');
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lc->params["ASYNC_SR"] = "1";
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} else {
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lc->params["ASYNC_SR"] = "0";
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}
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if (*citer == 'S') {
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replace_port(dff, "S", lc, "SR");
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lc->params["SET_NORESET"] = "1";
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} else {
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assert(*citer == 'R');
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replace_port(dff, "R", lc, "SR");
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lc->params["SET_NORESET"] = "0";
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}
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}
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assert(citer == config.end());
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if (pass_thru_lut) {
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lc->params["LUT_INIT"] = "2";
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replace_port(dff, "D", lc, "I0");
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}
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}
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