39 lines
604 B
VHDL
39 lines
604 B
VHDL
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library ieee ;
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context ieee.ieee_std_context;
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use work.components.all;
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entity top is
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port (
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pin1: out std_logic
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);
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attribute LOC: string;
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attribute LOC of pin1: signal is "13";
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end;
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architecture arch of top is
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signal clk: std_logic;
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signal led_timer: unsigned(23 downto 0) := (others=>'0');
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begin
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internal_oscillator_inst: OSCH
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generic map (
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NOM_FREQ => "16.63"
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)
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port map (
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STDBY => '0',
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OSC => clk
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);
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process(clk)
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begin
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if rising_edge(clk) then
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led_timer <= led_timer + 1;
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end if;
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end process;
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pin1 <= led_timer(led_timer'left);
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end;
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