2019-02-24 05:06:42 +08:00
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# nextpnr-ecp5 Primitive Support List
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nextpnr-ecp5 currently supports the following primitives:
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2020-10-01 16:02:29 +08:00
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- **ALU54B** - 54-bit ternary adder/subtractor (limited support, must be manually placed)
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- **CCU2C** - 2x LUT4 with carry logic
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2020-10-01 03:29:13 +08:00
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- **CLKDIVF** - clock divider
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2020-10-01 16:02:29 +08:00
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- **DCUA** - dual channel 3/5Gbps SERDES
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2020-10-01 03:29:13 +08:00
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- **DDRDLLA** - 90° delay for DQS or clock for DDR interface
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- **DELAYF** - configurable signal delay
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- **DELAYG** - simple signal delay
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- **DP16KD** - true dual port block RAM
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2020-10-01 16:02:29 +08:00
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- **DQSBUFM** - DQS control for DDR memory
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2020-10-01 03:29:13 +08:00
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- **DTR** - die temperature readout *notice: The IO-names in the FPGA Libraries Reference Guide 08/16 are wrong*
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2020-10-01 16:02:29 +08:00
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- **ECLKSYNCB** - edge clock stop/synchronisation
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- **EHXPLLL** - phase-locked-loop
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- **EXTREFB** - reference clock input buffer for external clock for SERDES
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2020-10-01 03:29:13 +08:00
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- **GSR** - global set/reset interface
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2020-10-01 16:02:29 +08:00
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- **IDDR71B** - 7:1 input gearbox
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- **IDDRX1F** - generic 1:2 input DDR
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- **IDDRX2DQA** - DDR2/3 memory 1:4 input interface
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- **IDDRX2F** - generic 1:4 input DDR
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- **JTAGG** - JTAG access to fabric
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- **L6MUX21** - 2 input multiplexer for LUT6 and above
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2020-10-01 03:29:13 +08:00
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- **LUT4** - 4 input Look Up Table
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- **MULT18X18D** - DSP multiplier (cascade functionality not supported)
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2020-10-01 16:02:29 +08:00
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- **ODDR71B** - 7:1 ODDR implementation
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- **ODDRX1F** - generic 2:1 output DDR
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- **ODDRX2DQA** - memory 4:1 output DDR primitive for DQ outputs
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- **ODDRX2DQSB** - memory 4:1 output DDR primitive for DQS outputs
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- **ODDRX2F** - generic 4:1 output DDR
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- **OSCG** - internal oscillator
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- **OSHX2A** - memory 4:1 output DDR primitive for address and command
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- **PCSCLKDIV** - clock divider for SERDES clock outputs
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- **PFUMX** - 2 input multiplexer for LUT5s
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2020-10-01 03:29:13 +08:00
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- **SEDGA** - allows checking configuration data for soft-errors, see TN1268 (untested)
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2020-10-01 16:02:29 +08:00
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- **TRELLIS_DPR16X4** - 16x4 LUTRAM
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- **TRELLIS_ECLKBUF** - internal edge clock buffer
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- **TRELLIS_FF** - SLICE flipflop
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- **TRELLIS_IO** - tristate IO, mapped by Yosys from BB, IB, OB, etc
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- **TRELLIS_SLICE** - logic SLICE (2x LUT4, 2x FF, 2x MUX2, CCU2 carry)
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2020-10-01 03:29:13 +08:00
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- **TSHX2DQA** - tristate control for DQ data output for DDR2 and DDR3 memory
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- **TSHX2DQSA** - tristate control for DQS output
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2020-10-01 16:02:29 +08:00
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- **USRMCLK** - provides access to SPI flash clock (MCLK)
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