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8c38e7ba61
nextpnr/machxo2/constids.inc

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Use TRELLIS primitives
2023-03-18 02:00:05 +08:00
X(TRELLIS_SLICE)
machxo2: Add initial set of constids for packing.
2020-11-24 00:20:39 +08:00
X(A0)
X(B0)
X(C0)
X(D0)
X(A1)
X(B1)
X(C1)
X(D1)
X(M0)
X(M1)
X(FCI)
X(FXA)
X(FXB)
X(CLK)
X(LSR)
X(CE)
port ecp5 split slice to machxo2
2023-03-28 01:40:55 +08:00
X(CEA)
X(CEW)
machxo2: Add initial set of constids for packing.
2020-11-24 00:20:39 +08:00
X(DI0)
X(DI1)
X(WD0)
X(WD1)
X(WAD0)
X(WAD1)
X(WAD2)
X(WAD3)
X(WRE)
X(WCK)
X(F0)
X(Q0)
X(F1)
X(Q1)
X(FCO)
X(OFX0)
X(OFX1)
X(WDO0)
X(WDO1)
X(WDO2)
X(WDO3)
X(WADO0)
X(WADO1)
X(WADO2)
X(WADO3)
X(MODE)
X(GSR)
X(SRMODE)
X(CEMUX)
X(CLKMUX)
X(LSRMUX)
X(LSRONMUX)
X(LUT0_INITVAL)
X(LUT1_INITVAL)
machxo2: Fix REGMODE identifier (per slice, not per-FF).
2021-02-01 12:29:04 +08:00
X(REGMODE)
machxo2: Add initial set of constids for packing.
2020-11-24 00:20:39 +08:00
X(REG0_SD)
X(REG1_SD)
X(REG0_REGSET)
X(REG1_REGSET)
X(CCU2_INJECT1_0)
X(CCU2_INJECT1_1)
X(WREMUX)
Use TRELLIS primitives
2023-03-18 02:00:05 +08:00
X(TRELLIS_FF)
machxo2: Add initial set of constids for packing.
2020-11-24 00:20:39 +08:00
X(DI)
X(Q)
X(REGSET)
Use TRELLIS primitives
2023-03-18 02:00:05 +08:00
X(TRELLIS_IO)
machxo2: Add initial set of constids for packing.
2020-11-24 00:20:39 +08:00
X(I)
X(EN)
X(O)
X(DIR)
X(LUT4)
X(A)
X(B)
X(C)
X(D)
X(Z)
X(INIT)
X(PFUMX)
X(ALUT)
X(BLUT)
X(L6MUX21)
X(SD)
machxo2: Import constids and BELs into facade_import.
2020-12-04 11:36:38 +08:00
X(T)
X(IOLDO)
X(IOLTO)
X(OSCH)
X(OSC)
X(SEDSTDBY)
X(DCCA)
X(CLKI)
X(CLKO)
X(DCMA)
X(CLK0)
X(CLK1)
X(SEL)
X(DCMOUT)
refactor: Use constids instead of id("..") Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-17 01:09:54 +08:00
X(BEL)
X(GND)
X(IO_TYPE)
X(LOC)
X(NOM_FREQ)
X(VCC)
Enable wires and add dummy wire type for now
2023-03-10 22:29:59 +08:00
X(WIRE_TYPE_NONE)
add missing bind and lutperm
2023-03-30 21:24:53 +08:00
X(TILE_WIRE_ID)
Enable wires and add dummy wire type for now
2023-03-10 22:29:59 +08:00
refactor: Use constids instead of id("..") Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-17 01:09:54 +08:00
X(machxo2)
X(pack)
X(place)
X(placer)
X(route)
X(router)
port ecp5 split slice to machxo2
2023-03-28 01:40:55 +08:00
X(TRELLIS_COMB)
X(TRELLIS_RAMW)
X(WD)
X(OFX)
X(F)
X(M)
Use CCU2D cell
2023-03-31 20:37:01 +08:00
X(CCU2D)
port ecp5 split slice to machxo2
2023-03-28 01:40:55 +08:00
X(CCU2_INJECT1)
X(INJECT1_0)
X(INJECT1_1)
X(TRELLIS_DPR16X4)
X(INITVAL)
X(INIT0)
X(INIT1)
X(DATAMUX_ODDR)
X(DATAMUX_MDDR)
X(CIN)
X(S0)
X(S1)
X(COUT)
X(E)
X(Y)
Add constants for new bels
2023-04-10 16:18:18 +08:00
X(WCKMUX)
X(EHXPLLJ)
X(CLKFB)
X(PHASESEL0)
Add missing bel pins
2023-04-10 17:16:57 +08:00
X(PHASESEL1)
Add constants for new bels
2023-04-10 16:18:18 +08:00
X(PHASEDIR)
X(PHASESTEP)
X(LOADREG)
X(STDBY)
X(PLLWAKESYNC)
X(RST)
Add missing bel pins
2023-04-10 17:16:57 +08:00
X(RESETM)
X(RESETC)
X(RESETD)
Add constants for new bels
2023-04-10 16:18:18 +08:00
X(ENCLKOP)
X(ENCLKOS)
X(ENCLKOS2)
X(ENCLKOS3)
Add missing bel pins
2023-04-10 17:16:57 +08:00
X(PLLCLK)
X(PLLRST)
X(PLLSTB)
X(PLLWE)
X(PLLDATI0)
X(PLLDATI1)
X(PLLDATI2)
X(PLLDATI3)
X(PLLDATI4)
X(PLLDATI5)
X(PLLDATI6)
X(PLLDATI7)
X(PLLADDR0)
X(PLLADDR1)
X(PLLADDR2)
X(PLLADDR3)
X(PLLADDR4)
Add constants for new bels
2023-04-10 16:18:18 +08:00
X(CLKOP)
X(CLKOS)
X(CLKOS2)
X(CLKOS3)
X(LOCK)
X(INTLOCK)
X(REFCLK)
X(CLKINTFB)
Add missing bel pins
2023-04-10 17:16:57 +08:00
X(DPHSRC)
X(PLLDATO0)
X(PLLDATO1)
X(PLLDATO2)
X(PLLDATO3)
X(PLLDATO4)
X(PLLDATO5)
X(PLLDATO6)
X(PLLDATO7)
X(PLLACK)
Add constants for new bels
2023-04-10 16:18:18 +08:00
X(DP8KC)
X(DIA0)
X(DIA1)
X(DIA2)
X(DIA3)
X(DIA4)
X(DIA5)
X(DIA6)
X(DIA7)
X(DIA8)
X(ADA0)
X(ADA1)
X(ADA2)
X(ADA3)
X(ADA4)
X(ADA5)
X(ADA6)
X(ADA7)
X(ADA8)
X(ADA9)
X(ADA10)
X(ADA11)
X(ADA12)
X(OCEA)
X(CLKA)
X(WEA)
X(CSA2)
X(CSA1)
X(CSA0)
X(RSTA)
X(DIB0)
X(DIB1)
X(DIB2)
X(DIB3)
X(DIB4)
X(DIB5)
X(DIB6)
X(DIB7)
X(DIB8)
X(ADB0)
X(ADB1)
X(ADB2)
X(ADB3)
X(ADB4)
X(ADB5)
X(ADB6)
X(ADB7)
X(ADB8)
X(ADB9)
X(ADB10)
X(ADB11)
X(ADB12)
X(CEB)
X(OCEB)
X(CLKB)
X(WEB)
X(CSB2)
X(CSB1)
X(CSB0)
X(RSTB)
X(DOA0)
X(DOA1)
X(DOA2)
X(DOA3)
X(DOA4)
X(DOA5)
X(DOA6)
X(DOA7)
X(DOA8)
X(DOB0)
X(DOB1)
X(DOB2)
X(DOB3)
X(DOB4)
X(DOB5)
X(DOB6)
X(DOB7)
X(DOB8)
X(AE)
X(AF)
X(EF)
X(FF)
X(WID)
X(CLKI_DIV)
X(CLKFB_DIV)
X(CLKOP_DIV)
X(CLKOS_DIV)
X(CLKOS2_DIV)
X(CLKOS3_DIV)
X(CLOCK_ENABLE_PORTS)
X(CLKOP_ENABLE)
X(CLKOS_ENABLE)
X(CLKOS2_ENABLE)
X(CLKOS3_ENABLE)
X(VCO_BYPASS_A0)
X(VCO_BYPASS_B0)
X(VCO_BYPASS_C0)
X(VCO_BYPASS_D0)
X(CLKOP_CPHASE)
X(CLKOS_CPHASE)
X(CLKOS2_CPHASE)
X(CLKOS3_CPHASE)
X(CLKOP_FPHASE)
X(CLKOS_FPHASE)
X(CLKOS2_FPHASE)
X(CLKOS3_FPHASE)
X(FEEDBK_PATH)
X(KVCO)
X(LPF_CAPACITOR)
X(LPF_RESISTOR)
X(ICP_CURRENT)
X(FRACN_ENABLE)
X(FRACN_DIV)
X(FRACN_ORDER)
X(CLKOP_TRIM_POL)
X(CLKOP_TRIM_DELAY)
X(CLKOS_TRIM_POL)
X(CLKOS_TRIM_DELAY)
X(PLL_EXPERT)
X(PLL_USE_WB)
X(PREDIVIDER_MUXA1)
X(PREDIVIDER_MUXB1)
X(PREDIVIDER_MUXC1)
X(PREDIVIDER_MUXD1)
X(OUTDIVIDER_MUXA2)
X(OUTDIVIDER_MUXB2)
X(OUTDIVIDER_MUXC2)
X(OUTDIVIDER_MUXD2)
X(FREQ_LOCK_ACCURACY)
X(PLL_LOCK_MODE)
X(PLL_LOCK_DELAY)
X(GMC_GAIN)
X(GMC_TEST)
X(MFG1_TEST)
X(MFG2_TEST)
X(MFG_FORCE_VFILTER)
X(MFG_ICP_TEST)
X(MFG_EN_UP)
X(MFG_FLOAT_ICP)
X(MFG_GMC_PRESET)
X(MFG_LF_PRESET)
X(MFG_GMC_RESET)
X(MFG_LF_RESET)
X(MFG_LF_RESGRND)
X(MFG_GMCREF_SEL)
X(MFG_ENABLE_FILTEROPAMP)
X(STDBY_ENABLE)
X(REFIN_RESET)
X(SYNC_ENABLE)
X(INT_LOCK_STICKY)
X(DPHASE_SOURCE)
X(INTFB_WAKE)
X(PLLRST_ENA)
X(MRST_ENA)
X(DCRST_ENA)
X(DDRST_ENA)
X(DATA_WIDTH_A)
X(DATA_WIDTH_B)
X(WRITEMODE_A)
X(WRITEMODE_B)
X(CSDECODE_A)
X(CSDECODE_B)
X(REGMODE_A)
X(REGMODE_B)
X(RESETMODE)
X(ASYNC_RESET_RELEASE)
X(RSTAMUX)
X(RSTBMUX)
X(WEAMUX)
X(WEBMUX)
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