2023-06-28 08:16:29 +08:00
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X(X01)
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X(N100)
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X(SN10)
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X(SN20)
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X(N130)
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X(S100)
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X(S130)
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X(E100)
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X(EW10)
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X(EW20)
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X(E130)
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X(W100)
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X(N200)
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X(N270)
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X(S200)
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X(E200)
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X(E220)
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X(E230)
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X(E240)
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X(E250)
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X(E260)
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X(E270)
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X(W200)
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X(W210)
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X(W240)
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X(W260)
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X(W270)
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X(N800)
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X(N810)
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X(N820)
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X(N830)
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X(S800)
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X(S810)
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X(S820)
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X(S830)
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X(E800)
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X(E810)
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X(E820)
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X(E830)
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X(W800)
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X(W810)
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X(W820)
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X(W830)
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X(CLK0)
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X(CLK1)
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X(CLK2)
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X(LSR0)
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X(LSR1)
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X(CE0)
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X(SEL0)
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X(SEL7)
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X(N101)
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X(N131)
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X(S101)
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X(S131)
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X(E101)
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X(E131)
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X(W101)
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X(W131)
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X(N201)
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X(N211)
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X(N221)
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X(N231)
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X(N241)
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X(N251)
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X(N261)
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X(N271)
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X(S201)
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X(S211)
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X(S221)
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X(S231)
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X(S241)
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X(S251)
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X(S271)
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X(E201)
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X(E211)
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X(E221)
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X(E231)
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X(E241)
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X(E251)
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X(E261)
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X(E271)
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X(W201)
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X(W211)
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X(W221)
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X(W231)
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X(W241)
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X(W251)
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X(W261)
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X(W271)
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X(N202)
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X(N212)
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X(N222)
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X(N232)
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X(N242)
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X(N252)
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X(N262)
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X(N272)
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X(S202)
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X(S212)
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X(S222)
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X(S232)
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X(S242)
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X(S252)
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X(S262)
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X(S272)
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X(E202)
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X(E212)
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X(E222)
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X(E232)
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X(E242)
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X(E252)
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X(E262)
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X(E272)
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X(W202)
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X(W212)
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X(W222)
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X(W232)
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X(W242)
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X(W252)
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X(W262)
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X(W272)
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X(N804)
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X(N814)
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X(N824)
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X(N834)
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X(S804)
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X(S814)
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X(S824)
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X(S834)
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X(E804)
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X(E814)
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X(E824)
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X(E834)
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X(W804)
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X(W814)
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X(W824)
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X(W834)
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X(N808)
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X(N818)
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X(N828)
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X(N838)
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X(S808)
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X(S818)
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X(S828)
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X(S838)
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X(E808)
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X(E818)
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X(E828)
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X(E838)
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X(W808)
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X(W818)
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X(W828)
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X(W838)
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X(E110)
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X(W110)
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X(E120)
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X(W120)
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X(S110)
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X(N110)
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X(S120)
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X(N120)
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X(E111)
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X(W111)
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X(E121)
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X(W121)
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X(S111)
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X(N111)
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X(S121)
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X(N121)
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X(LB01)
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X(LB11)
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X(LB21)
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X(LB31)
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X(LB41)
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X(LB51)
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X(LB61)
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X(LB71)
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X(GB00)
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X(GB10)
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X(GB20)
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X(GB30)
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X(GB40)
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X(GB50)
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X(GB60)
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X(GB70)
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X(VCC)
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X(VSS)
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X(LT00)
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X(LT10)
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X(LT20)
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X(LT30)
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X(LT02)
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X(LT13)
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X(LT01)
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X(LT04)
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X(LBO0)
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X(LBO1)
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X(SS00)
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X(SS40)
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X(GT00)
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X(GT10)
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X(GBO0)
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X(GBO1)
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X(DI0)
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X(DI1)
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X(DI2)
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X(DI3)
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X(DI4)
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X(DI5)
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X(DI6)
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X(DI7)
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X(CIN0)
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X(CIN1)
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X(CIN2)
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X(CIN3)
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X(CIN4)
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X(CIN5)
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X(COUT0)
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X(COUT1)
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X(COUT2)
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X(COUT3)
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X(COUT4)
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X(COUT5)
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X(VREN)
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// wires
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// SN
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X(S10)
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X(S10_loop0)
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X(S13)
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X(S13_loop0)
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X(N10)
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X(N10_loop0)
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X(N13)
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X(N13_loop0)
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X(SN10_loop_n)
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X(SN10_loop_s)
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X(SN20_loop_n)
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X(SN20_loop_s)
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X(S20)
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X(S20_loop0)
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X(S20_loop1)
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X(S21)
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X(S21_loop0)
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X(S21_loop1)
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X(S22)
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X(S22_loop0)
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X(S22_loop1)
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X(S23)
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X(S23_loop0)
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X(S23_loop1)
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X(S24)
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X(S24_loop0)
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X(S24_loop1)
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X(S25)
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X(S25_loop0)
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X(S25_loop1)
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X(S26)
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X(S26_loop0)
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X(S26_loop1)
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X(S27)
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X(S27_loop0)
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X(S27_loop1)
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X(N20)
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X(N20_loop0)
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X(N20_loop1)
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X(N21)
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X(N21_loop0)
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X(N21_loop1)
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X(N22)
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X(N22_loop0)
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X(N22_loop1)
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X(N23)
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X(N23_loop0)
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|
X(N23_loop1)
|
|
|
|
|
X(N24)
|
|
|
|
|
X(N24_loop0)
|
|
|
|
|
X(N24_loop1)
|
|
|
|
|
X(N25)
|
|
|
|
|
X(N25_loop0)
|
|
|
|
|
X(N25_loop1)
|
|
|
|
|
X(N26)
|
|
|
|
|
X(N26_loop0)
|
|
|
|
|
X(N26_loop1)
|
|
|
|
|
X(N27)
|
|
|
|
|
X(N27_loop0)
|
|
|
|
|
X(N27_loop1)
|
|
|
|
|
X(S80)
|
|
|
|
|
X(S80_loop0)
|
|
|
|
|
X(S80_loop1)
|
|
|
|
|
X(S80_loop2)
|
|
|
|
|
X(S80_loop3)
|
|
|
|
|
X(S80_loop4)
|
|
|
|
|
X(S80_loop5)
|
|
|
|
|
X(S80_loop6)
|
|
|
|
|
X(S80_loop7)
|
|
|
|
|
X(N80)
|
|
|
|
|
X(N80_loop0)
|
|
|
|
|
X(N80_loop1)
|
|
|
|
|
X(N80_loop2)
|
|
|
|
|
X(N80_loop3)
|
|
|
|
|
X(N80_loop4)
|
|
|
|
|
X(N80_loop5)
|
|
|
|
|
X(N80_loop6)
|
|
|
|
|
X(N80_loop7)
|
|
|
|
|
X(S81)
|
|
|
|
|
X(S81_loop0)
|
|
|
|
|
X(S81_loop1)
|
|
|
|
|
X(S81_loop2)
|
|
|
|
|
X(S81_loop3)
|
|
|
|
|
X(S81_loop4)
|
|
|
|
|
X(S81_loop5)
|
|
|
|
|
X(S81_loop6)
|
|
|
|
|
X(S81_loop7)
|
|
|
|
|
X(N81)
|
|
|
|
|
X(N81_loop0)
|
|
|
|
|
X(N81_loop1)
|
|
|
|
|
X(N81_loop2)
|
|
|
|
|
X(N81_loop3)
|
|
|
|
|
X(N81_loop4)
|
|
|
|
|
X(N81_loop5)
|
|
|
|
|
X(N81_loop6)
|
|
|
|
|
X(N81_loop7)
|
|
|
|
|
X(S82)
|
|
|
|
|
X(S82_loop0)
|
|
|
|
|
X(S82_loop1)
|
|
|
|
|
X(S82_loop2)
|
|
|
|
|
X(S82_loop3)
|
|
|
|
|
X(S82_loop4)
|
|
|
|
|
X(S82_loop5)
|
|
|
|
|
X(S82_loop6)
|
|
|
|
|
X(S82_loop7)
|
|
|
|
|
X(N82)
|
|
|
|
|
X(N82_loop0)
|
|
|
|
|
X(N82_loop1)
|
|
|
|
|
X(N82_loop2)
|
|
|
|
|
X(N82_loop3)
|
|
|
|
|
X(N82_loop4)
|
|
|
|
|
X(N82_loop5)
|
|
|
|
|
X(N82_loop6)
|
|
|
|
|
X(N82_loop7)
|
|
|
|
|
X(S83)
|
|
|
|
|
X(S83_loop0)
|
|
|
|
|
X(S83_loop1)
|
|
|
|
|
X(S83_loop2)
|
|
|
|
|
X(S83_loop3)
|
|
|
|
|
X(S83_loop4)
|
|
|
|
|
X(S83_loop5)
|
|
|
|
|
X(S83_loop6)
|
|
|
|
|
X(S83_loop7)
|
|
|
|
|
X(N83)
|
|
|
|
|
X(N83_loop0)
|
|
|
|
|
X(N83_loop1)
|
|
|
|
|
X(N83_loop2)
|
|
|
|
|
X(N83_loop3)
|
|
|
|
|
X(N83_loop4)
|
|
|
|
|
X(N83_loop5)
|
|
|
|
|
X(N83_loop6)
|
|
|
|
|
X(N83_loop7)
|
|
|
|
|
|
|
|
|
|
// WE
|
|
|
|
|
X(E10)
|
|
|
|
|
X(E10_loop0)
|
|
|
|
|
X(E13)
|
|
|
|
|
X(E13_loop0)
|
|
|
|
|
X(W10)
|
|
|
|
|
X(W10_loop0)
|
|
|
|
|
X(W13)
|
|
|
|
|
X(W13_loop0)
|
|
|
|
|
X(EW10_loop_w)
|
|
|
|
|
X(EW10_loop_e)
|
|
|
|
|
X(EW20_loop_w)
|
|
|
|
|
X(EW20_loop_e)
|
|
|
|
|
//
|
|
|
|
|
X(E20)
|
|
|
|
|
X(E20_loop0)
|
|
|
|
|
X(E20_loop1)
|
|
|
|
|
X(E21)
|
|
|
|
|
X(E21_loop0)
|
|
|
|
|
X(E21_loop1)
|
|
|
|
|
X(E22)
|
|
|
|
|
X(E22_loop0)
|
|
|
|
|
X(E22_loop1)
|
|
|
|
|
X(E23)
|
|
|
|
|
X(E23_loop0)
|
|
|
|
|
X(E23_loop1)
|
|
|
|
|
X(E24)
|
|
|
|
|
X(E24_loop0)
|
|
|
|
|
X(E24_loop1)
|
|
|
|
|
X(E25)
|
|
|
|
|
X(E25_loop0)
|
|
|
|
|
X(E25_loop1)
|
|
|
|
|
X(E26)
|
|
|
|
|
X(E26_loop0)
|
|
|
|
|
X(E26_loop1)
|
|
|
|
|
X(E27)
|
|
|
|
|
X(E27_loop0)
|
|
|
|
|
X(E27_loop1)
|
|
|
|
|
X(W20)
|
|
|
|
|
X(W20_loop0)
|
|
|
|
|
X(W20_loop1)
|
|
|
|
|
X(W21)
|
|
|
|
|
X(W21_loop0)
|
|
|
|
|
X(W21_loop1)
|
|
|
|
|
X(W22)
|
|
|
|
|
X(W22_loop0)
|
|
|
|
|
X(W22_loop1)
|
|
|
|
|
X(W23)
|
|
|
|
|
X(W23_loop0)
|
|
|
|
|
X(W23_loop1)
|
|
|
|
|
X(W24)
|
|
|
|
|
X(W24_loop0)
|
|
|
|
|
X(W24_loop1)
|
|
|
|
|
X(W25)
|
|
|
|
|
X(W25_loop0)
|
|
|
|
|
X(W25_loop1)
|
|
|
|
|
X(W26)
|
|
|
|
|
X(W26_loop0)
|
|
|
|
|
X(W26_loop1)
|
|
|
|
|
X(W27)
|
|
|
|
|
X(W27_loop0)
|
|
|
|
|
X(W27_loop1)
|
|
|
|
|
//
|
|
|
|
|
X(E80)
|
|
|
|
|
X(E80_loop0)
|
|
|
|
|
X(E80_loop1)
|
|
|
|
|
X(E80_loop2)
|
|
|
|
|
X(E80_loop3)
|
|
|
|
|
X(E80_loop4)
|
|
|
|
|
X(E80_loop5)
|
|
|
|
|
X(E80_loop6)
|
|
|
|
|
X(E80_loop7)
|
|
|
|
|
X(W80)
|
|
|
|
|
X(W80_loop0)
|
|
|
|
|
X(W80_loop1)
|
|
|
|
|
X(W80_loop2)
|
|
|
|
|
X(W80_loop3)
|
|
|
|
|
X(W80_loop4)
|
|
|
|
|
X(W80_loop5)
|
|
|
|
|
X(W80_loop6)
|
|
|
|
|
X(W80_loop7)
|
|
|
|
|
X(E81)
|
|
|
|
|
X(E81_loop0)
|
|
|
|
|
X(E81_loop1)
|
|
|
|
|
X(E81_loop2)
|
|
|
|
|
X(E81_loop3)
|
|
|
|
|
X(E81_loop4)
|
|
|
|
|
X(E81_loop5)
|
|
|
|
|
X(E81_loop6)
|
|
|
|
|
X(E81_loop7)
|
|
|
|
|
X(W81)
|
|
|
|
|
X(W81_loop0)
|
|
|
|
|
X(W81_loop1)
|
|
|
|
|
X(W81_loop2)
|
|
|
|
|
X(W81_loop3)
|
|
|
|
|
X(W81_loop4)
|
|
|
|
|
X(W81_loop5)
|
|
|
|
|
X(W81_loop6)
|
|
|
|
|
X(W81_loop7)
|
|
|
|
|
X(E82)
|
|
|
|
|
X(E82_loop0)
|
|
|
|
|
X(E82_loop1)
|
|
|
|
|
X(E82_loop2)
|
|
|
|
|
X(E82_loop3)
|
|
|
|
|
X(E82_loop4)
|
|
|
|
|
X(E82_loop5)
|
|
|
|
|
X(E82_loop6)
|
|
|
|
|
X(E82_loop7)
|
|
|
|
|
X(W82)
|
|
|
|
|
X(W82_loop0)
|
|
|
|
|
X(W82_loop1)
|
|
|
|
|
X(W82_loop2)
|
|
|
|
|
X(W82_loop3)
|
|
|
|
|
X(W82_loop4)
|
|
|
|
|
X(W82_loop5)
|
|
|
|
|
X(W82_loop6)
|
|
|
|
|
X(W82_loop7)
|
|
|
|
|
X(E83)
|
|
|
|
|
X(E83_loop0)
|
|
|
|
|
X(E83_loop1)
|
|
|
|
|
X(E83_loop2)
|
|
|
|
|
X(E83_loop3)
|
|
|
|
|
X(E83_loop4)
|
|
|
|
|
X(E83_loop5)
|
|
|
|
|
X(E83_loop6)
|
|
|
|
|
X(E83_loop7)
|
|
|
|
|
X(W83)
|
|
|
|
|
X(W83_loop0)
|
|
|
|
|
X(W83_loop1)
|
|
|
|
|
X(W83_loop2)
|
|
|
|
|
X(W83_loop3)
|
|
|
|
|
X(W83_loop4)
|
|
|
|
|
X(W83_loop5)
|
|
|
|
|
X(W83_loop6)
|
|
|
|
|
X(W83_loop7)
|
|
|
|
|
|
|
|
|
|
// spines
|
|
|
|
|
X(SPINE0)
|
|
|
|
|
X(SPINE1)
|
|
|
|
|
X(SPINE2)
|
|
|
|
|
X(SPINE3)
|
|
|
|
|
X(SPINE4)
|
|
|
|
|
X(SPINE5)
|
|
|
|
|
X(SPINE6)
|
|
|
|
|
X(SPINE7)
|
|
|
|
|
X(SPINE8)
|
|
|
|
|
X(SPINE9)
|
|
|
|
|
X(SPINE10)
|
|
|
|
|
X(SPINE11)
|
|
|
|
|
X(SPINE12)
|
|
|
|
|
X(SPINE13)
|
|
|
|
|
X(SPINE14)
|
|
|
|
|
X(SPINE15)
|
|
|
|
|
X(SPINE16)
|
|
|
|
|
X(SPINE17)
|
|
|
|
|
X(SPINE18)
|
|
|
|
|
X(SPINE19)
|
|
|
|
|
X(SPINE20)
|
|
|
|
|
X(SPINE21)
|
|
|
|
|
X(SPINE22)
|
|
|
|
|
X(SPINE23)
|
|
|
|
|
X(SPINE24)
|
|
|
|
|
X(SPINE25)
|
|
|
|
|
X(SPINE26)
|
|
|
|
|
X(SPINE27)
|
|
|
|
|
X(SPINE28)
|
|
|
|
|
X(SPINE29)
|
|
|
|
|
X(SPINE30)
|
|
|
|
|
X(SPINE31)
|
|
|
|
|
|
|
|
|
|
// slice items
|
|
|
|
|
X(SLICE)
|
|
|
|
|
X(CLK)
|
|
|
|
|
X(LSR)
|
|
|
|
|
X(CE)
|
|
|
|
|
X(Q)
|
|
|
|
|
X(F)
|
|
|
|
|
X(A)
|
|
|
|
|
X(B)
|
|
|
|
|
X(C)
|
|
|
|
|
X(D)
|
|
|
|
|
// iob items
|
|
|
|
|
X(IOB)
|
|
|
|
|
X(I)
|
|
|
|
|
X(O)
|
|
|
|
|
X(IO)
|
|
|
|
|
X(OE)
|
|
|
|
|
X(OB)
|
|
|
|
|
X(IB)
|
|
|
|
|
|
|
|
|
|
// bels
|
|
|
|
|
X(DFF0)
|
|
|
|
|
X(DFF1)
|
|
|
|
|
X(DFF2)
|
|
|
|
|
X(DFF3)
|
|
|
|
|
X(DFF4)
|
|
|
|
|
X(DFF5)
|
|
|
|
|
|
|
|
|
|
X(LUT0)
|
|
|
|
|
X(LUT1)
|
|
|
|
|
X(LUT2)
|
|
|
|
|
X(LUT3)
|
|
|
|
|
X(LUT4)
|
|
|
|
|
X(LUT5)
|
|
|
|
|
X(LUT6)
|
|
|
|
|
X(LUT7)
|
|
|
|
|
|
|
|
|
|
X(IOBA)
|
|
|
|
|
X(IOBB)
|
|
|
|
|
X(IOBC)
|
|
|
|
|
X(IOBD)
|
|
|
|
|
X(IOBE)
|
|
|
|
|
X(IOBF)
|
|
|
|
|
X(IOBG)
|
|
|
|
|
X(IOBH)
|
|
|
|
|
X(IOBI)
|
|
|
|
|
X(IOBJ)
|
|
|
|
|
|
|
|
|
|
// misc
|
|
|
|
|
X(DUMMY_CELL)
|
|
|
|
|
|
|
|
|
|
// simplified iobs
|
|
|
|
|
X(IOBS)
|
|
|
|
|
X(IOBAS)
|
|
|
|
|
X(IOBBS)
|
|
|
|
|
X(IOBCS)
|
|
|
|
|
X(IOBDS)
|
|
|
|
|
X(IOBES)
|
|
|
|
|
X(IOBFS)
|
|
|
|
|
X(IOBGS)
|
|
|
|
|
X(IOBHS)
|
|
|
|
|
X(IOBIS)
|
|
|
|
|
X(IOBJS)
|
|
|
|
|
|
|
|
|
|
// long wires
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(LONGWIRE)
|
2023-06-28 08:16:29 +08:00
|
|
|
X(BUFS)
|
|
|
|
|
X(BUFS0)
|
|
|
|
|
X(BUFS1)
|
|
|
|
|
X(BUFS2)
|
|
|
|
|
X(BUFS3)
|
|
|
|
|
X(BUFS4)
|
|
|
|
|
X(BUFS5)
|
|
|
|
|
X(BUFS6)
|
|
|
|
|
X(BUFS7)
|
|
|
|
|
X(LWT0)
|
|
|
|
|
X(LWB0)
|
|
|
|
|
X(LWT1)
|
|
|
|
|
X(LWB1)
|
|
|
|
|
X(LWT2)
|
|
|
|
|
X(LWB2)
|
|
|
|
|
X(LWT3)
|
|
|
|
|
X(LWB3)
|
|
|
|
|
X(LWT4)
|
|
|
|
|
X(LWB4)
|
|
|
|
|
X(LWT5)
|
|
|
|
|
X(LWB5)
|
|
|
|
|
X(LWT6)
|
|
|
|
|
X(LWB6)
|
|
|
|
|
X(LWT7)
|
|
|
|
|
X(LWB7)
|
|
|
|
|
X(LWSPINETL0)
|
|
|
|
|
X(LWSPINETL1)
|
|
|
|
|
X(LWSPINETL2)
|
|
|
|
|
X(LWSPINETL3)
|
|
|
|
|
X(LWSPINETL4)
|
|
|
|
|
X(LWSPINETL5)
|
|
|
|
|
X(LWSPINETL6)
|
|
|
|
|
X(LWSPINETL7)
|
|
|
|
|
X(LWSPINETR0)
|
|
|
|
|
X(LWSPINETR1)
|
|
|
|
|
X(LWSPINETR2)
|
|
|
|
|
X(LWSPINETR3)
|
|
|
|
|
X(LWSPINETR4)
|
|
|
|
|
X(LWSPINETR5)
|
|
|
|
|
X(LWSPINETR6)
|
|
|
|
|
X(LWSPINETR7)
|
|
|
|
|
X(LWSPINEBL0)
|
|
|
|
|
X(LWSPINEBL1)
|
|
|
|
|
X(LWSPINEBL2)
|
|
|
|
|
X(LWSPINEBL3)
|
|
|
|
|
X(LWSPINEBL4)
|
|
|
|
|
X(LWSPINEBL5)
|
|
|
|
|
X(LWSPINEBL6)
|
|
|
|
|
X(LWSPINEBL7)
|
|
|
|
|
X(LWSPINEBR0)
|
|
|
|
|
X(LWSPINEBR1)
|
|
|
|
|
X(LWSPINEBR2)
|
|
|
|
|
X(LWSPINEBR3)
|
|
|
|
|
X(LWSPINEBR4)
|
|
|
|
|
X(LWSPINEBR5)
|
|
|
|
|
X(LWSPINEBR6)
|
|
|
|
|
X(LWSPINEBR7)
|
|
|
|
|
X(LWI0)
|
|
|
|
|
X(LWI1)
|
|
|
|
|
X(LWI2)
|
|
|
|
|
X(LWI3)
|
|
|
|
|
X(LWI4)
|
|
|
|
|
X(LWI5)
|
|
|
|
|
X(LWI6)
|
|
|
|
|
X(LWI7)
|
|
|
|
|
X(LWO0)
|
|
|
|
|
X(LWO1)
|
|
|
|
|
X(LWO2)
|
|
|
|
|
X(LWO3)
|
|
|
|
|
X(LWO4)
|
|
|
|
|
X(LWO5)
|
|
|
|
|
X(LWO6)
|
|
|
|
|
X(LWO7)
|
|
|
|
|
|
|
|
|
|
// IOLOGIC
|
|
|
|
|
X(TX)
|
|
|
|
|
X(TX0)
|
|
|
|
|
X(TX1)
|
|
|
|
|
X(TX2)
|
|
|
|
|
X(TX3)
|
|
|
|
|
X(FCLK)
|
|
|
|
|
X(PCLK)
|
|
|
|
|
X(CALIB)
|
|
|
|
|
X(DAADJ0)
|
|
|
|
|
X(DAADJ1)
|
|
|
|
|
X(GW9_ALWAYS_LOW0)
|
|
|
|
|
X(GW9_ALWAYS_LOW1)
|
|
|
|
|
X(GW9C_ALWAYS_LOW0)
|
|
|
|
|
X(GW9C_ALWAYS_LOW1)
|
|
|
|
|
X(OBUF_TYPE)
|
|
|
|
|
X(IBUF_TYPE)
|
|
|
|
|
X(SBUF)
|
|
|
|
|
X(DBUF)
|
|
|
|
|
X(ODDR)
|
|
|
|
|
X(IDDR)
|
|
|
|
|
X(ODDRC)
|
|
|
|
|
X(IDDRC)
|
|
|
|
|
X(ODDRA)
|
|
|
|
|
X(ODDRB)
|
|
|
|
|
X(ODDRCA)
|
|
|
|
|
X(ODDRCB)
|
|
|
|
|
X(OSER4)
|
|
|
|
|
X(OSER8)
|
|
|
|
|
X(OSER10)
|
|
|
|
|
X(OVIDEO)
|
|
|
|
|
X(OSER16)
|
|
|
|
|
X(IDES4)
|
|
|
|
|
X(IDES8)
|
|
|
|
|
X(IDES10)
|
|
|
|
|
X(IVIDEO)
|
|
|
|
|
X(IDES16)
|
2024-02-10 12:16:52 +08:00
|
|
|
X(IOLOGIC)
|
2024-02-09 15:44:57 +08:00
|
|
|
X(IOLOGICI)
|
|
|
|
|
X(IOLOGICO)
|
2023-06-28 08:16:29 +08:00
|
|
|
X(IOLOGICA)
|
|
|
|
|
X(IOLOGICB)
|
|
|
|
|
X(IOLOGIC_TYPE)
|
|
|
|
|
X(IOLOGIC_FCLK)
|
|
|
|
|
X(IOLOGIC_MASTER_CELL)
|
|
|
|
|
X(IOLOGIC_AUX_CELL)
|
|
|
|
|
X(D8)
|
|
|
|
|
X(D9)
|
|
|
|
|
X(D10)
|
|
|
|
|
X(D11)
|
|
|
|
|
X(D12)
|
|
|
|
|
X(D13)
|
|
|
|
|
X(D14)
|
|
|
|
|
X(D15)
|
|
|
|
|
X(Q8)
|
|
|
|
|
X(Q9)
|
|
|
|
|
X(Q10)
|
|
|
|
|
X(Q11)
|
|
|
|
|
X(Q12)
|
|
|
|
|
X(Q13)
|
|
|
|
|
X(Q14)
|
|
|
|
|
X(Q15)
|
|
|
|
|
|
|
|
|
|
// Wide LUTs
|
|
|
|
|
X(MUX2_LUT5)
|
|
|
|
|
X(MUX2_LUT6)
|
|
|
|
|
X(MUX2_LUT7)
|
|
|
|
|
X(MUX2_LUT8)
|
|
|
|
|
X(I0MUX0)
|
|
|
|
|
X(I1MUX0)
|
|
|
|
|
X(I0MUX1)
|
|
|
|
|
X(I1MUX1)
|
|
|
|
|
X(I0MUX2)
|
|
|
|
|
X(I1MUX2)
|
|
|
|
|
X(I0MUX3)
|
|
|
|
|
X(I1MUX3)
|
|
|
|
|
X(I0MUX4)
|
|
|
|
|
X(I1MUX4)
|
|
|
|
|
X(I0MUX5)
|
|
|
|
|
X(I1MUX5)
|
|
|
|
|
X(I0MUX6)
|
|
|
|
|
X(I1MUX6)
|
|
|
|
|
X(I0MUX7)
|
|
|
|
|
X(I1MUX7)
|
|
|
|
|
|
|
|
|
|
// ALU
|
|
|
|
|
X(ALU)
|
|
|
|
|
X(GND)
|
|
|
|
|
X(ALU_MODE)
|
|
|
|
|
|
|
|
|
|
// DFF types
|
|
|
|
|
X(DFF)
|
|
|
|
|
X(DFFE)
|
|
|
|
|
X(DFFS)
|
|
|
|
|
X(DFFSE)
|
|
|
|
|
X(DFFR)
|
|
|
|
|
X(DFFRE)
|
|
|
|
|
X(DFFP)
|
|
|
|
|
X(DFFPE)
|
|
|
|
|
X(DFFC)
|
|
|
|
|
X(DFFCE)
|
|
|
|
|
X(DFFN)
|
|
|
|
|
X(DFFNE)
|
|
|
|
|
X(DFFNS)
|
|
|
|
|
X(DFFNSE)
|
|
|
|
|
X(DFFNR)
|
|
|
|
|
X(DFFNRE)
|
|
|
|
|
X(DFFNP)
|
|
|
|
|
X(DFFNPE)
|
|
|
|
|
X(DFFNC)
|
|
|
|
|
X(DFFNCE)
|
|
|
|
|
|
|
|
|
|
// Shadow RAM
|
|
|
|
|
X(RAM16)
|
|
|
|
|
X(RAMW)
|
|
|
|
|
X(RAM16SDP4)
|
2023-07-06 12:48:44 +08:00
|
|
|
X(RAM16SDP2)
|
|
|
|
|
X(RAM16SDP1)
|
2023-06-28 08:16:29 +08:00
|
|
|
X(WADA)
|
|
|
|
|
X(WADB)
|
|
|
|
|
X(WADC)
|
|
|
|
|
X(WADD)
|
|
|
|
|
X(DIA)
|
|
|
|
|
X(DIB)
|
|
|
|
|
X(DIC)
|
|
|
|
|
X(DID)
|
|
|
|
|
X(WRE)
|
|
|
|
|
|
2023-10-03 19:11:40 +08:00
|
|
|
// BSRAM
|
|
|
|
|
X(BSRAM_SUBTYPE)
|
|
|
|
|
X(BIT_WIDTH)
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(BIT_WIDTH_0)
|
|
|
|
|
X(BIT_WIDTH_1)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(ROM)
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(DP)
|
|
|
|
|
X(DPB)
|
|
|
|
|
X(DPX9B)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(SP)
|
|
|
|
|
X(SPX9)
|
gowin: Himbaechel. Add GW1NZ-1 BSRAM.
The following primitives are implemented for the GW1NZ-1 chip:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
Also:
- The creation of databases for GW1NS-2 has been removed - this was not
planned to be supported in Himbaechel from the very beginning and
even examples were not created in apicula for this chip due to the
lack of boards with it on sale.
- It is temporarily prohibited to connect DFFs and LUTs into clusters
because for some reason this prevents the creation of images on lower
chips (placer cannot find the placement), although without these
clusters the images are quite working. Requires further research.
- Added creation of ALU with mode 0 - addition. Such an element is not
generated by Yosys, but it is a favorite vendor element and its
support here greatly simplifies the compilation of vendor netlists.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-20 10:27:56 +08:00
|
|
|
X(SDP)
|
|
|
|
|
X(SDPB)
|
|
|
|
|
X(SDPX9B)
|
2023-10-03 19:11:40 +08:00
|
|
|
X(pROM)
|
|
|
|
|
X(pROMX9)
|
|
|
|
|
X(BSRAM)
|
|
|
|
|
X(OCE)
|
|
|
|
|
X(OCEA)
|
|
|
|
|
X(OCEB)
|
|
|
|
|
X(CEA)
|
|
|
|
|
X(CEB)
|
|
|
|
|
X(RESETA)
|
|
|
|
|
X(RESETB)
|
|
|
|
|
X(WREA)
|
|
|
|
|
X(WREB)
|
|
|
|
|
X(CLKA)
|
|
|
|
|
X(CLKB)
|
|
|
|
|
|
2024-03-18 20:08:52 +08:00
|
|
|
// DSP
|
|
|
|
|
X(ALU54D)
|
|
|
|
|
X(MULTADDALU18X18)
|
|
|
|
|
X(MULTALU18X18)
|
|
|
|
|
X(MULTALU36X18)
|
|
|
|
|
X(MULT36X36)
|
|
|
|
|
X(MULT18X18)
|
|
|
|
|
X(MULT9X9)
|
|
|
|
|
X(PADD18)
|
|
|
|
|
X(PADD9)
|
|
|
|
|
X(ASIGN)
|
|
|
|
|
X(BSIGN)
|
|
|
|
|
X(ASIGN0)
|
|
|
|
|
X(BSIGN0)
|
|
|
|
|
X(ASIGN1)
|
|
|
|
|
X(BSIGN1)
|
|
|
|
|
X(ASEL)
|
|
|
|
|
X(ASEL0)
|
|
|
|
|
X(ASEL1)
|
|
|
|
|
X(BSEL)
|
|
|
|
|
X(BSEL0)
|
|
|
|
|
X(BSEL1)
|
|
|
|
|
X(SOA_REG)
|
|
|
|
|
X(DSIGN)
|
|
|
|
|
X(ACCLOAD)
|
|
|
|
|
X(ACCLOAD0)
|
|
|
|
|
X(ACCLOAD1)
|
|
|
|
|
X(NET_ACCLOAD)
|
|
|
|
|
X(ALUSEL0)
|
|
|
|
|
X(ALUSEL1)
|
|
|
|
|
X(ALUSEL2)
|
|
|
|
|
X(ALUSEL3)
|
|
|
|
|
X(ALUSEL4)
|
|
|
|
|
X(ALUSEL5)
|
|
|
|
|
X(ALUSEL6)
|
|
|
|
|
X(USE_CASCADE_OUT)
|
|
|
|
|
X(USE_CASCADE_IN)
|
|
|
|
|
X(LAST_IN_CHAIN)
|
|
|
|
|
X(MULTALU18X18_MODE)
|
|
|
|
|
X(MULTADDALU18X18_MODE)
|
|
|
|
|
X(MULTALU36X18_MODE)
|
|
|
|
|
|
2023-06-28 08:16:29 +08:00
|
|
|
// IOB types
|
|
|
|
|
X(IBUF)
|
|
|
|
|
X(OBUF)
|
|
|
|
|
X(IOBUF)
|
|
|
|
|
X(TBUF)
|
|
|
|
|
X(TLVDS_OBUF)
|
|
|
|
|
X(TLVDS_TBUF)
|
|
|
|
|
X(TLVDS_IBUF)
|
|
|
|
|
X(TLVDS_IOBUF)
|
|
|
|
|
X(ELVDS_OBUF)
|
|
|
|
|
X(ELVDS_TBUF)
|
|
|
|
|
X(ELVDS_IBUF)
|
|
|
|
|
X(ELVDS_IOBUF)
|
|
|
|
|
|
|
|
|
|
// global set/reset
|
|
|
|
|
X(GSR)
|
|
|
|
|
X(GSR0)
|
|
|
|
|
X(GSRI)
|
|
|
|
|
|
2024-01-23 12:50:36 +08:00
|
|
|
// inverter
|
|
|
|
|
X(INV)
|
|
|
|
|
|
2023-06-28 08:16:29 +08:00
|
|
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// Oscillators
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X(OSC)
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X(OSCZ)
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X(OSCH)
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X(OSCF)
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X(OSCW)
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X(OSCO)
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// PLLs
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X(rPLL)
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X(RPLLA)
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X(PLLVR)
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// primitive attributes
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X(INIT)
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X(FF_USED)
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X(FF_TYPE)
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X(INPUT_USED)
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X(OUTPUT_USED)
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X(ENABLE_USED)
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X(BEL)
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X(DIFF)
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X(DIFF_TYPE)
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X(DEVICE)
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X(IOLOGIC_IOB)
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// ports
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X(EN)
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X(E)
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X(Y)
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X(PAD)
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X(RESET)
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X(SET)
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X(PRESET)
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X(CLEAR)
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X(I0)
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X(I1)
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X(I2)
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X(I3)
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X(OEN)
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X(S0)
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X(SEL)
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X(SUM)
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X(CIN)
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X(COUT)
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X(OF)
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X(V)
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X(G)
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X(OSCOUT)
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X(OSCEN)
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X(RESET_P)
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X(CLKFB)
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X(FBDSEL0)
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X(FBDSEL1)
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X(FBDSEL2)
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X(FBDSEL3)
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X(FBDSEL4)
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X(FBDSEL5)
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X(IDSEL0)
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X(IDSEL1)
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X(IDSEL2)
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X(IDSEL3)
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X(IDSEL4)
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X(IDSEL5)
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X(ODSEL0)
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X(ODSEL1)
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X(ODSEL2)
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X(ODSEL3)
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X(ODSEL4)
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X(ODSEL5)
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X(PSDA0)
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X(PSDA1)
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X(PSDA2)
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X(PSDA3)
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X(DUTYDA0)
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X(DUTYDA1)
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X(DUTYDA2)
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X(DUTYDA3)
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X(FDLY0)
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X(FDLY1)
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X(FDLY2)
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X(FDLY3)
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X(CLKIN)
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X(CLKOUT)
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X(CLKOUTP)
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X(CLKOUTD)
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X(CLKOUTD3)
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X(LOCK)
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gowin: Himbaechel. Add BSRAM for all chips.
The following primitives are implemented for the GW1N-1, GW2A-18,
GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
of 32/36 bits are implemented using a pair of 16-bit wide
primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-26 18:51:16 +08:00
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X(AD)
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X(DI)
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X(DO)
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2023-06-28 08:16:29 +08:00
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// PLL parameters
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X(CLKOUTPS)
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X(CLKOUTDIV)
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X(CLKOUTDIV3)
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X(PWDEN)
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X(RSTEN)
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X(FLOCK)
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X(INSEL)
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X(FBSEL)
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X(CLKFB_SEL)
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// timing
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X(X0)
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X(FX1)
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X(X2)
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X(X8)
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X(PIO_CENT_PCLK)
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X(CENT_SPINE_PCLK)
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X(SPINE_TAP_PCLK)
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X(TAP_BRANCH_PCLK)
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X(BRANCH_PCLK)
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X(CENT_SPINE_SCLK)
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X(SPINE_TAP_SCLK_0)
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X(SPINE_TAP_SCLK_1)
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X(TAP_BRANCH_SCLK)
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X(BRANCH_SCLK)
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X(clksetpos)
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X(clkholdpos)
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X(clk_qpos)
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X(a_f)
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X(b_f)
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X(c_f)
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X(d_f)
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X(fx_ofx1)
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X(I01)
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// GUI
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X(DECAL_LUT_ACTIVE)
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X(DECAL_LUT_INACTIVE)
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X(DECAL_LUTDFF_ACTIVE)
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X(DECAL_LUTDFF_INACTIVE)
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X(DECAL_LUT_UNUSED_DFF_ACTIVE)
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X(DECAL_GRP_LUT)
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X(DECAL_CRU)
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X(DECAL_MUXUPPER_INACTIVE)
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X(DECAL_MUXUPPER_ACTIVE)
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X(DECAL_MUXLOWER_INACTIVE)
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X(DECAL_MUXLOWER_ACTIVE)
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X(DECAL_IOB_INACTIVE)
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X(DECAL_IOB_ACTIVE)
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X(DECAL_IOBS_INACTIVE)
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X(DECAL_IOBS_ACTIVE)
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X(DECAL_ALU_ACTIVE)
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X(SINGLE_INPUT_MUX)
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X(cst)
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X(none)
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X(pack)
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X(place)
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X(placer)
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X(route)
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X(router)
|
2023-06-29 04:50:16 +08:00
|
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|
|
2023-06-30 15:18:14 +08:00
|
|
|
// misc
|
|
|
|
|
X(GOWIN_GND)
|
|
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|
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X(GOWIN_VCC)
|
2023-07-22 08:01:35 +08:00
|
|
|
X(PLL)
|
2023-07-23 14:46:04 +08:00
|
|
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X(BOTTOM_IO_PORT_A)
|
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X(BOTTOM_IO_PORT_B)
|
2023-08-07 16:20:08 +08:00
|
|
|
X(IOLOGIC_DUMMY)
|
2023-06-30 15:18:14 +08:00
|
|
|
|
2023-10-03 19:11:40 +08:00
|
|
|
//
|
|
|
|
|
|
2023-07-12 09:25:28 +08:00
|
|
|
// wire types
|
|
|
|
|
X(GLOBAL_CLK)
|
|
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|
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X(TILE_CLK)
|
|
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|
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X(TILE_LSR)
|
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|
|
X(TILE_CE)
|
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|
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X(IO_I)
|
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|
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X(IO_O)
|
|
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|
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X(LUT_INPUT)
|
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|
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X(LUT_OUT)
|
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X(FF_INPUT)
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X(FF_OUT)
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X(MUX_OUT)
|
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X(MUX_SEL)
|
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X(ALU_CIN)
|
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X(ALU_COUT)
|
2023-07-22 08:01:35 +08:00
|
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X(PLL_O)
|
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X(PLL_I)
|
2023-07-12 09:25:28 +08:00
|
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|
2023-07-19 11:29:18 +08:00
|
|
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// fake dff inputs
|
|
|
|
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X(XD0)
|
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X(XD1)
|
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X(XD2)
|
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X(XD3)
|
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X(XD4)
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X(XD5)
|
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|
2023-08-06 18:56:08 +08:00
|
|
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// HCLK wires
|
2023-08-08 08:57:45 +08:00
|
|
|
X(HCLK)
|
2023-08-06 18:56:08 +08:00
|
|
|
X(HCLK_OUT0)
|
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|
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X(HCLK_OUT1)
|
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|
X(HCLK_OUT2)
|
|
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X(HCLK_OUT3)
|
|
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|
|
2023-09-04 20:20:08 +08:00
|
|
|
// BUFG, clock buffers stuff
|
|
|
|
|
X(BUFG)
|
|
|
|
|
X(CLOCK)
|
|
|
|
|
|
gowin: Himbaechel. Add BSRAM for all chips.
The following primitives are implemented for the GW1N-1, GW2A-18,
GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
of 32/36 bits are implemented using a pair of 16-bit wide
primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-11-26 18:51:16 +08:00
|
|
|
|