2018-06-20 17:44:28 +08:00
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "timing.h"
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2018-06-20 17:53:49 +08:00
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#include <algorithm>
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2018-06-20 17:44:28 +08:00
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#include <unordered_map>
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#include <utility>
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2018-06-20 17:53:49 +08:00
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#include "log.h"
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2018-07-21 16:55:20 +08:00
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#include "util.h"
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2018-06-20 17:44:28 +08:00
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2018-06-20 17:53:49 +08:00
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NEXTPNR_NAMESPACE_BEGIN
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2018-08-04 13:39:25 +08:00
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typedef std::vector<const PortRef*> PortRefVector;
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2018-08-04 14:39:42 +08:00
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typedef std::map<delay_t, unsigned> DelayFrequency;
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2018-07-25 00:20:07 +08:00
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2018-08-04 13:39:25 +08:00
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struct Timing
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2018-06-20 17:44:28 +08:00
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{
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2018-08-04 13:39:25 +08:00
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Context *ctx;
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bool update;
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delay_t min_slack;
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PortRefVector current_path;
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PortRefVector *crit_path;
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2018-08-04 14:39:42 +08:00
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DelayFrequency *slack_histogram;
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2018-08-04 13:39:25 +08:00
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2018-08-04 14:39:42 +08:00
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Timing(Context *ctx, bool update, PortRefVector *crit_path = nullptr, DelayFrequency *slack_histogram = nullptr)
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: ctx(ctx), update(update), min_slack(1.0e12 / ctx->target_freq), crit_path(crit_path), slack_histogram(slack_histogram) {}
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2018-08-04 13:39:25 +08:00
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delay_t follow_net(NetInfo *net, int path_length, delay_t slack)
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{
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delay_t net_budget = slack / (path_length + 1);
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for (auto &usr : net->users) {
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if (crit_path)
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current_path.push_back(&usr);
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// If budget override is less than existing budget, then do not increment path length
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int pl = path_length + 1;
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auto budget = ctx->getBudgetOverride(net, usr, net_budget);
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if (budget < net_budget) {
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net_budget = budget;
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pl = std::max(1, path_length);
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}
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auto delay = ctx->getNetinfoRouteDelay(net, usr);
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net_budget = std::min(
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net_budget, follow_user_port(usr, pl, slack - delay));
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if (update)
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usr.budget = std::min(usr.budget, delay + net_budget);
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2018-07-26 13:32:07 +08:00
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if (crit_path)
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2018-08-04 13:39:25 +08:00
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current_path.pop_back();
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2018-07-26 13:10:26 +08:00
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}
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2018-08-04 13:39:25 +08:00
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return net_budget;
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}
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// Follow a path, returning budget to annotate
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delay_t follow_user_port(PortRef &user, int path_length, delay_t slack)
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{
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delay_t value;
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if (ctx->getPortClock(user.cell, user.port) != IdString()) {
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// At the end of a timing path (arguably, should check setup time
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// here too)
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value = slack / path_length;
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if (slack < min_slack) {
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min_slack = slack;
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if (crit_path)
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*crit_path = current_path;
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}
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2018-08-04 14:39:42 +08:00
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if (slack_histogram)
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(*slack_histogram)[slack]++;
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2018-08-04 13:39:25 +08:00
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} else {
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// Default to the path ending here, if no further paths found
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value = slack / path_length;
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// Follow outputs of the user
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for (auto port : user.cell->ports) {
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if (port.second.type == PORT_OUT) {
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DelayInfo comb_delay;
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// Look up delay through this path
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bool is_path = ctx->getCellDelay(user.cell, user.port, port.first, comb_delay);
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if (is_path) {
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NetInfo *net = port.second.net;
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if (net) {
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delay_t path_budget = follow_net(net, path_length, slack - comb_delay.maxDelay());
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value = std::min(value, path_budget);
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}
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2018-06-20 18:21:56 +08:00
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}
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}
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}
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}
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2018-08-04 13:39:25 +08:00
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return value;
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2018-06-20 18:21:56 +08:00
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}
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2018-08-04 13:39:25 +08:00
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delay_t walk_paths()
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{
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delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
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// Go through all clocked drivers and distribute the available path
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// slack evenly into the budget of every sink on the path
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for (auto &cell : ctx->cells) {
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for (auto port : cell.second->ports) {
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if (port.second.type == PORT_OUT) {
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IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first);
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if (clock_domain != IdString()) {
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delay_t slack = default_slack; // TODO: clock constraints
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DelayInfo clkToQ;
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if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ))
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slack -= clkToQ.maxDelay();
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if (port.second.net)
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follow_net(port.second.net, 0, slack);
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}
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}
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}
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2018-07-27 13:32:24 +08:00
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}
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2018-08-04 13:39:25 +08:00
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return min_slack;
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2018-06-20 17:53:49 +08:00
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}
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2018-06-20 17:44:28 +08:00
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2018-08-04 13:39:25 +08:00
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void assign_budget()
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{
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// Clear delays to a very high value first
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delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
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for (auto &net : ctx->nets) {
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for (auto &usr : net.second->users) {
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usr.budget = default_slack;
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2018-06-20 18:21:56 +08:00
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}
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}
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2018-06-20 23:08:57 +08:00
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2018-08-04 13:39:25 +08:00
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walk_paths();
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}
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};
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2018-07-26 09:21:39 +08:00
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2018-07-29 05:10:48 +08:00
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void assign_budget(Context *ctx, bool quiet)
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2018-07-26 09:21:39 +08:00
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{
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2018-07-29 05:10:48 +08:00
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if (!quiet) {
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log_break();
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log_info("Annotating ports with timing budgets\n");
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}
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2018-08-04 13:39:25 +08:00
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Timing timing(ctx, true /* update */);
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timing.assign_budget();
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2018-07-26 09:21:39 +08:00
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2018-07-29 05:10:48 +08:00
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if (!quiet || ctx->verbose) {
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2018-07-29 03:50:21 +08:00
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for (auto &net : ctx->nets) {
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for (auto &user : net.second->users) {
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// Post-update check
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2018-07-25 14:34:59 +08:00
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if (ctx->user_freq && user.budget < 0)
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2018-07-22 03:47:09 +08:00
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log_warning("port %s.%s, connected to net '%s', has negative "
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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ctx->getDelayNS(user.budget));
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2018-07-29 05:10:48 +08:00
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else if (ctx->verbose)
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2018-07-22 03:47:09 +08:00
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log_info("port %s.%s, connected to net '%s', has "
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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ctx->getDelayNS(user.budget));
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}
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2018-07-21 16:55:20 +08:00
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}
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}
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2018-07-27 12:35:37 +08:00
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2018-08-01 10:07:39 +08:00
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// For slack redistribution, if user has not specified a frequency
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// dynamically adjust the target frequency to be the currently
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// achieved maximum
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if (!ctx->user_freq && ctx->slack_redist_iter > 0) {
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2018-08-04 13:39:25 +08:00
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delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
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ctx->target_freq = 1e12 / (default_slack - timing.min_slack);
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if (ctx->verbose)
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log_info("minimum slack for this assign = %d, target Fmax for next update = %.2f MHz\n", timing.min_slack,
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ctx->target_freq / 1e6);
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2018-07-27 12:35:37 +08:00
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}
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2018-07-29 05:10:48 +08:00
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if (!quiet)
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log_info("Checksum: 0x%08x\n", ctx->checksum());
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2018-07-21 16:55:20 +08:00
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}
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2018-08-04 14:39:42 +08:00
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void timing_analysis(Context *ctx, bool print_histogram, bool print_path)
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2018-07-26 09:21:39 +08:00
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{
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2018-08-04 13:39:25 +08:00
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PortRefVector crit_path;
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2018-08-04 14:39:42 +08:00
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DelayFrequency slack_histogram;
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2018-08-04 13:39:25 +08:00
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2018-08-04 14:39:42 +08:00
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Timing timing(ctx, false /* update */, print_path ? &crit_path : nullptr, print_histogram ? &slack_histogram : nullptr);
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2018-08-04 13:39:25 +08:00
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auto min_slack = timing.walk_paths();
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2018-07-26 13:10:26 +08:00
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if (print_path) {
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2018-08-01 17:23:11 +08:00
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if (crit_path.empty()) {
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log_info("Design contains no timing paths\n");
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} else {
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delay_t total = 0;
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log_break();
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log_info("Critical path report:\n");
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log_info("curr total\n");
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
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for (auto sink : crit_path) {
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auto sink_cell = sink->cell;
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auto &port = sink_cell->ports.at(sink->port);
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auto net = port.net;
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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DelayInfo comb_delay;
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ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
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total += comb_delay.maxDelay();
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log_info("%4d %4d Source %s.%s\n", comb_delay.maxDelay(), total, driver_cell->name.c_str(ctx),
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driver.port.c_str(ctx));
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auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
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total += net_delay;
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auto driver_loc = ctx->getBelLocation(driver_cell->bel);
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auto sink_loc = ctx->getBelLocation(sink_cell->bel);
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log_info("%4d %4d Net %s budget %d (%d,%d) -> (%d,%d)\n", net_delay, total, net->name.c_str(ctx),
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sink->budget, driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
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log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
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last_port = sink->port;
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}
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log_break();
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2018-07-26 13:10:26 +08:00
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}
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}
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2018-08-04 13:39:25 +08:00
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delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
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log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));
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2018-08-04 14:39:42 +08:00
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if (print_histogram) {
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constexpr unsigned num_bins = 20;
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unsigned bar_width = 60;
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auto min_slack = slack_histogram.begin()->first;
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auto max_slack = slack_histogram.rbegin()->first;
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auto bin_size = (max_slack - min_slack) / num_bins;
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std::vector<unsigned> bins(num_bins+1);
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unsigned max_freq = 0;
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for (const auto& i : slack_histogram) {
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auto& bin = bins[(i.first-min_slack) / bin_size];
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bin += i.second;
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max_freq = std::max(max_freq, bin);
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}
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bar_width = std::min(bar_width, max_freq);
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log_break();
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log_info("Slack histogram:\n");
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log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
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for (unsigned i = 0; i < bins.size(); ++i)
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log_info("%6d < ps < %6d |%s\n", min_slack + bin_size*i, min_slack + bin_size*(i+1), std::string(bins[i] * bar_width / max_freq, '*').c_str());
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}
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2018-07-26 09:21:39 +08:00
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}
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2018-06-20 17:53:49 +08:00
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NEXTPNR_NAMESPACE_END
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